CTNF 18/050,944 CTNF 96330 Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/1/2026 has been entered. Remarks This Office Action is responsive to Applicants' Amendment filed on June 1, 2026, in which claims 1, 11, and 21 are currently amended. Claims 1-25 are currently pending. Response to Arguments Applicant’s arguments with respect to rejection of claims 1-25 under 35 U.S.C. 102/103 based on amendment have been considered and are persuasive. The argument is moot in view of a new ground of rejection set forth below. 07-30-03-h AIA Claim Interpretation 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: Claim 11, "a compute block configured to" Claim 11, "A DMA engine configured to" Claim 11, "An acceleration module configured to" Claim 21, "A compiler configured to" Claim 21, "a DMA engine configured to" Claim 21, "An acceleration module configured to" Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. A “DMA engine” is a known structural term in the art and the instant claims and specification provide sufficient structure for “compute block”, “acceleration module”, and “compiler”. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-5, 11-14, 21, 22, and 25 are rejected under U.S.C. §103 as being unpatentable over the combination of Persson (US11907855B2) and Redfern (US20180248562A1). PNG media_image1.png 432 378 media_image1.png Greyscale FIG. 2 of Persson Regarding claim 1, Persson teaches A method for deep learning, comprising: receiving an activation transfer task for writing activations of a convolution from a local memory of a compute block performing the convolution into an external memory; ([Col. 1 l. 35-67] "there is provided a computer implemented method of storing and retrieving feature map data of a neural network the method comprising transferring feature map data between local storage and external storage") the local memory arranged inside the compute block, the external memory arranged outside the compute block; ([Col. 5 l. 32-55] "The NPU comprises local storage circuitry and processing circuitry. In examples, the local storage circuitry is static random access memory (SRAM). The data processing system also comprises external storage circuitry where data is stored to be transferred to the local storage circuitry for processing. In examples, the external storage circuitry is dynamic random access memory (DRAM)." See also FIG. 2. NPU interpreted as compute block ) reading, by a direct memory access (DMA) engine of an accelerator, the activations from the local memory; ([Col. 1 l. 35-67] "receiving a first portion of feature map data from the local storage" [Col. 10 l. 35-45] "The controller 501 generates control data for the DMA 403 to receive feature map data from the SRAM 406" Feature map portion interpreted as synonymous with activation. Persson explicitly states that the controller generates control data for the DMA to receive feature map data from SRAM 406 and that the received data is an OFM stripe. In the FIG. 2 system, the DMA facilitates reading and writing between DRAM and SRAM, and the NPU is explicitly described as a neural-network/AI accelerator ) compressing, by an acceleration module of the accelerator, the activations to generate compressed activation data; ([Col. 1 l. 35-67] "compressing the subportions of feature map data to produce a first plurality of sections of compressed feature map data, each section corresponding to a respective subportion" [Col. 10 l. 35-40] "The OFM stripe is retrieved from the SRAM 406 and transferred to the compressor 502" Persson explicitly states that the OFM stripe retrieved from SRAM is transferred to compressor 502 which splits the stripe into subportions and compresses them to generate sections of compressed feature map data. The compressor is interpreted as the acceleration module inside the DMA circuitry of the NPU ) writing the compressed activation data into the external memory; and ([Col. 1 l. 35-67] "instructing the storage of the first plurality of sections of compressed feature map data into the external storage" [Col. 12 l. 10-15] "to write the plurality of sections of compressed feature map data to the DRAM 402" Persson discloses that after compression the compressed sections are transferred to write buffer 503, which generates a data stream used to write the compressed sections into DRAM 402, specifically into DRAM cells sized for those sections ) receiving another activation transfer task for writing the activations from the external memory into the local memory; ([Col. 9 l. 18-20] "The OFM stripe related to one neural network layer is stored in the external storage where it is transferred back to the local storage to be processed as an IFM stripe of a different neural network layer." [Col. 9 l. 24-31] "FIG. 4 illustrates a flow diagram representing a method of address data. receiving feature map data of a neural network in accordance with an example of the present disclosure. In examples, the neural network is processed using the data processing system previously discussed in FIG. 2. At step 401 of the flow diagram the DMA receives a plurality of sections of compressed feature map data from external 30 storage." Persson explicitly discloses a second-stage inbound transfer in which data previously stored externally is brought back into local storage for later-layer processing ) reading, by the DMA engine from the external memory, the compressed activation data based on the size of the compressed activation data. ([Col. 1 l. 35-67] "receiving a second plurality of sections of compressed feature map data from the external storage"). However, Persson does not explicitly teach writing, by the acceleration module, data indicating a size of the compressed activation data into the local memory. in response to receiving the another activation transfer task, reading, by the DMA engine from the local memory, the data indicating the size of the compressed activation data; . Redfern, in the same field of endeavor, teaches writing, by the acceleration module, data indicating a size of the compressed activation data into the local memory. ([Abstract] "A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed" [¶0211] "Selection of the optimal 1D compressed superblock (CSB) size may be computed as follows. If (ceil((number of bytes in the 1D compressed superblock)/128))<(number of 1D uncompressed blocks) then compression is beneficial. The 1D compressed superblock size is never larger than the size of the 1D uncompressed blocks as the compression information (compression method per original 1D uncompressed block and final 1D compressed superblock length) is separately locally stored. This simplifies LDM allocation as an upper bound is always known. This also simplifies EDM to LDM movement of the compressed data via a DMA as the transfer length can be specified at the start." Final compressed superblock length interpreted as size data. "Separately locally stored" maps to writing size metadata into local memory. CNN feature-map data and CSB interpreted as synonymous with activation data ) in response to receiving the another activation transfer task, reading, by the DMA engine from the local memory, the data indicating the size of the compressed activation data; and ([¶0214] "A 0-tag method for compression with local memory storage of compression parameters and individual block compression and no compression decisions is implemented. This ensures the 1D compressed superblock size is not larger than the 1D uncompressed blocks size and allows compression to be agnostic to the fixed point precision. This also allows the subsequent DMA in the decompression direction from EDM to LDM to know the read size ahead of time" [¶0250] "(2) Reading the compression mode vector (CMV) from the LDM (4602);"). Persson as well as Redfern are directed towards convolutional neural network accelerators. Therefore, Persson as well as Redfern are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Persson with the teachings of Redfern by storing the compression information locally in addition to in external memory so that the subsequent EDM to LDM DMA knows the read size at the start. Redfern provides as additional motivation for combination ([¶0211] "This simplifies LDM allocation as an upper bound is always known. This also simplifies EDM to LDM movement of the compressed data via a DMA as the transfer length can be specified at the start."). Regarding claim 2, the combination of Persson, and Redfern teaches The method of claim 1, further comprising: decompressing, by the acceleration module, the compressed activation data to restore the activations; and (Persson [Col. 9 l. 55-65] "At step 402 the DMA decompresses the plurality of sections of feature map data to produce a set of subportions of a portion of feature map data") writing, by the acceleration module, the activations into the local memory. (Persson [Col. 1 l. 35-67] "decompressing the second plurality of sections to produce a second set of subportions of the second portion of feature map data; and storing the second portion of feature map data in local storage,"). Regarding claim 3, the combination of Persson, and Redfern teaches The method of claim 2, wherein reading the compressed activation data from the external memory comprises: reading the compressed activation data from the external memory after reading the data indicating the size of the compressed activation data from the local memory. (Persson [Col. 9 l. 55-65] "the plurality of sections of feature map data comprise a corresponding plurality of blocks of data. The blocks of data comprise payload data and header data. As demonstrated by FIG. 1 , the header data 107 precedes the payload data 108 such that the header data 107 is read before the payload data 108. As discussed previously, the header data comprises a data element indicative of the data size of the payload data comprising the section of compressed feature map data. This indicates to the DMA, how much of the section of compressed feature map data to read, to retrieve the payload data for decompression. The data element is used to ensure that the payload data is read"). Regarding claim 4, the combination of Persson, and Redfern teaches The method of claim 1, wherein the data indicating the size of the compressed activation data indicates a number of bytes in the compressed activation data. (Persson [Col. 5 l. 60-66] "the feature map has dimensions 32 (height)×32 (width)×64 (depth) which is represented by feature map data having a set of elements. Each element represents a pixel value of the image 101. The feature map dimensions represents how the pixels are arranged in the image 101. Each element has a data size of 8 bytes. The data size of the feature map data is therefore approximately 524 kilobytes"). Regarding claim 5, the combination of Persson, and Redfern teaches The method of claim 1, wherein the activations are stored in a first storage unit in the local memory, and the data indicating the size of the compressed activation data is stored in a second storage unit in the local memory. (Redfern [¶0229] "(1) Perform 2D-to-1D translation of 2D uncompressed data (2DU) contained in LDM to generate 1D uncompressed data (1DU)" [¶0211] "(compression method per original 1D uncompressed block and final 1D compressed superblock length) is separately locally stored" Redfern uses distinct LDM-resident objects/regions: source LDM tile 4121, CMV 4123, CSB 4124 ). Regarding claim 11, Persson teaches A deep neural network (DNN) accelerator, comprising: a compute block configured to perform a convolution, the compute block comprising a local memory; ([Col. 7 l. 55-60] "MCEs are configured to perform convolutions between an IFM and weight data to generate an OFM" See FIG. 2. NPU 204 interpreted as compute block ) a direct memory access (DMA) engine configured to: receive an activation transfer task for writing activations of the convolution from the local memory into an external memory associated with the DNN accelerator, ([Col. 6 l. 20-25] "this is achieved by using a direct memory access (DMA) which facilitates the reading and writing of data between the local storage circuitry and external storage circuitry" See also FIG. 2 ) the local memory arranged inside the compute block, the external memory arranged outside the compute block, and ([Col. 5 l. 32-55] "The NPU comprises local storage circuitry and processing circuitry. In examples, the local storage circuitry is static random access memory (SRAM). The data processing system also comprises external storage circuitry where data is stored to be transferred to the local storage circuitry for processing. In examples, the external storage circuitry is dynamic random access memory (DRAM)." See also FIG. 2. NPU interpreted as compute block ) read the activations from the local memory; and ([Col. 1 l. 35-67] "receiving a first portion of feature map data from the local storage" Feature map portion interpreted as synonymous with activation ) an acceleration module configured to: compress the activations to generate compressed activation data, ([Col. 1 l. 35-67] "compressing the subportions of feature map data to produce a first plurality of sections of compressed feature map data, each section corresponding to a respective subportion") write the compressed activation data into the external memory, and ([Col. 1 l. 35-67] "instructing the storage of the first plurality of sections of compressed feature map data into the external storage") wherein: the DMA engine is further configured to: receive another activation transfer task for writing the activations from the external memory into the local memory, ([Col. 9 l. 18-20] "The OFM stripe related to one neural network layer is stored in the external storage where it is transferred back to the local storage to be processed as an IFM stripe of a different neural network layer." [Col. 9 l. 24-31] "FIG. 4 illustrates a flow diagram representing a method of address data. receiving feature map data of a neural network in accordance with an example of the present disclosure. In examples, the neural network is processed using the data processing system previously discussed in FIG. 2. At step 401 of the flow diagram the DMA receives a plurality of sections of compressed feature map data from external 30 storage." Persson explicitly discloses a second-stage inbound transfer in which data previously stored externally is brought back into local storage for later-layer processing ) wherein the acceleration module is further configured to read, from the external memory, the compressed activation data based on the size of the compressed activation data. ([Col. 1 l. 35-67] "receiving a second plurality of sections of compressed feature map data from the external storage"). However, Persson does not explicitly teach write data indicating a size of the compressed activation data in the local memory. in response to receiving the another activation transfer task, read, from the local memory, the data indicating the size of the compressed activation data, . Redfern, in the same field of endeavor, teaches write data indicating a size of the compressed activation data in the local memory. ([Abstract] "A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed" [¶0211] "Selection of the optimal 1D compressed superblock (CSB) size may be computed as follows. If (ceil((number of bytes in the 1D compressed superblock)/128))<(number of 1D uncompressed blocks) then compression is beneficial. The 1D compressed superblock size is never larger than the size of the 1D uncompressed blocks as the compression information (compression method per original 1D uncompressed block and final 1D compressed superblock length) is separately locally stored. This simplifies LDM allocation as an upper bound is always known. This also simplifies EDM to LDM movement of the compressed data via a DMA as the transfer length can be specified at the start." Final compressed superblock length interpreted as size data. "Separately locally stored" maps to writing size metadata into local memory. CNN feature-map data and CSB interpreted as synonymous with activation data ) in response to receiving the another activation transfer task, read, from the local memory, the data indicating the size of the compressed activation data, ([¶0214] "A 0-tag method for compression with local memory storage of compression parameters and individual block compression and no compression decisions is implemented. This ensures the 1D compressed superblock size is not larger than the 1D uncompressed blocks size and allows compression to be agnostic to the fixed point precision. This also allows the subsequent DMA in the decompression direction from EDM to LDM to know the read size ahead of time" [¶0250] "(2) Reading the compression mode vector (CMV) from the LDM (4602);"). Persson as well as Redfern are directed towards convolutional neural network accelerators. Therefore, Persson as well as Redfern are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Persson with the teachings of Redfern by storing the compression information locally in addition to in external memory so that the subsequent EDM to LDM DMA knows the read size at the start. Redfern provides as additional motivation for combination ([¶0211] "This simplifies LDM allocation as an upper bound is always known. This also simplifies EDM to LDM movement of the compressed data via a DMA as the transfer length can be specified at the start."). Regarding claim 12, the combination of Persson, and Redfern teaches The DNN accelerator of claim 11, the acceleration module is further configured to: decompress the compressed activation data to restore the activations, (Persson [Col. 9 l. 55-65] "At step 402 the DMA decompresses the plurality of sections of feature map data to produce a set of subportions of a portion of feature map data") and write the activations into the local memory. (Persson [Col. 1 l. 35-67] "decompressing the second plurality of sections to produce a second set of subportions of the second portion of feature map data; and storing the second portion of feature map data in local storage,"). Regarding claim 13, the combination of Persson, and Redfern teaches The DNN accelerator of claim 12, wherein the DMA engine is configured to read the compressed activation data from the external memory after reading the data indicating the size of the compressed activation data from the local memory. (Persson [Col. 9 l. 55-65] "the plurality of sections of feature map data comprise a corresponding plurality of blocks of data. The blocks of data comprise payload data and header data. As demonstrated by FIG. 1 , the header data 107 precedes the payload data 108 such that the header data 107 is read before the payload data 108. As discussed previously, the header data comprises a data element indicative of the data size of the payload data comprising the section of compressed feature map data. This indicates to the DMA, how much of the section of compressed feature map data to read, to retrieve the payload data for decompression. The data element is used to ensure that the payload data is read"). Regarding claim 14, the combination of Persson, and Redfern teaches The DNN accelerator of claim 11, wherein the data indicating the size of the compressed activation data indicates a number of bytes in the compressed activation data. (Persson [Col. 5 l. 60-66] "the feature map has dimensions 32 (height)×32 (width)×64 (depth) which is represented by feature map data having a set of elements. Each element represents a pixel value of the image 101. The feature map dimensions represents how the pixels are arranged in the image 101. Each element has a data size of 8 bytes. The data size of the feature map data is therefore approximately 524 kilobytes"). Regarding claim 21, Persson teaches A system for deep learning, the system comprising: a first memory; (See FIG. 2. DRAM interpreted as first memory) a compiler configured to generate an activation transfer task for transferring activations of a convolution from a second memory to the first memory ([Col. 11 l. 45-65] "The compiler processes source code or assembly code implementing a neural network with layers to determine a set of instructions used by hardware components to carry out processes during clock cycles of the data processing system. The set of instructions comprise instructions related to each layer of the neural network. The instructions related to each layer of the neural network are used by the hardware components of the data processing system, such as the DMA, to schedule the transfer of the feature map data between local storage and external storage during the processing of the layer of the neural network") and to generate another activation transfer task for transferring the activations from the first memory into the second memory ([Col. 9 l. 18-20] "The OFM stripe related to one neural network layer is stored in the external storage where it is transferred back to the local storage to be processed as an IFM stripe of a different neural network layer." [Col. 9 l. 24-31] "FIG. 4 illustrates a flow diagram representing a method of address data. receiving feature map data of a neural network in accordance with an example of the present disclosure. In examples, the neural network is processed using the data processing system previously discussed in FIG. 2. At step 401 of the flow diagram the DMA receives a plurality of sections of compressed feature map data from external 30 storage." Persson explicitly discloses a second-stage inbound transfer in which data previously stored externally is brought back into local storage for later-layer processing ) a compute block configured to perform the convolution, the compute block comprising the second memory; ([Col. 7 l. 55-60] "MCEs are configured to perform convolutions between an IFM and weight data to generate an OFM" See FIG. 2. NPU 204 interpreted as compute block. SRAM interpreted as second memory. ) the second memory arranged inside the compute block, the first memory arranged outside the compute block; ([Col. 5 l. 32-55] "The NPU comprises local storage circuitry and processing circuitry. In examples, the local storage circuitry is static random access memory (SRAM). The data processing system also comprises external storage circuitry where data is stored to be transferred to the local storage circuitry for processing. In examples, the external storage circuitry is dynamic random access memory (DRAM)." See also FIG. 2. NPU interpreted as compute block ) a direct memory access (DMA) engine configured to: receive the activation transfer task, and ([Col. 6 l. 20-25] "this is achieved by using a direct memory access (DMA) which facilitates the reading and writing of data between the local storage circuitry and external storage circuitry" See also FIG. 2 ) read the activations from the second memory; and ([Col. 1 l. 35-67] "receiving a first portion of feature map data from the local storage" Feature map portion interpreted as synonymous with activation ) an acceleration module configured to: compress the activations to generate compressed activation data, ([Col. 1 l. 35-67] "compressing the subportions of feature map data to produce a first plurality of sections of compressed feature map data, each section corresponding to a respective subportion") write the compressed activation data into the first memory, and ([Col. 1 l. 35-67] "instructing the storage of the first plurality of sections of compressed feature map data into the external storage") wherein the DMA engine is further configured to: receive the another activation transfer task, ([Col. 9 l. 18-20] "The OFM stripe related to one neural network layer is stored in the external storage where it is transferred back to the local storage to be processed as an IFM stripe of a different neural network layer." [Col. 9 l. 24-31] "FIG. 4 illustrates a flow diagram representing a method of address data. receiving feature map data of a neural network in accordance with an example of the present disclosure. In examples, the neural network is processed using the data processing system previously discussed in FIG. 2. At step 401 of the flow diagram the DMA receives a plurality of sections of compressed feature map data from external 30 storage." Persson explicitly discloses a second-stage inbound transfer in which data previously stored externally is brought back into local storage for later-layer processing ) wherein the acceleration module is further configured to read, from the first memory, the compressed activation data based on the size of the compressed activation data. ([Col. 1 l. 35-67] "receiving a second plurality of sections of compressed feature map data from the external storage"). However, Persson does not explicitly teach write data indicating a size of the compressed activation data in the second memory. and in response to receiving the another activation transfer task, read, from the second memory, the data indicating the size of the compressed activation data . Redfern, in the same field of endeavor, teaches write data indicating a size of the compressed activation data in the second memory. ([¶0214] "A 0-tag method for compression with local memory storage of compression parameters and individual block compression and no compression decisions is implemented. This ensures the 1D compressed superblock size is not larger than the 1D uncompressed blocks size and allows compression to be agnostic to the fixed point precision. This also allows the subsequent DMA in the decompression direction from EDM to LDM to know the read size ahead of time" [¶0250] "(2) Reading the compression mode vector (CMV) from the LDM (4602);") and in response to receiving the another activation transfer task, read, from the second memory, the data indicating the size of the compressed activation data, ([¶0214] "A 0-tag method for compression with local memory storage of compression parameters and individual block compression and no compression decisions is implemented. This ensures the 1D compressed superblock size is not larger than the 1D uncompressed blocks size and allows compression to be agnostic to the fixed point precision. This also allows the subsequent DMA in the decompression direction from EDM to LDM to know the read size ahead of time" [¶0250] "(2) Reading the compression mode vector (CMV) from the LDM (4602);"). Persson as well as Redfern are directed towards convolutional neural network accelerators. Therefore, Persson as well as Redfern are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Persson with the teachings of Redfern by storing the compression information locally in addition to in external memory so that the subsequent EDM to LDM DMA knows the read size at the start. Redfern provides as additional motivation for combination ([¶0211] "This simplifies LDM allocation as an upper bound is always known. This also simplifies EDM to LDM movement of the compressed data via a DMA as the transfer length can be specified at the start."). Regarding claim 22, the combination of Persson, and Redfern teaches The system of claim 21, wherein: the acceleration module is further configured to: decompress the compressed activation data to restore the activations, (Persson [Col. 9 l. 55-65] "At step 402 the DMA decompresses the plurality of sections of feature map data to produce a set of subportions of a portion of feature map data") and write the activations into the second memory. (Persson [Col. 1 l. 35-67] "decompressing the second plurality of sections to produce a second set of subportions of the second portion of feature map data; and storing the second portion of feature map data in local storage,"). Regarding claim 25, the combination of Persson, and Redfern teaches The system of claim 21, wherein: the plurality of activation vector comprises a first activation vector and a second activation vector, non-zero valued activations of the first activation vector are arranged before non-zero valued activations of the second activation vector, and (Persson [Col. 5 l. 7-30] "The number and/or rate of external memory accesses can also be reduced by rearranging the order in which feature map data of the neural network is processed relative to the order in which the layers of the neural network are arranged. For example, once a first OFM stripe is produced from a first process and stored in the local storage circuitry, to avoid a series of memory accesses it may again be fetched for a second process instead of transferred to external storage. This occurs if the arrangement of the neural network indicates that a later layer would result in the first OFM stripe being processed by the second process." Persson explicitly discloses processing the non-zero valued activations of one layer before another layer ) the compressed activation data further comprises a zero valued datapoint between the non-zero valued activations of the first activation vector and the non-zero valued activations of the second activation vector. (Persson [Col. 7 l. 5-12] "the sections of compressed feature map data comprise a portion of storage size which contains zero-value data which is not accessed for transfer."). Claims 6, 7, 8, and 10 are rejected under U.S.C. §103 as being unpatentable over the combination of Persson and Redfern and Vivancos (WO2021226720A1). Regarding claim 6, the combination of Persson, and Redfern teaches The method of claim 1, wherein the compressed activation data comprises: non-zero valued activations in a plurality of activation vectors, (Persson [Col. 9 l. 55-Col. 10 l. 17] "the one or more compression techniques comprise the removal of zero-value elements from the subportions of feature map data to produce compressed feature map data during compression. The header data comprises compression data indicating where zero-value elements are to be returned to the payload data during the decompression") each activation vector comprises a sequence of activations corresponding to different channels of the convolution, and (Persson [Col. 4 l. 13-40] "The depth dimension of the feature map is representative of multiple parameter values associated with each pixel, such as intensity values which make up the different color channels. "). However, the combination of Persson, and Redfern doesn't explicitly teach sparsity bitmaps of the plurality of activation vectors, wherein each sparsity bitmap corresponds to a respective activation vector of the plurality of activation vectors and comprises a sequence of bits, each of which corresponds to an activation in the respective activation vector and indicates whether the activation has a zero value or non-zero value. . Vivancos, in the same field of endeavor, teaches sparsity bitmaps of the plurality of activation vectors, wherein each sparsity bitmap corresponds to a respective activation vector of the plurality of activation vectors and comprises a sequence of bits, each of which corresponds to an activation in the respective activation vector and indicates whether the activation has a zero value or non-zero value. ([¶0090] "To take advantage of sparsity, the imap and the fmap omit zero values storing non-zero values as ((value), (skip)) pairs where (skip) is the number of zero values omitted after each. By using these (skip) fields, SCNN deduces the original position of each value and maps the products to their respective accumulators" skip field interpreted as sparsity bitmap indicating whether the activation has a zero or non-zero value ). Persson as well as Vivancos are directed towards compression based neural network accelerators. Therefore, Persson as well as Vivancos are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Persson with the teachings of Vivancos by using the compressor size/width metadata storage scheme in Vivancos to decouple the metadata from a DRAM resident header (simple substitution). Vivancos provides as additional motivation for combination ([¶0079] "Advantageously, embodiments of the present disclosure provide a lossless on-chip compression scheme which, for example: (1) can support the relatively long sequential accesses generally needed by neural networks, (2) can support multiple wide accesses to maintain high utilisation of processing units, (3) allows decoding to happen just before the processing units, thus keeping data compressed for as long as possible, and (4) takes advantage of value behaviour that is typical of neural networks"). This motivation for combination also applies to the remaining claims which depend on this combination. Regarding claim 7, the combination of Persson, Redfern, and Vivancos teaches The method of claim 6, wherein compressing the activations to generate compressed activation data comprises: forming a plurality of data packages from the non-zero valued activations and the sparsity bitmaps, wherein each data package comprises a sparsity bitmap and non-zero valued activations in an activation vector corresponding to the sparsity bitmap. (Vivancos [¶0090] "To take advantage of sparsity, the imap and the fmap omit zero values storing non-zero values as ((value), (skip)) pairs where (skip) is the number of zero values omitted after each. By using these (skip) fields, SCNN deduces the original position of each value and maps the products to their respective accumulators" skip field interpreted as sparsity bitmap indicating whether the activation has a zero or non-zero value ). Regarding claim 8, the combination of Persson, Redfern, and Vivancos teaches The method of claim 7, wherein each data package further comprises a header that indicates a number of the non-zero valued activations in the activation vector. (Persson [Col. 9 l. 55-Col. 10 l. 17] "the one or more compression techniques comprise the removal of zero-value elements from the subportions of feature map data to produce compressed feature map data during compression. The header data comprises compression data indicating where zero-value elements are to be returned to the payload data during the decompression" Persson explicitly packs a number and indicates that only non-zero activations are packed ). Regarding claim 10, the combination of Persson, Redfern, and Vivancos teaches The method of claim 6, wherein: the plurality of activation vectors comprises a first activation vector and a second activation vector, non-zero valued activations of the first activation vector are arranged before non-zero valued activations of the second activation vector, and (Persson [Col. 5 l. 7-30] "The number and/or rate of external memory accesses can also be reduced by rearranging the order in which feature map data of the neural network is processed relative to the order in which the layers of the neural network are arranged. For example, once a first OFM stripe is produced from a first process and stored in the local storage circuitry, to avoid a series of memory accesses it may again be fetched for a second process instead of transferred to external storage. This occurs if the arrangement of the neural network indicates that a later layer would result in the first OFM stripe being processed by the second process." Persson explicitly discloses processing the non-zero valued activations of one layer before another layer ) the compressed activation data further comprises a zero valued datapoint between the non-zero valued activations of the first activation vector and the non-zero valued activations of the second activation vector. (Persson [Col. 7 l. 5-12] "the sections of compressed feature map data comprise a portion of storage size which contains zero-value data which is not accessed for transfer."). The combination of Persson and Redfern as well as Vivancos are directed towards compression based neural network accelerators. Therefore, the combination of Persson and Redfern as well as Vivancos are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of the combination of Persson and Redfern with the teachings of Vivancos by using the compressor size/width metadata storage scheme in Vivancos to decouple the metadata from a DRAM resident header (simple substitution). Vivancos provides as additional motivation for combination ([¶0079] "Advantageously, embodiments of the present disclosure provide a lossless on-chip compression scheme which, for example: (1) can support the relatively long sequential accesses generally needed by neural networks, (2) can support multiple wide accesses to maintain high utilisation of processing units, (3) allows decoding to happen just before the processing units, thus keeping data compressed for as long as possible, and (4) takes advantage of value behaviour that is typical of neural networks"). This motivation for combination also applies to the remaining claims which depend on this combination. Claim 9 is rejected under U.S.C. §103 as being unpatentable over the combination of Persson and Redfern and Vivancos and Aimar (“NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps”, 2019). Regarding claim 9, the combination of Persson, Redfern, and Vivancos teaches The method of claim 8. However, the combination of Persson, Redfern, and Vivancos doesn't explicitly teach the header is arranged between the sparsity bitmap and the non-zero valued activations in the activation vector. Aimar, in the same field of endeavor, teaches the header is arranged between the sparsity bitmap and the non-zero valued activations in the activation vector. ([p. 3 §IIIA] "NullHop uses a novel sparse matrix compression algorithm. This algorithm produces an average compression level that is higher than that obtained from using the method in [12] and is easier to decode than the Huffman coding used in [13]. The coding uses two elements: a sparsity map (SM) and a nonzero value list (NZVL). The SM is a 3-D mask, having the same number of entries as a number of pixels in the feature maps. Each binary entry in the SM is 1 if the corresponding pixel is nonzero and 0 otherwise" Aimar discloses sparsity map and non-zero activations packed together with the number of non-zero value activations encoded among the sparsity mask and non-zero activations. ). The combination of Persson, Redfern, and Vivancos as well as Aimar are directed towards convolutional neural network accelerators. Therefore, the combination of Persson, Redfern, and Vivancos as well as Aimar are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of the combination of Persson, Redfern, and Vivancos with the teachings of Aimar by using a sparsity map and non-zero value list. Aimar provides as additional motivation for combination ([p. 4] “Although our SM algorithm produces an equivalent level of compression as the Huffman coding used in [13], our data structure permits an easier decoding during the computation, allowing the accelerator to operate directly on compressed representations”). Claim 15 is rejected under U.S.C. §103 as being unpatentable over the combination of Persson and Redfern and Rutishauser (“An On-the-Fly Feature Map Compression Engine for Background Memory Access Cost Reduction in DNN Inference”, 2020). Regarding claim 15, the combination of Persson, and Redfern teaches The DNN accelerator of claim 11. However, the combination of Persson, and Redfern doesn't explicitly teach wherein the activations are stored in a first storage unit in the local memory, and the data indicating the size of the compressed activation data is stored in a second storage unit in the local memory. Rutishauser, in the same field of endeavor, teaches the activations are stored in a first storage unit in the local memory, and the data indicating the size of the compressed activation data is stored in a second storage unit in the local memory. ([p. 11] "book-keeping metadata in L2 to keep track of the size and location of the different compressed streams […] consider the transfer from L2 to L1 memory of M = 8 feature maps divided into NT = 2 stripes by a decompressing DMA engine which processes 4 streams in parallel" Rutishauser stores feature maps in L1 and L2 memory, the metadata including feature map size being stored in L2 memory, both L1 and L2 memory interpreted as local memory. ). The combination of Persson and Redfern as well as Rutishauser are directed towards convolutional neural network feature map compression. Therefore, the combination of Persson and Redfern as well as Rutishauser are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of the combination of Persson and Redfern with the teachings of Rutishauser by storing the activations and activation size in different units of local memory. Rutishauser provides as additional motivation for combination ([p. 11 §4.2] "Once processing of the first tile is completed, the transfer of the second tile is started by restoring the first saved context. Compressing transfers from L2 to L1 memory are performed analogously. This approach has the advantage of avoiding the degradation of the compression ratio through edge effects and eliminating the book-keeping overhead inherent to compressed striping. Furthermore, it allows for different (one-dimensional) striping schemes to be applied at will throughout the network, as the feature maps are stored contiguously in L2 and can be split arbitrarily"). Claims 16, 17, 18, 19, 20, 23, and 24 are rejected under U.S.C. §103 as being unpatentable over the combination of Persson, Redfern, and Aimar. Regarding claim 16, the combination of Persson, and Redfern teaches The DNN accelerator of claim 11, wherein the compressed activation data comprises: non-zero valued activations in a plurality of activation vectors, each activation vector comprises a sequence of activations corresponding to different channels of the convolution, and (Persson [Col. 9 l. 55-Col. 10 l. 17] "the one or more compression techniques comprise the removal of zero-value elements from the subportions of feature map data to produce compressed feature map data during compression. The header data comprises compression data indicating where zero-value elements are to be returned to the payload data during the decompression") sparsity bitmaps of the plurality of activation vectors, (Persson [Col. 4 l. 13-40] "The depth dimension of the feature map is representative of multiple parameter values associated with each pixel, such as intensity values which make up the different color channels. "). However, the combination of Persson, and Redfern doesn't explicitly teach wherein each sparsity bitmap corresponds to a respective activation vector of the plurality of activation vectors and comprises a sequence of bits, each of which corresponds to an activation in the respective activation vector and indicates whether the activation has a zero value or non-zero value. Aimar, in the same field of endeavor, teaches wherein each sparsity bitmap corresponds to a respective activation vector of the plurality of activation vectors and comprises a sequence of bits, each of which corresponds to an activation in the respective activation vector and indicates whether the activation has a zero value or non-zero value. ([p. 3 §IIIA] "NullHop uses a novel sparse matrix compression algorithm. This algorithm produces an average compression level that is higher than that obtained from using the method in [12] and is easier to decode than the Huffman coding used in [13]. The coding uses two elements: a sparsity map (SM) and a nonzero value list (NZVL). The SM is a 3-D mask, having the same number of entries as a number of pixels in the feature maps. Each binary entry in the SM is 1 if the corresponding pixel is nonzero and 0 otherwise"). the combination of Persson and Redfern as well as Aimar are directed towards convolutional neural network accelerators. Therefore, the combination of Persson and Redfern as well as Aimar are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of the combination of Persson and Redfern with the teachings of Aimar by using a sparsity map and non-zero value list. Aimar provides as additional motivation for combination ([p. 4] “Although our SM algorithm produces an equivalent level of compression as the Huffman coding used in [13], our data structure permits an easier decoding during the computation, allowing the accelerator to operate directly on compressed representations”). Regarding claim 17, the combination of Persson, Redfern, and Aimar teaches The DNN accelerator of claim 16, wherein the accelerator module is configured to compress the activations to generate compressed activation data by forming a plurality of data packages from the non-zero valued activations and the sparsity bitmaps, wherein each data package comprises a sparsity bitmap and non-zero valued activations in an activation vector corresponding to the sparsity bitmap. (Aimar [p. 3 §IIIA] "NullHop uses a novel sparse matrix compression algorithm. This algorithm produces an average compression level that is higher than that obtained from using the method in [12] and is easier to decode than the Huffman coding used in [13]. The coding uses two elements: a sparsity map (SM) and a nonzero value list (NZVL). The SM is a 3-D mask, having the same number of entries as a number of pixels in the feature maps. Each binary entry in the SM is 1 if the corresponding pixel is nonzero and 0 otherwise"). Regarding claim 18, the combination of Persson, Redfern, and Aimar teaches The DNN accelerator of claim 17, wherein each data package further comprises a header that indicates a number of the non-zero valued activations in the activation vector. (Persson [Col. 9 l. 55-Col. 10 l. 17] "the one or more compression techniques comprise the removal of zero-value elements from the subportions of feature map data to produce compressed feature map data during compression. The header data comprises compression data indicating where zero-value elements are to be returned to the payload data during the decompression" Persson explicitly packs a number and indicates that only non-zero activations are packed ). Regarding claim 19, the combination of Persson, Redfern, and Aimar teaches The DNN accelerator of claim 18, wherein the header is arranged between the sparsity bitmap and the non-zero valued activations in the activation vector. (Aimar [p. 3 §IIIA] "NullHop uses a novel sparse matrix compression algorithm. This algorithm produces an average compression level that is higher than that obtained from using the method in [12] and is easier to decode than the Huffman coding used in [13]. The coding uses two elements: a sparsity map (SM) and a nonzero value list (NZVL). The SM is a 3-D mask, having the same number of entries as a number of pixels in the feature maps. Each binary entry in the SM is 1 if the corresponding pixel is nonzero and 0 otherwise" Aimar discloses sparsity map and non-zero activations packed together with the number of non-zero value activations encoded among the sparsity mask and non-zero activations. ). Regarding claim 20, the combination of Persson, Redfern, and Aimar teaches The DNN accelerator of claim 16, wherein: the plurality of activation vectors comprises a first activation vector and a second activation vector, non-zero valued activations of the first activation vector are arranged before non-zero valued activations of the second activation vector, and (Persson [Col. 5 l. 7-30] "The number and/or rate of external memory accesses can also be reduced by rearranging the order in which feature map data of the neural network is processed relative to the order in which the layers of the neural network are arranged. For example, once a first OFM stripe is produced from a first process and stored in the local storage circuitry, to avoid a series of memory accesses it may again be fetched for a second process instead of transferred to external storage. This occurs if the arrangement of the neural network indicates that a later layer would result in the first OFM stripe being processed by the second process." Persson explicitly discloses processing the non-zero valued activations of one layer before another ) the compressed activation data further comprises a zero valued datapoint between the non-zero valued activations of the first activation vector and the non-zero valued activations of the second activation vector. (Persson [Col. 7 l. 5-12] "the sections of compressed feature map data comprise a portion of storage size which contains zero-value data which is not accessed for transfer."). Regarding claim 23, the combination of Persson, and Redfern teaches The system of claim 21, wherein the compressed activation data comprises: non-zero valued activations in a plurality of activation vectors, (Persson [Col. 9 l. 55-Col. 10 l. 17] "the one or more compression techniques comprise the removal of zero-value elements from the subportions of feature map data to produce compressed feature map data during compression. The header data comprises compression data indicating where zero-value elements are to be returned to the payload data during the decompression") each activation vector comprises a sequence of activations corresponding to different channels of the convolution, and (Persson [Col. 4 l. 13-40] "The depth dimension of the feature map is representative of multiple parameter values associated with each pixel, such as intensity values which make up the different color channels. "). However, the combination of Persson, and Redfern doesn't explicitly teach sparsity bitmaps of the plurality of activation vectors, wherein each sparsity bitmap corresponds to a respective activation vector of the plurality of activation vectors and comprises a sequence of bits, each of which corresponds to an activation in the respective activation vector and indicates whether the activation has a zero value or non-zero value. . Aimar, in the same field of endeavor, teaches sparsity bitmaps of the plurality of activation vectors, wherein each sparsity bitmap corresponds to a respective activation vector of the plurality of activation vectors and comprises a sequence of bits, each of which corresponds to an activation in the respective activation vector and indicates whether the activation has a zero value or non-zero value. ([p. 3 §IIIA] "NullHop uses a novel sparse matrix compression algorithm. This algorithm produces an average compression level that is higher than that obtained from using the method in [12] and is easier to decode than the Huffman coding used in [13]. The coding uses two elements: a sparsity map (SM) and a nonzero value list (NZVL). The SM is a 3-D mask, having the same number of entries as a number of pixels in the feature maps. Each binary entry in the SM is 1 if the corresponding pixel is nonzero and 0 otherwise"). the combination of Persson and Redfern as well as Aimar are directed towards convolutional neural network accelerators. Therefore, the combination of Persson and Redfern as well as Aimar are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of the combination of Persson and Redfern with the teachings of Aimar by using a sparsity map and non-zero value list. Aimar provides as additional motivation for combination ([p. 4] “Although our SM algorithm produces an equivalent level of compression as the Huffman coding used in [13], our data structure permits an easier decoding during the computation, allowing the accelerator to operate directly on compressed representations”). Regarding claim 24, the combination of Persson, Redfern, and Aimar teaches The system of claim 23, wherein the accelerator module is configured to compress the activations to generate compressed activation data by forming a plurality of data packages from the non-zero valued activations and the sparsity bitmaps, wherein each data package comprises a sparsity bitmap and non-zero valued activations in an activation vector corresponding to the sparsity bitmap. (Aimar [p. 3 §IIIA] "NullHop uses a novel sparse matrix compression algorithm. This algorithm produces an average compression level that is higher than that obtained from using the method in [12] and is easier to decode than the Huffman coding used in [13]. The coding uses two elements: a sparsity map (SM) and a nonzero value list (NZVL). The SM is a 3-D mask, having the same number of entries as a number of pixels in the feature maps. Each binary entry in the SM is 1 if the corresponding pixel is nonzero and 0 otherwise"). Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sabogol (“ReCoN: A Reconfigurable CNN Acceleration Framework for Hybrid Semantic Segmentation on Hybrid SoCs for Space Applications”, 2022) is directed towards a CNN accelerator with a DMA that has explicit stream size parameterization on the DMA . Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDNEY VINCENT BOSTWICK whose telephone number is (571)272-4720. The examiner can normally be reached M-F 7:30am-5:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Miranda Huang can be reached on (571)270-7092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIDNEY VINCENT BOSTWICK/Examiner, Art Unit 2124 Application/Control Number: 18/050,944 Page 2 Art Unit: 2124 Application/Control Number: 18/050,944 Page 3 Art Unit: 2124 Application/Control Number: 18/050,944 Page 4 Art Unit: 2124 Application/Control Number: 18/050,944 Page 5 Art Unit: 2124 Application/Control Number: 18/050,944 Page 6 Art Unit: 2124 Application/Control Number: 18/050,944 Page 7 Art Unit: 2124 Application/Control Number: 18/050,944 Page 8 Art Unit: 2124 Application/Control Number: 18/050,944 Page 9 Art Unit: 2124 Application/Control Number: 18/050,944 Page 10 Art Unit: 2124 Application/Control Number: 18/050,944 Page 11 Art Unit: 2124 Application/Control Number: 18/050,944 Page 12 Art Unit: 2124 Application/Control Number: 18/050,944 Page 13 Art Unit: 2124 Application/Control Number: 18/050,944 Page 14 Art Unit: 2124 Application/Control Number: 18/050,944 Page 15 Art Unit: 2124 Application/Control Number: 18/050,944 Page 16 Art Unit: 2124 Application/Control Number: 18/050,944 Page 17 Art Unit: 2124 Application/Control Number: 18/050,944 Page 18 Art Unit: 2124 Application/Control Number: 18/050,944 Page 19 Art Unit: 2124 Application/Control Number: 18/050,944 Page 20 Art Unit: 2124 Application/Control Number: 18/050,944 Page 21 Art Unit: 2124 Application/Control Number: 18/050,944 Page 22 Art Unit: 2124 Application/Control Number: 18/050,944 Page 23 Art Unit: 2124 Application/Control Number: 18/050,944 Page 24 Art Unit: 2124 Application/Control Number: 18/050,944 Page 25 Art Unit: 2124 Application/Control Number: 18/050,944 Page 26 Art Unit: 2124 Application/Control Number: 18/050,944 Page 27 Art Unit: 2124 Application/Control Number: 18/050,944 Page 28 Art Unit: 2124 Application/Control Number: 18/050,944 Page 29 Art Unit: 2124 Application/Control Number: 18/050,944 Page 30 Art Unit: 2124 Application/Control Number: 18/050,944 Page 31 Art Unit: 2124 Application/Control Number: 18/050,944 Page 32 Art Unit: 2124 Application/Control Number: 18/050,944 Page 33 Art Unit: 2124 Application/Control Number: 18/050,944 Page 34 Art Unit: 2124 Application/Control Number: 18/050,944 Page 35 Art Unit: 2124 Application/Control Number: 18/050,944 Page 36 Art Unit: 2124 Application/Control Number: 18/050,944 Page 37 Art Unit: 2124 Application/Control Number: 18/050,944 Page 38 Art Unit: 2124 Application/Control Number: 18/050,944 Page 39 Art Unit: 2124
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