CTNF 18/051,379 CTNF 82548 DETAILED ACTION 1. Claims 1-25 are pending in the application. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 3. 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. 4. Claims 18-22 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. 5. Claims 18-22 are directed to, "A computer-readable storage medium." Computer readable storage medium when interpreted in light of the specification (which provides no limiting definition to only non-transitory media) and taking into account the meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art includes communication media that transmits a program as signals. Therefore, the claim as a whole covers a transitory signal, which does not fall within the definition of a process, a machine, manufacture, or composition of matter (In re Nuijten). Amendments may be made to narrow the claim to cover only statutory embodiments to avoid a rejection under 35 U.S.C. § 1 01 by adding the limitation "non-transitory" to the claim, e.g. "a non-transitory computer-readable storage medium". Such an amendment would typically not raise the issue of new matter, even when the specification is silent because the broadest reasonable interpretation relies on the ordinary and customary meaning that includes non-transitory embodiments and transitory signals per se. Subject Matter Eligibility of Computer Readable Media, 1351 OG 212 (February 23,2010). Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA 7. Claim(s) 1-7 and 9-15 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Bradford et al (hereafter Bradford)(US Pub. 2019/0042248) . 8. As to claims 1 and 9, Bradford discloses a computing system (abstract) comprising: a compute engine to issue an input instruction (fig. 2 array transpose instructions 203); a memory; a memory controller coupled to the memory; transposition hardware (fig. 2, fig 13 and [0175]-[0177] memory and memory controller unit(s); and a data controller coupled to the compute engine, the memory controller, and the transposition hardware, the data controller to detect the input instruction, transfer, based on the input instruction, stored matrix data from the memory to the transposition hardware, and configure the transposition hardware to stream out transposed matrix data associated with the stored matrix data (figs 2 and 13, [0172], [0175]-[0177] and [0181]). 9. As to claims 2 and 10, Bradford discloses wherein one row of the transposed matrix data is to be streamed per cycle at a rate associated with a bandwidth of the memory ([0171]). 10. As to claims 3 and 11, Bradford discloses wherein the data controller is to transition the transposition hardware between a parallel mode and a serial mode based on a state of the transposition hardware ([0052] parallel and serial). 11. As to claims 4 and 12, Bradford discloses wherein the transposition hardware includes: an input multiplexer to receive the stored matrix data and output intermediate matrix data; a plurality of transpose engines coupled to the input multiplexer, the plurality of transpose engines to hold the intermediate matrix data; and an output multiplexer coupled to the plurality of transpose engines, the output multiplexer to generate the transposed matrix data ([0076], multiplexer; [0054] and [0069] matrix transpose engine). 12. As to claims 5 and 13, Bradford discloses wherein the stored matrix data is to include non-square matrices, and wherein the data controller is to interleave one or more write operations from the transposition hardware ([0065]-[0069]). 13. As to claims 6 and 14, Bradford discloses wherein a row dimension of the stored matrix data is to be greater than a row dimension of the memory, and wherein the data controller is to interleave one or more read operations from the memory ([0081]). 14. As to claims 7 and 15, Bradford discloses wherein a width of the memory is greater than a width of an interface between the data controller and the memory, and wherein the data controller is to duplicate read operations from locations in the memory ([0094] and [0124]-[0126]) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 15. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 16. Claim (s) 8 and 16-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bradford in view of Lu (US Pub. 2021/0193208) . 17. As to claims 8 and 16 Bradford discloses a number of matrices to be transposed, and wherein the compute engine is to perform one or more matrix multiplication operations on the transposed matrix data while the transposed matrix data is being streamed out (figs 2 and 13, [0172], [0175]-[0177] and [0181]). 18. Bradford does not disclose the input instruction is to include a wordline size of the memory. However, Lu discloses the input instruction is to include a wordline size of the memory ([0035] a data set representing an input data array (such as a matrix) having one or more one-dimensional data arrays (such as rows or columns of a matrix), each having a set of elements (such as the elements in a row or column of a matrix) using an a array of memory cells accessible in rows and columns includes (a) applying (410) a set of input signals to respective wordlines of a two-dimensional array of memory cells arranged in rows and columns). 19. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to modify the teachings of Bradford by having the input instruction to include a wordline size of the memory, as taught by Lu, for the benefit of accelerating applications of matrix transposition in machine learning and similar implementations, for more efficient operation (Lu, [0002] and [0003]). 20. As to claim 17, the combination of Bradford and Lu discloses wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates ([0021]-[0022] transistors). 21. As to claims 18 and 23, Bradford discloses at least one computer readable storage medium comprising a set of executable program instructions, which when executed by a computing system (abstract), cause the computing system to: Determine a number of matrices to be transposed and incorporate a number of matrices into an input instruction ([0197] input instructions); and issue the input instruction to a data controller associated with transposition hardware, wherein the input instruction is to instruct the transposition hardware to stream out transposed matrix data (figs 2 and 13, [0065]-[0069]). 22. Bradford does not disclose determine a wordline size of a memory and incorporate the wordline size into an input instruction. However, Lu discloses determine a wordline size of a memory and incorporate the wordline size into an input instruction ([0035] a data set representing an input data array (such as a matrix) having one or more one-dimensional data arrays (such as rows or columns of a matrix), each having a set of elements (such as the elements in a row or column of a matrix) using an a array of memory cells accessible in rows and columns includes (a) applying (410) a set of input signals to respective wordlines of a two-dimensional array of memory cells arranged in rows and columns). 23. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to modify the teachings of Bradford by having the input instruction to include a wordline size of the memory, as taught by Lu, for the benefit of accelerating applications of matrix transposition in machine learning and similar implementations, for more efficient operation (Lu, [0002] and [0003]). 24. As to claims 19, 20, and 24, the combination of Bradford and Lu discloses the set of executable program instructions, when executed, further cause the computing system to incorporate a base address of a matrix in the memory, a row dimension of the matrix, and a column dimension of the matrix into the input instruction (Bradford [0081] dimensions. 25. As to claims 21 and 25, the combination of Bradford and Lu discloses wherein the executable program instructions, when executed, further cause the computing system to incorporate a destination address into the input instruction (Bradford [0100] destination address). 26. As to claim 22, the combination of Bradford and Lu discloses wherein the instructions, when executed, further cause to computing system to perform one or more matrix multiplication operations on the transposed matrix data while the transposed matrix data is being streamed out (Bradford [0165]) . Conclusion 07-96 AIA 27. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 28. US Pat. 6574651 – related to a method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in the multiplication unit. The multiplication unit includes a selector which can feed various-sized data formats to the same multiplier circuits. Multiple data transformation paths are provided and feed into a single compression circuit and a single configurable full adder circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571)272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151 Application/Control Number: 18/051,379 Page 2 Art Unit: 2151 Application/Control Number: 18/051,379 Page 3 Art Unit: 2151 Application/Control Number: 18/051,379 Page 4 Art Unit: 2151 Application/Control Number: 18/051,379 Page 5 Art Unit: 2151 Application/Control Number: 18/051,379 Page 6 Art Unit: 2151 Application/Control Number: 18/051,379 Page 7 Art Unit: 2151 Application/Control Number: 18/051,379 Page 8 Art Unit: 2151 Application/Control Number: 18/051,379 Page 9 Art Unit: 2151 Application/Control Number: 18/051,379 Page 10 Art Unit: 2151 Application/Control Number: 18/051,379 Page 11 Art Unit: 2151
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