DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed March 11, 2026 have been entered and considered.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 11, 2026 has been entered.
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1C, Fig. 22, Claims 1-2, 4-5, and 7 in the reply filed on March 3, 2025 is acknowledged.
Claims 3, 6, and 8-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group and/or Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 3, 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 9590053 B2), in view of Ho et al. (US 20200373395 A1), and Yuda et al. (US 20210391428 A1).
Regarding claim 1, Chou et al. teaches:
A semiconductor device [200, Col. 4, Lines 1-15, Fig. 2] comprising:
a semiconductor substrate [102, Col. 4, Lines, 5-15, Fig. 2] having an upper surface and a lower surface;
an n-type first semiconductor region [204, Col. 4, Lines 33-41, Fig. 2] formed in the semiconductor substrate [102, Fig. 2] and having a predetermined depth from the upper surface of the semiconductor substrate [102, Fig. 2];
a p-type second semiconductor region [202, Col. 4, Lines 22-35, Fig. 2] formed in the semiconductor substrate [102, Fig. 2] so as to be adjacent to the first semiconductor region [204, Fig. 2] in a first direction along the upper surface of the semiconductor substrate [102, Fig. 2], the second semiconductor region [202, Fig. 2] having a predetermined depth from the upper surface of the semiconductor substrate [102, Fig. 2];
an n-type source region [104, Col. 4, Lines 5-24, Fig. 2] formed in an upper surface of the second semiconductor region [202, Fig. 2];
an n-type drain region [106, Col. 4, Lines 5-15; Col. 4, Lines 33-35, Fig. 2] formed in an upper surface of the first semiconductor region [204, Fig. 2];
a gate electrode [108, Col. 4, Lines 42-59, Fig. 2] formed on the second semiconductor region [202, Fig. 2] between the source region [104, Fig. 2] and the drain region [106, Fig. 2] via a gate dielectric film [110, Col. 4, Lines 47-52, Fig. 2]; and
a first electrode [122/214, Col. 5, Lines 1-9, Fig. 1/2] formed on the first semiconductor region [204, Fig. 2] between the gate electrode [108, Fig. 2] and the drain region [106, Fig. 2] via a first dielectric film [124, Col. 4, Lines 60-67 to Col. 5, Lines 1-3, Fig. 2].
wherein an LDMOSFET [200, Col. 4, Lines 1-4, Fig. 2] includes the first semiconductor region [204, Fig. 2], the second semiconductor region [202, Fig. 2], the source region [104, Fig. 2], the drain region [106, Fig. 2], the gate electrode [108, Fig. 2], the first dielectric film [124, Fig. 2], and the first electrode [122/214, Fig. 1-2],
wherein the gate electrode [108, Fig. 2] and the first electrode [122/214, Fig. 1/2] are next to each other.
wherein the first electrode [122/214, Fig. 1/2] is formed of a material having a work function, the first semiconductor region [204, Col. 5, Lines 3-4, Fig. 2] located directly below the first electrode [122/214, Fig. 1/2].
Chou et al. does not teach:
a first dielectric film having a larger film thickness than the gate dielectric film.
wherein the gate electrode is made of an n-type semiconductor film, and
wherein the first electrode is made of a p-type semiconductor film.
Ho et al. teaches:
a first dielectric film [124, paragraph [0025], Fig. 2A] having a larger film thickness than the gate dielectric film [110, paragraph [0023], Fig. 2A].
wherein the gate electrode [108, paragraph [0010], [0012], [0015], [0023], [0026], [0033-0036], [0081], Fig. 2A] is made of an n-type semiconductor film, and
wherein the first electrode [122, paragraph [0012], [0037], [0039-0041], [0061], Fig. 2A] is made of a p-type semiconductor film.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ho et al. into the teachings of Chou et al. to include a first dielectric film having a larger film thickness than the gate dielectric film, wherein the gate electrode is made of an n-type semiconductor film, and wherein the first electrode is made of a p-type semiconductor film, for the purpose of increasing breakdown voltage, protecting features underneath, mitigating fabrication costs, increasing performance, the field plate comprises metal materials with a work-function (e.g., N-metal or P-metal materials). This, in part, enhances a formation of a depletion region in the drift region without applying a bias to the field plate. Additionally, during formation of the conductive contacts, a high power plasma etch process is utilized. The field plate functions as an etch stop layer during the high power plasma etch process, thereby mitigating damage to the drift region, enabling a low-cost method of fabrication, decreasing a breakdown voltage of the high voltage device, enhancing the performance of the device by manipulating electric fields (e.g., reducing peak electric fields) generated by a gate electrode, generating an electric field that controls the movement of charge carriers within a channel region, and the field plate acting upon the electric field generated by the gate electrode reduces a high-field charge carrier trapping effect near the drain region.
Chou et al. and Ho et al. do not teach:
wherein the first electrode is formed of a material having a larger work function than the first semiconductor region located directly below the first electrode.
Yuda et al. teaches:
wherein the first electrode [7, paragraph [0049-0050], Fig. 8] is formed of a material having a larger work function than the first semiconductor region [2, paragraph [0049], Fig. 8] located directly below the first electrode [7, Fig. 8].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yuda et al. into the teachings of Chou et al. and Ho et al. to include wherein the first electrode is formed of a material having a larger work function than the first semiconductor region located directly below the first electrode, for the purpose of increasing sensitivity to changes in electric field, improving stability, resistance, performance and efficiency, and increase efficiency of electron injection.
Regarding claim 2, Chou et al., Ho et al., and Yuda et al. teach the semiconductor device according to claim 1.
Chou et al. further teaches:
wherein the first electrode [122/214, Col. 5, Lines 37-41, Fig. 1/2] comprises p-type silicon, copper or platinum.
Regarding claim 4, Chou et al., Ho et al., and Yuda et al. teach the semiconductor device according to claim 1.
Chou et al. further teaches:
wherein the first dielectric film [124, Col. 4, Lines 60-67, Fig. 2] covers the upper surface of the semiconductor substrate [102, Fig. 2] between the gate electrode [108, Fig. 2] and the drain region [106, Fig. 2], a side surface of the gate electrode [108, Fig. 2] on a drain region [106, Fig. 2] side, and a part of an upper surface of the gate electrode [108, Fig. 2].
Regarding claim 5, Chou et al., Ho et al., and Yuda et al. teach the semiconductor device according to claim 4.
Chou et al. further teaches:
wherein the first electrode [214, Col. 5, Lines 1-2, Fig. 2] is in contact with the first dielectric film [124, Fig. 2] covering the side surface of the gate electrode [108, Fig. 2] on the drain region [106, Fig. 2] side.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 9590053 B2), in view of Ho et al. (US 20200373395 A1), and Yuda et al. (US 20210391428 A1) as applied to claim 1 above, and further in view of another embodiment of Chou et al. (US 9590053 B2), and Krull et al. (US 20080200020 A1).
Regarding claim 7, Chou et al., Ho et al., and Yuda et al. teach the semiconductor device according to claim 1.
Chou et al. further teaches:
wherein the first electrode [214, Fig. 2] is continuously formed in contact with an upper surface of the first dielectric film [124, Fig. 2] located between the gate electrode [108, Fig. 2] and the drain region [106, Fig. 2] in the first direction, a side surface of the first dielectric film [124, Fig. 2] covering the side surface of the gate electrode [108, Fig. 2] on the drain region [106, Fig. 2] side, and the upper surface of the first dielectric film [124, Fig. 2] on the upper surface of the gate electrode [108, Fig. 2], and
wherein, between a laminated film formed of the first dielectric film [124, Fig. 2] and the first electrode [214, Fig. 2] and the drain region [106, Fig. 2]
Chou et al. first embodiment [Fig. 2] does not teach:
a sidewall spacer formed of a second dielectric film covering a side surface of the laminated film on the drain region side.
Another embodiment of Chou et al. [Fig. 4, 16-19] teaches:
a sidewall spacer [406, Col. 6, Lines 40-53, Fig. 4, 16-19] formed of a second dielectric film covering a side surface of the laminated film [402, 404, Fig. 4, 16-19] on the drain region [106, Fig. 4, 16-19] side.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of another embodiment of Chou et al. [Fig. 4, 16-19] into the teachings of Chou et al. [Fig. 2], Ho et al., and Yuda et al to include a sidewall spacer formed of a second dielectric film covering a side surface of the laminated film on the drain region side, for the purpose of protecting underlying features, and enhancing performance and reliability.
Chou et al., Ho et al., and Yuda et al. do not teach:
A sidewall spacer exposing the drain region.
Krull et al. teaches:
A sidewall spacer [59, paragraph [0041], Fig. 4e] exposing the drain region [67, paragraph [0041], Fig. 4e].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Krull et al. into the teachings of Chou et al., Ho et al., and Yuda et al. to include a sidewall spacer exposing the drain region, for the purpose of preparing for subsequent processing, improving control, heat dissipation, performance, efficiency and reliability.
Response to Arguments
Applicant’s arguments with respect to independent claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on pages 1-2, Section: Claim Rejections under 35 U.S.C. §103, in remarks filed March 11, 2026 that the current prior art of record does not teach the amended limitations of independent claim 1. Examiner disagree with Applicant. The amended limitations of independent claim 1 can be overcome by previously cited secondary reference Ho et al. (US 20200373395 A1). Ho et al. teaches that the gate electrode is made of n-type semiconductor film, and the first electrode (field plate) is made of a p-type semiconductor film. Support for this can be found at least in paragraphs [0010], [0012], [0015], [0023], [0026], [0033-0041], [0061], and [0081]. The amended limitations of claim 1 are not new, and are known limitations in the art. One of ordinary skill in the art would have been motivated to include a gate electrode is made of n-type semiconductor film, and the first electrode (field plate) is made of a p-type semiconductor film for the purpose of the field plate comprises metal materials with a work-function (e.g., N-metal or P-metal materials). This, in part, enhances a formation of a depletion region in the drift region without applying a bias to the field plate. Additionally, during formation of the conductive contacts, a high power plasma etch process is utilized. The field plate functions as an etch stop layer during the high power plasma etch process, thereby mitigating damage to the drift region, enabling a low-cost method of fabrication, decreasing a breakdown voltage of the high voltage device, enhancing the performance of the device by manipulating electric fields (e.g., reducing peak electric fields) generated by a gate electrode, generating an electric field that controls the movement of charge carriers within a channel region, and the field plate acting upon the electric field generated by the gate electrode reduces a high-field charge carrier trapping effect near the drain region.
Applicant argues on page 2, Section: Claim Rejections under 35 U.S.C. §103, in remarks filed March 11, 2026 that based on the foregoing arguments, dependent claims should be now be in condition for allowance. Examiner disagrees with Applicant due to secondary reference Ho et al. (US 20200373395 A1) overcoming the amended limitations of independent claim 1.
In summary, Applicant’s arguments regarding independent claim 1 are moot because the amended limitations can be overcome by previously cited secondary source Ho et al. (US 20200373395 A1). All claims directly or indirectly dependent on independent claim 1 are therefore rejected for at least the reasons mentioned above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID MICHAEL HELBERG whose telephone number is (571)270-1422. The examiner can normally be reached Mon.-Fri. 8am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571)270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.M.H./Examiner, Art Unit 2815 04/03/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815