Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to claim 8 fixes the prior antecedent basis issues. The 112 rejection of claims 8 – 14 is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 - 7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 states “a first gate dielectric layer of the bottom device… entirely below a horizontal plane between the top device and the bottom device, and a second gate dielectric layer of the bottom device… entirely below the horizontal plane”. The drawings and specification do not provide adequate description of a second gate dielectric layer of the bottom device that is entirely below a horizontal plane that separates the device. The drawings appear to show two dielectric layers, but the two dielectric layers appear to be separated between the top device and the bottom device, and not both dielectric layers existing in the bottom device. For example, figure 50 and 51 show a first gate dielectric layer 132 and a second gate dielectric layer 150. The dielectric layers are separated by a spacer 122 sandwiched between the two dielectric layers as claimed in claim 2. The specification describes spacer 122 as isolating the top devices from the bottom devices (immediate application, Par. [0066]). This appears to show that the top and bottom devices are separated by the spacer 122 and that the dielectric layer above the spacer is a part of one device and the dielectric layer below the spacer is a part of a different device. This contradicts the claim of the two gate dielectric layers belonging to a singular device and instead teaches the first gate dielectric layer as a part of the bottom device and the second gate dielectric layer as a part of the top device, similar to claims 8 and 15. Further, the immediate application describes in the specification that the second gate dielectric 150 forms the bottom gate structure (Par. [00110]) and that the first gate dielectric 132 forms a top gate structure (Par. [0085]). This appears to teach that the dielectric layers are a part of two different devices, a top and bottom device, and not a part of the same device. This makes it unclear what two dielectric layers are specifically being referred to in the claims, where the two dielectric layers are located, where the two devices are separated at, and where the horizontal plane is placed that the gate dielectric layers are supposed to be placed below or if both or if just one gate dielectric layer is supposed to be below or above the horizontal plane. Another issue appears to be that the drawings do not provide a clear indication of where the horizontal plane can be that allows for both of the gate dielectric layers to be entirely beneath the horizontal plane. For example, in figure 50 if the horizontal plane is placed at the top of gate dielectric 150, then both layers would be below the horizontal plane, but the horizontal plane would no longer separate the top and bottom devices as the surrounding second work function metal layer 152 of the bottom gate structure is now included below the device, while the rest of the bottom structure is located above the device. If the horizontal plane in figure 50 is placed between gate dielectric layers 150 and 132, then the horizontal plane separates the top and bottom devices but both dielectric gate layers are no longer below the horizontal plane as claimed in claim 1. The claimed subject matter when compared with the specification and drawings makes it unclear where the horizontal plane is supposed to be located to separate the top and bottom devices but allows for both gate dielectric layers to be below the horizontal plane.
The subject matter of the first and second gate dielectric layers being a part of the bottom device appears to lack adequate description in the specification and drawings as the specification and drawings appear to teach the two gate dielectric layers as being a part of two separate devices, not the same device, and on opposite sides of the horizontal plane. Claim 1 is rejected as being indefinite as lacking written description that conveys to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claims 2 – 7 depend on claim 1 and inherit all of its deficiencies. Claims 2 – 7 are rejected as lacking written description. For the purpose of compact prosecution, examiner is interpreting claim 1 as two gate dielectric layers are located below a horizontal plane that separates a top device from a bottom device.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, and 8 – 10 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20200294866 A1 hereinafter Cheng.
For claim 1, Cheng teaches “A semiconductor structure comprising: a stacked transistor structure comprising a top device stacked directly above a bottom device (fig. 8B numeral 106 and 104); a first gate dielectric layer of the bottom device, wherein the first dielectric layer is entirely below a horizontal plane between the top device and the bottom device (fig. 8B numeral 802); and a second gate dielectric layer of the bottom device, wherein the second gate dielectric layer is entirely below the horizontal plane (fig. 8B numeral 312).” Figure 8B of Cheng shows to dielectric layers entirely below a horizontal point between the top device 106 and the bottom device 104; see attached figure of annotated figure 8B.
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For claim 3, Cheng teaches “The semiconductor structure according to claim 1, further comprising: a spacer material (fig. 8B numeral 602) separating a top source drain region of the top device (fig. 8B numeral 604) from a bottom source drain region of the bottom device (fig. 8B numeral 502).
For claim 5, Cheng teaches “The semiconductor structure according to claim 1, wherein a topmost surface of the first gate dielectric layer (fig. 8B numeral 802) directly contacts a bottommost surface of the second gate dielectric layer (fig. 8B numeral 312).”
For claim 8, Cheng teaches “A semiconductor structure comprising: a first stacked transistor structure (fig. 2A numeral 202) comprising a first top device (fig. 2A numeral 106) stacked directly above a first bottom device (fig. 2A numeral 104); a second stacked transistor structure adjacent to the first stacked transistor structure (fig. 2A numeral 204), the second stacked transistor structure comprising a second top device (fig. 2A numeral 106) stacked directly above a second bottom device (fig. 2A numeral 104); a first gate dielectric layer of the first bottom device and the second bottom device, wherein the first gate dielectric layer is entirely below a horizontal plane between the first top device and the first bottom device (fig. 8A and 8B numeral 802; Par. [0030]); and a second gate dielectric layer of the first top device and the second top device, wherein the second gate dielectric layer is entirely above the horizontal plane (fig. 8A and 8B numeral 802).” Figures 8A and 8B show a dielectric layer 802 on the first and second bottom devices and a separate dielectric layer 802 on the first and second top devices and wherein the two dielectric layers 802 are respectively above and below a horizontal plane separating the top and bottom devices. See annotated figures 8A and 8B showing the horizontal line.
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For claim 9, Cheng teaches “The semiconductor structure according to claim 8, further comprising: a dielectric spacer sandwiched between the first gate dielectric layer and the second gate dielectric layer (fig. 8B numeral 312; Par. [0056]), wherein a width of the dielectric spacer is equal to a width of a channel nanosheet of the first top device and a channel nanosheet of the first bottom device (fig. 8B shows spacer 312 with matching widths with channel nanosheets 110 of the top and bottom devices).”
For claim 10, Cheng teaches “the semiconductor structure according to claim 9, further comprising: a spacer material (fig. 8B numeral 602) separating a top source drain region of the first top device (fig. 8B numeral 604) from a bottom source drain region of the first bottom device (fig. 8B numeral 502).”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200294866 A1 hereinafter Cheng.
For claim 4, Cheng teaches all of claim 1. Cheng does not explicitly state that the first gate dielectric layer and the second gate dielectric layer are different materials. Cheng does teach that different dielectric materials can be used and that multiple materials can be used at once in combination (Cheng, Par. [0068]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the first and second gate dielectric layers in Cheng could comprise different materials as Cheng teaches a variety materials that can be used in combination with each other depending on the desired properties of the layers (Par. [0068]). It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
For claim 11, Cheng teaches all of claim 8. Cheng does not explicitly state that the first gate dielectric layer and the second gate dielectric layer are different materials. Cheng does teach that different dielectric materials can be used and that multiple materials can be used at once in combination (Cheng, Par. [0068]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the first and second gate dielectric layers in Cheng could comprise different materials as Cheng teaches a variety materials that can be used in combination with each other depending on the desired properties of the layers (Par. [0068]). It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
For claim 18, Cheng teaches all of claim 15. Cheng does not explicitly state that the first gate dielectric layer and the second gate dielectric layer are different materials. Cheng does teach that different dielectric materials can be used and that multiple materials can be used at once in combination (Cheng, Par. [0068]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the first and second gate dielectric layers in Cheng could comprise different materials as Cheng teaches a variety materials that can be used in combination with each other depending on the desired properties of the layers (Par. [0068]). It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claim(s) 15 – 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200294866 A1 hereinafter Cheng in further view of US 20180053690 A1 hereinafter Wang.
For claim 15, Cheng teaches a semiconductor structure comprising: a stacked nanosheet transistor comprising a plurality of top devices (Cheng, fig. 8A and 8B numeral 106) stacked directly above a plurality of bottom devices (fig. 8A and 8B numeral 104); a bottom gate dielectric layer of the plurality of bottom devices, wherein the bottom gate dielectric layer is entirely below the horizontal plane between the plurality of top devices and the plurality of bottom devices (fig. 8A and 8B numeral 802); and a top gate dielectric layer of the plurality of top devices, wherein the top gate dielectric layer is entirely above the horizontal plane (fig. 8A and 8B numeral 802). Figures 8A and 8B show a dielectric layer 802 on the first and second bottom devices and a separate dielectric layer 802 on the first and second top devices and wherein the two dielectric layers 802 are respectively above and below a horizontal plane separating the top and bottom devices. See annotated figures 8A and 8B showing the horizontal line.
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Cheng is silent regarding each of the plurality of top devices have a different threshold voltage and each of the plurality of bottom devices have a different threshold voltage.
Wang teaches a semiconductor device (Wang, fig. 4) comprising stacked nanosheet transistors (fig. 4 numeral 410a, 410b, and 410c) and that each device has a different threshold voltage (Par. [0023]; Par. [0059]; Par. [0075 – 0077]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the different threshold voltage for each device in Wang with the stacked nanosheet structure and bilayer gate dielectric in Cheng in order to optimize the delay in switching and control power leakage (Wang, Par. [0003]).
For claim 16, Cheng and Wang teach all of claim 15. Cheng also teaches a dielectric spacer sandwiched between the bottom gate dielectric layer and the top gate dielectric layer (Cheng, fig. 8B numeral 312) and wherein the width of the dielectric spacer is equal to a width of the channel nanosheets of the plurality of top devices and channel nanosheets of the plurality of bottom devices (fig. 8A and 8B show spacer 312 having matching widths with the nanosheets 110).
For claim 17, Cheng and Wang teach all of claim 16. Cheng also teaches a spacer material separating top source drain regions of the plurality of top devices from bottom source drain regions of the plurality of bottom devices (Cheng, fig. 8B shows spacer material 602 separating top source drain regions 604 from bottom source drain regions 502).
Allowable Subject Matter
Claims 12 – 14, and 19 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 12, Cheng is silent regarding the top surface of the first gate dielectric layer contacts a bottom surface of the second gate dielectric layer at the horizontal plane. The dielectric layers do not appear to make direct contact in Cheng.
For claim 13, Cheng does not appear to teach the top gate structure of the fist top device and a bottom gate structure of the first bottom device directly contacting sidewalls of a gate contact, and wherein the first gate dielectric layer and the second gate dielectric layer directly contact sidewalls of the gate contact.
For claim 14, Cheng does not appear to teach dielectric pillars adjacent to both the first top device and the first bottom device, and wherein the first gate dielectric layer and the second gate dielectric layer directly contact sidewalls of the dielectric pillar.
For claim 19, Cheng does not appear to teach the bottom gate dielectric layer and the top gate dielectric layer making direct contact.
For claim 20, Cheng does not appear to teach a gate contact in direct contact with the bottom gate dielectric layer and the top gate dielectric layer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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