DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In response to amendments, filed October 1, 2025, claims 1, 4-5, 7, and 10-12 have been amended. Claim 2 has been cancelled. Claims 13-17 have been added. Claims 1 and 3-17 are pending.
Response to Arguments
Applicant’s arguments, see Remarks, filed October 1, 2025, with respect to rejections under 35 USC 112 and 35 USC 101 have been fully considered and are persuasive. The rejections under 35 USC 112 and 35 USC 101 have been withdrawn.
Applicant’s arguments with respect to the prior art rejections have been considered but are moot because the new ground of rejection does not rely on the same reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. A new ground(s) of rejection is made in view of the combinations of Lutz (US 20020055687 A1), Kovacs (US 20070208233 A1), Masui (US 20160337152 A1), and Chamoun (US 4907597 A). Any arguments still relevant based on the new grounds of rejection are addressed below.
In response to applicant's argument that Lutz teaches away from using a synchronizing signal in the 0.5-2Hz range, Examiner respectfully disagrees. Lutz is not restricted to the use of the 8 kHz master bus cycle clock signal from an IEEE 1394 bus, and therefore Lutz’s features may be used with Kovacs’ real-time clock including divider components (e.g. flip-flops, counters) for digitally dividing the received base timing signal to produce a real-time digital signal with a frequency of 1 Hz as described in (Kovac [0054]). The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lutz (US 20020055687 A1) in view of Kovacs (US 20070208233 A1).
Regarding claim 1, Lutz teaches a method for synchronizing EEG signals measured by an EEG monitoring system ([0025] "system and method for providing time frame synchronization between stimulus and response signals provided, detected, analyzed and/or displayed by a medical monitoring system" [0046] “the method and apparatus described above for providing time frame synchronization of signals in a medical monitoring system, by providing a multi-bit digital signal indicating the segment of a bus cycle during which a signal occurs, may be applied to signals other than stimulation trigger signals in a medical monitoring system. For example, time frame synchronized response signals may be generated by indicating points in time during a bus cycle wherein specific response signals are received by an amplifier device from a subject”),
wherein the EEG monitoring system comprises a plurality of EEG sensors configured to be positioned on a layer of tissue and wherein each of the plurality of EEG sensors is configured to capture EEG signals of a patient, at least one amplifier coupled to each of the plurality of EEG sensors and configured to amplify the captured EEG signals ([0025] “the amplifier 16 may be connected by electrodes to the subject 14 to receive EEG or EMG signals produced by the subject 14 in response to the stimulus provided by the stimulator device 12”),
and a first oscillator, wherein the at least one amplifier comprises an input for receiving a synchronizing signal from the first oscillator ([0027] “a bus which provides a periodic master bus cycle clock signal”), the method comprising:
distributing the synchronizing signal from the first oscillator to each of the at least one amplifier ([0027] "the stimulator 12, amplifier 16, and monitor 18 devices are connected together via a bus which provides a periodic master bus cycle clock signal to each device on the bus to guarantee that the bus operates to a common time reference;").
However, Lutz fails to disclose wherein the synchronizing signal has a frequency in a range of 0.5 Hz to 2 Hz. Kovacs teaches a cardiac pacemaker with an analog telemetry system with multiple leads.
Kovacs discloses wherein the synchronizing signal has a frequency in a range of 0.5 Hz to 2 Hz ([0054] "Real-time clock 62 includes divider components (e.g. flip-flops, counters) for digitally dividing the received base timing signal to produce a real-time digital signal with a frequency of 1 Hz. For example, a 1-Hz real-time clock signal may be generated by dividing down a 2.097152 MHz integrated circuit synchronization clock signal by 2.sup.21=2.097152.times.10.sup.6, using twenty-one flip-flops connected in series. The 1 Hz tick signal is further input to one or more digital counters to generate a real-time digital time stamp transmitted to digital control logic 60."
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Lutz to include the synchronizing signal has a frequency in a range of 0.5 Hz to 2 Hz as disclosed in Kovacs to generate a real-time digital time stamp for detecting whether predetermined physiologic conditions, real-time conditions, and/or sensor faults or other conditions have occurred (Kovacs [0054, 0085]).
The combination of Lutz/Kovacs discloses:
measuring a period of the synchronizing signal (Lutz: phase detector circuit 44; [0034]);
adjusting a second oscillator, having a frequency, in the at least one amplifier to match a timer count based on the period of the synchronizing signal (Lutz: amplifier 72; [0037] "The output of the low-pass loop filter 46 is provided on a line 74 to an oscillator circuit 48. The oscillator circuit 48 may be implemented in a conventional manner to produce a high frequency local stimulus synchronization circuit clock signal having a frequency which is adjustable in response to a detected phase difference between the local clock signal and the master bus cycle clock signal.” [0037] “the oscillator circuit 48 may be implemented as a voltage controlled crystal oscillator integrated circuit 48, as illustrated in FIG. 4.);
determining a function of the frequency of the second oscillator frequency to produce a clock signal (Lutz: Fig. 2; [0033] "The PLL circuit 40 is employed to generate a local stimulus synchronization circuit clock signal which is synchronized with the master bus cycle clock. The PLL circuit 40 preferably includes a phase detector circuit 44, a low-pass loop filter 46, an oscillator circuit 48, and a clock divider circuit 50. The phase detector 44 receives the master bus cycle clock signal on a line 52 from the bus interface 22 and a local stimulus synchronization circuit clock signal from the clock divider 50 on a line 54. For example, in an IEEE 1394 bus, operation is divided into 125 microsecond cycles." [0037] “The exemplary voltage controlled crystal oscillator 48 produces a high frequency clock signal of, e.g., 12.88 MHz, which forms the high frequency local stimulus synchronization circuit clock. The voltage controlled crystal oscillator 48 is responsive to the signal provided from the low-pass loop filter on line 74, to adjust the output frequency of the oscillator 48. In this manner, the local high frequency stimulus synchronization circuit clock signal is synchronized to the bus cycle clock signal in a conventional manner by the PLL 40"); and
adjusting the frequency of the second oscillator such that the frequency of the second oscillator is equal to the frequency of the synchronizing signal (Lutz: oscillator 48; [0037] “In this manner, the local high frequency stimulus synchronization circuit clock signal is synchronized to the bus cycle clock signal in a conventional manner by the PLL 40”).
Regarding claim 3, the combination of Lutz/Kovacs discloses the method of claim 1, wherein the second oscillator is voltage controlled ([0037] "the oscillator circuit 48 may be implemented as a voltage controlled crystal oscillator integrated circuit 48, as illustrated in FIG. 4").
Regarding claim 4, the combination of Lutz/Kovacs discloses the method of claim 1, wherein the function of the frequency of the second oscillator frequency is determined by dividing the frequency of the second oscillator to produce the clock signal (Lutz: Fig. 2; [0033] "The PLL circuit 40 is employed to generate a local stimulus synchronization circuit clock signal which is synchronized with the master bus cycle clock. The PLL circuit 40 preferably includes a phase detector circuit 44, a low-pass loop filter 46, an oscillator circuit 48, and a clock divider circuit 50. The phase detector 44 receives the master bus cycle clock signal on a line 52 from the bus interface 22 and a local stimulus synchronization circuit clock signal from the clock divider 50 on a line 54. For example, in an IEEE 1394 bus, operation is divided into 125 microsecond cycles." [0037] "The output of the low-pass loop filter 46 is provided on a line 74 to an oscillator circuit 48. The oscillator circuit 48 may be implemented in a conventional manner to produce a high frequency local stimulus synchronization circuit clock signal having a frequency which is adjustable in response to a detected phase difference between the local clock signal and the master bus cycle clock signal.").
Regarding claim 5, the combination of Lutz/Kovacs discloses the method of claim 4, wherein the EEG monitoring system (Lutz: [0025] “the amplifier 16 may be connected by electrodes to the subject 14 to receive EEG or EMG signals produced by the subject 14”) further comprises an analog to digital converter coupled to the second oscillator and configured to digitize the captured EEG signals (Kovacs: [0051] “A/D converter 58 (FIG. 2-A) receives filtered signals from drive/signal processing circuit 52, and generates corresponding digital signals for transmission to digital control logic 60.” amplification 112 is a component of processing circuit 52; Lutz: amplifier 72 within oscillator circuit 48) and the method further comprises using the clock signal to drive an analog to digital converter clock signal (Lutz: [0033] “The PLL circuit 40 preferably includes a phase detector circuit 44, a low-pass loop filter 46, an oscillator circuit 48, and a clock divider circuit 50. The phase detector 44 receives the master bus cycle clock signal on a line 52 from the bus interface 22 and a local stimulus synchronization circuit clock signal from the clock divider 50 on a line 54.” Kovacs: [0082] “Acquisition control logic 120 [a component within digital control logic 60] includes logic controlling the operation of A/D converter 58 and signal processing circuit 52 (FIG. 2-A) according to a number of configuration parameters, including parameters defining the analog signals to be processed and their sampling rates. In embodiments in which signal processing circuit 52 uses analog circuitry, acquisition control logic 120 mainly handles the timing of A/D converter 58”).
Regarding claim 8, the combination of Lutz/Kovacs discloses the method of claim 1, further comprising transmitting the amplified EEG signals to a computing device, wherein the computing device is configured to process the amplified EEG signals (Lutz: [0025] "The monitor device 18 is preferably microprocessor controlled, and may be implemented as a computer system programmed for the display, manipulation, and analysis of the response signals provided by the amplifier device 16").
Regarding claim 9, the combination of Lutz/Kovacs discloses the method of claim 1, wherein the synchronizing signal has a frequency of 1 Hz (Lutz: [0033] “master bus cycle clock signal;” Kovacs: [0054] "Real-time clock 62 includes divider components (e.g. flip-flops, counters) for digitally dividing the received base timing signal to produce a real-time digital signal with a frequency of 1 Hz… The 1 Hz tick signal is further input to one or more digital counters to generate a real-time digital time stamp transmitted to digital control logic 60”).
Claim(s) 6, 10-15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lutz (US 20020055687 A1) in view of Kovacs (US 20070208233 A1) and in further view of Masui (US 20160337152 A1).
Regarding claim 6, the combination of Lutz/Kovacs discloses the method of claim 4, wherein the at least one amplifier comprises the second oscillator (Lutz: amplifier 16, amplifier 72, oscillator circuit 48), the analog to digital converter coupled to the second oscillator and configured to digitize the captured EEG signals (Kovacs: [0051] “A/D converter 58 (FIG. 2-A) receives filtered signals from drive/signal processing circuit 52, and generates corresponding digital signals for transmission to digital control logic 60.” amplification 112 is a component of processing circuit 52; Lutz: amplifier 72 within oscillator circuit 48).
However, the combination of Lutz/Kovacs fails to disclose a microcontroller controlling the frequency of the second oscillator. Masui teaches a transceiver circuit for transmitting and receiving EEG signals. Masui discloses and a microcontroller configured to control the frequency of the second oscillator (Figs. 4 and 5, digital circuit 21; [0101] “In the PFD/CP/LF 115, a PFD 1151 receives an output of the programmable divider 111, and outputs a first control voltage V.sub.CTRL1 to the LC-VCO (LC type voltage controlled oscillator) 112 via a CP 1152 and an LF 1153. Further, the FM DAC 117 receives an FM transmission signal (9-b FM.sub.TX) from the data interface 118, and outputs a second control voltage V.sub.CTRL2 to the VCO 112.” [0154] “Furthermore, the ADCs 1241 and 1242 are formed as variable sampling clock A/D converters capable of variably controlling a sampling frequency (clock frequency fclk) based on the compliant mode, the high speed mode and the low power mode.” [0160] “Specifically, in the low power mode and the compliant mode, the clock frequency fclk is set to a low speed (for example, 1.5 MHz), and in the high speed mode, the clock frequency fclk is set to a high speed (for example, 12 MHz). Note that the technique disclosed in Non-Patent Document 2 may be applied so as to vary the clock frequency (sampling frequency of the ADC).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lutz/Kovacs to include a microcontroller controlling the frequency of the second oscillator as disclosed in Masui to perform feedback control of the VCO so that the clock signal CLK and the output signal of the variable frequency divider are synchronized (Masui [0089]).
The combination of Lutz/Kovacs/Masui discloses and an operation of the analog to digital converter based on the synchronizing signal (Kovacs: [0054] “The 1 Hz tick signal is further input to one or more digital counters to generate a real-time digital time stamp transmitted to digital control logic 60.” [0082] “Acquisition control logic 120 [a component within digital control logic 60] includes logic controlling the operation of A/D converter 58 and signal processing circuit 52 (FIG. 2-A) according to a number of configuration parameters, including parameters defining the analog signals to be processed and their sampling rates. In embodiments in which signal processing circuit 52 uses analog circuitry, acquisition control logic 120 mainly handles the timing of A/D converter 58”).
Regarding claim 10, the combination of Lutz/Kovacs/Masui discloses teaches the method of claim 6, wherein the microcontroller includes a digital to analog (DAC) converter and wherein the microcontroller is configured to adjust the second oscillator by setting the DAC to a corresponding voltage (Masui: [0101] “In the PFD/CP/LF 115, a PFD 1151 receives an output of the programmable divider 111, and outputs a first control voltage V.sub.CTRL1 to the LC-VCO (LC type voltage controlled oscillator) 112 via a CP 1152 and an LF 1153. Further, the FM DAC 117 receives an FM transmission signal (9-b FM.sub.TX) from the data interface 118, and outputs a second control voltage V.sub.CTRL2 to the VCO 112.” Fig. 5, digital circuit 21).
Regarding claim 11, the combination of Lutz/Kovacs/Masui teaches the method of claim 6, wherein the at least one amplifier further comprises an internal timer having microsecond resolution (Lutz: Fig. 2; [0033] "The PLL circuit 40 is employed to generate a local stimulus synchronization circuit clock signal which is synchronized with the master bus cycle clock [1 Hz per Kovacs]. The PLL circuit 40 preferably includes a phase detector circuit 44, a low-pass loop filter 46, an oscillator circuit 48, and a clock divider circuit 50. The phase detector 44 receives the master bus cycle clock signal on a line 52 from the bus interface 22 and a local stimulus synchronization circuit clock signal from the clock divider 50 on a line 54. For example, in an IEEE 1394 bus, operation is divided into 125 microsecond cycles.”).
Regarding claim 12, the combination of Lutz/Kovacs/Masui teaches the method of claim 6, wherein the at least one amplifier further comprises a filter configured to filter out high frequency noise (Lutz: Fig. 2; IEEE 1394 bus, amplifier 16, amplifier 72, low-pass loop filter 46), having a value range greater than 2 kHz, present in an analog voltage signal from the microcontroller output (Kovacs: [0048] “Low-pass filtering circuit 164 has a pass frequency on the order of Hz, for example about 5 Hz, chosen so as not to obscure or blur together individual pacing pulses. Low-pass filtering circuit 164 produces a pulsatile waveform, with each pulse corresponding to one pacemaker pulse signal. Comparator circuit 166 receives the pulsatile waveform, and outputs a digital output corresponding to each pacemaker pulse. Comparator circuit 166 may include a Schmitt trigger. In some embodiments, the output of low-pass filtering circuit 164 may be sent to A/D converter 58 (FIG. 2-A), where the pacemaker pulse detection signal is sampled at a rate on the order of tens of Hz (e.g. 50 Hz)”).
Regarding claim 13, the combination of Lutz/Kovacs discloses the method of claim 1. However, the combination of Lutz/Kovacs fails to explicitly disclose a digital to analog converter outputting a reference voltage. Masui discloses wherein the at least one amplifier comprises a microcontroller that includes a digital to analog (DAC) converter and wherein the DAC is configured to adjust a voltage-controlled oscillator (VOC) by outputting a voltage reference (Masui: [0101] “In the PFD/CP/LF 115, a PFD 1151 receives an output of the programmable divider 111, and outputs a first control voltage V.sub.CTRL1 to the LC-VCO (LC type voltage controlled oscillator) 112 via a CP 1152 and an LF 1153. Further, the FM DAC 117 receives an FM transmission signal (9-b FM.sub.TX) from the data interface 118, and outputs a second control voltage V.sub.CTRL2 to the VCO 112.” Fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lutz/Kovacs to include a digital to analog (DAC) converter outputting a reference voltage as disclosed in Masui to perform feedback control of the VCO so that the clock signal CLK and the output signal of the variable frequency divider are synchronized (Masui [0089]).
Regarding claim 14, the combination of Lutz/Kovacs/Masui discloses the method of claim 13, wherein the at least one amplifier comprises a low-pass filter configured to remove high frequency noise (Lutz: low-pass loop filter 46), having a value range greater than 2 kHz (Kovacs: [0048] “Low-pass filtering circuit 164 has a pass frequency on the order of Hz, for example about 5 Hz, chosen so as not to obscure or blur together individual pacing pulses.”) from an output of the DAC before the DAC outputs the voltage reference to the VOC (Lutz: low pass filter 46 prior to VCXO 48, Fig. 2; Masui: Fig. 4; [0101] “In the PFD/CP/LF 115, a PFD 1151 receives an output of the programmable divider 111, and outputs a first control voltage V.sub.CTRL1 to the LC-VCO (LC type voltage controlled oscillator) 112 via a CP 1152 and an LF 1153. Further, the FM DAC 117 receives an FM transmission signal (9-b FM.sub.TX) from the data interface 118, and outputs a second control voltage V.sub.CTRL2 to the VCO 112.”).
Regarding claim 15, the combination of Lutz/Kovacs/Masui discloses the method of claim 13, wherein the microcontroller is configured to divide the second oscillator frequency to produce the clock signal and a convert start signal (Lutz: [0033] “The PLL circuit 40 preferably includes a phase detector circuit 44, a low-pass loop filter 46, an oscillator circuit 48, and a clock divider circuit 50. The phase detector 44 receives the master bus cycle clock signal on a line 52 from the bus interface 22 and a local stimulus synchronization circuit clock signal from the clock divider 50 on a line 54.” Kovacs: [0082] “Acquisition control logic 120 [a component within digital control logic 60] includes logic controlling the operation of A/D converter 58 and signal processing circuit 52 (FIG. 2-A) according to a number of configuration parameters, including parameters defining the analog signals to be processed and their sampling rates. In embodiments in which signal processing circuit 52 uses analog circuitry, acquisition control logic 120 mainly handles the timing of A/D converter 58”).
Regarding claim 17, the combination of Lutz/Kovacs/Masui discloses the method of claim 11, wherein the microcontroller is configured to measure a period of the synchronizing signal using the internal timer (Lutz: Fig. 2; [0033] "The PLL circuit 40 is employed to generate a local stimulus synchronization circuit clock signal which is synchronized with the master bus cycle clock [1 Hz per Kovacs]. The PLL circuit 40 preferably includes a phase detector circuit 44, a low-pass loop filter 46, an oscillator circuit 48, and a clock divider circuit 50. The phase detector 44 receives the master bus cycle clock signal on a line 52 from the bus interface 22 and a local stimulus synchronization circuit clock signal from the clock divider 50 on a line 54. For example, in an IEEE 1394 bus, operation is divided into 125 microsecond cycles.” Masui: digital circuit 21).
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lutz (US 20020055687 A1) in view of Kovacs (US 20070208233 A1) and Masui (US 20160337152 A1), and in further view of Chamoun (US 4907597 A).
Regarding claim 7, the combination of Lutz/Kovacs/Masui teaches the method of claim 6. However, the combination of Lutz/Kovacs/Masui fails to disclose a signal isolator.
Chamoun teaches a biopotential analysis system and method of the present invention for determining, in a noninvasive manner, cerebral electrical properties. Chamoun discloses wherein the microcontroller comprises a signal isolator (Col 3, lines 55-58 “All DC power lines going to the amplifiers 30, sample and hold circuits 32, multiplexer 36 and analog-to-digital convertor 38 are also isolated from the AC power line with a DC/DC convertor 46”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Lutz/Kovacs/Masui to include a signal isolator as disclosed in Chamoun in order to provide complete patient isolation from ground for increased patient safety and to protect the host computer form transients (Chamoun, Col 3, lines 55-59 and Col 4 lines 3-6).
Regarding claim 16, the combination of Lutz/Kovacs/Masui/Chamoun teaches the method of claim 7, wherein the signal isolator comprises isolated DC-DC power converters configured to provide an isolation barrier over which the synchronizing signal can be coupled (Col 3, lines 55-58 “All DC power lines going to the amplifiers 30, sample and hold circuits 32, multiplexer 36 and analog-to-digital convertor 38 are also isolated from the AC power line with a DC/DC convertor 46”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.H./Examiner, Art Unit 3791
/DEVIN B HENSON/Primary Examiner, Art Unit 3791