Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action responds to the Application filed on 11/09/2022 and IDS filed on 12/07/2022.
Claims 1-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, 6, and 7-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 10,074,693. Although the claims at issue are not identical, they are not patentably distinct from each other because the patented application recited an integrated circuit/memory array having limitations that correspond to the memory device/integrated circuit/memory array of the current application.
Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 10,686,015. Although the claims at issue are not identical, they are not patentably distinct from each other because the patented application recited an integrated circuit/memory array having limitations that correspond to the memory device/integrated circuit/memory array of the current application.
Claims 7, 8, 11, 16, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-18 of U.S. Patent No. 11,522,014. Although the claims at issue are not identical, they are not patentably distinct from each other because the patented application recited an apparatus having limitations that correspond to the memory device/integrated circuit/memory array of the current application. Wherein, limitation of boundary regions in the patented application correspond to the limitation socket interconnect regions in the current application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recited “plurality of electrode lines at a first level, the plurality of electrode
lines extending in a first direction and having a first pitch in a second direction, wherein each electrode line is connected at a connection position in the first direction”, however it is not apparent what the electrode line is connected to at the connection position in the first direction.
As per claims 2-6 are rejected to for incorporating the above limitations into the claims by dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Samachisa et al. (U.S. Pat. No. 8,547,720 B2).
As per claim 1, Samachisa discloses:
A memory device, comprising:
PNG
media_image1.png
631
887
media_image1.png
Greyscale
a plurality of electrode lines at a first level, the plurality of electrode lines extending in a first direction (See Figure 30B, i.e. label as A & Col 38; Lines 52-63) and having a first pitch in a second direction (See Figure 30B, i.e. label as B & Col 38; Lines 52-63), wherein each electrode line is connected at a connection position in the first direction (See Figure 30B, i.e. label as C),
wherein each electrode line is connected to one of a plurality of metal lines of an interconnect level above or below the first level in a third direction (See Figure 30B, i.e. label as E & Col 38; Lines 52-63), and
wherein the connection positions of at least some of the plurality of electrode lines periodically repeat in the second direction at a periodicity that is greater than the first pitch (See Figure 30B, i.e. label as F, repeated connection in F is greater than the distance B between electrodes & Col 38; Lines 52-63).
As per claim 2, Samachisa discloses all of the features of claim 1 as discloses above wherein Samachisa also discloses wherein the plurality of metal lines is electrically connected with a transistor level below the interconnect level in the third direction (See Col 38; Lines 52-63, i.e. active elements … transistors 222)
As per claim 6, Samachisa discloses all of the features of claim 1 as discloses above wherein Samachisa also discloses wherein: the third direction is perpendicular to the first direction and to the second direction, or the third direction crosses the first direction and the second direction and is non-perpendicular to the first direction and to the second direction (See Figure 30B, i.e. label as E & Col 38; Lines 52-63).
Claim(s) 7, 8, 11, and 13-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho (U.S. Pub. No. 2011/0032785 A1).
As per claim 7, Cho discloses:
An integrated circuit, comprising:
PNG
media_image2.png
570
750
media_image2.png
Greyscale
a plurality of conductive lines formed at a first level that extend in a first direction and have a pitch in a second direction (See Figure 9, i.e. DL7 & DL8 & See Para [00120]-[0125]), wherein the plurality of conductive lines are connected to interconnect structures formed at a second level above or below the first level in a third direction, the plurality of conductive lines (See Figure 9, i.e. label A & See Para [00120]-[0125]) comprising:
a first plurality of lines connected to at least one interconnect structure at a socket interconnect region (See Figure 9, i.e. label A , with socket region being B & See Para [00120]-[0125]);
a second plurality of lines connected to the socket interconnect region (See Figure 9, i.e. EL7 & EL8 & See Para [00120]-[0125]); and
a third plurality of lines that pass through the socket interconnect region (See Figure 9, i.e. EL5, EL6, DL5, DL6 pass through & See Para [00120]-[0125]).
As per claim 8, Cho discloses all of the features of claim 7 as discloses above wherein Cho also discloses wherein the third plurality of lines pass through the socket interconnect region without being connected to the socket interconnect region and without being terminated at or within the socket interconnect region (See Figure 9, i.e. EL5, EL6, DL5, DL6 pass through & See Para [00120]-[0125]).
As per claim 11, Cho discloses all of the features of claim 7 as discloses above wherein Cho also discloses wherein the plurality of conductive lines are word lines or digit lines of a first memory array deck and upper conductive lines serve as word lines or digit lines of a second memory array deck (See Para [0087], i.e. memory cell array, and the sub-wordline, See Para [00120]-[0125]).
As per claim 13, Cho discloses all of the features of claim 7 as discloses above wherein Cho also discloses wherein at least one connector is positioned between a first pair of contacted lines and extends the third direction (See Figure 9, i.e. label A , with socket region being B & See Para [00120]-[0125]).
As per claim 14, Cho discloses all of the features of claim 7 as discloses above wherein Cho also discloses wherein a line of the second plurality of lines is connected to an interconnect structure of a second socket interconnect region that is offset from the socket interconnect region in the first direction (See Figure 9, i.e. different interconnection region CONJ, offset from one and another & See Para [00120]-[0125]).
As per claim 15, Cho discloses all of the features of claim 7 as discloses above wherein Cho also discloses wherein each of the first plurality of lines, the second plurality of lines and the third plurality of lines have substantially the same length in the first direction (See Figure 9, i.e. DL7, DL8, EL7, and EL8 & See Para [00120]-[0125]).
As per claim 16, Cho discloses all of the features of claim 7 as discloses above wherein Cho also discloses wherein: the third direction is perpendicular to the first direction and to the second direction, or the third direction crosses the first direction and the second direction and is non-perpendicular to the first direction and to the second direction (See Figure 9, i.e. DL7, DL8 & label A – & See Para [00120]-[0125]).
Claim(s) 17 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Siau et al. (U.S. Pub. No. 2016/0133320 A1).
As per claim 17, Siau discloses:
A memory array, comprising:
a plurality of electrode lines formed at a first level and traversing a plurality of memory cell regions (See Figure 4A, i.e. WL and LBL in region 412 & Para [0071]-[0076]);
each memory cell region formed between socket interconnect regions in a first direction (See Figure 4A, -[in Figure 4A – region 412 is between 410 and bottom region , considered as the memory cell regions], See Para [0071]-[0076])
wherein the plurality of electrode lines have a pitch in a second direction and include digit lines and word lines that intersect in the plurality of memory cell regions (See Figure 4A -WL and LBL in 412 include pitch between, intersect between WL and LBL], See Para [0071]-[0076])
wherein each electrode line is coupled with a second level above or below the first level in a third direction using at least one socket interconnect region (See Figure 4A, -[in Figure 4A – LBL is connected to Q and GBL in bottom region (socket interconnect region) ], See Para [0071]-[0076])
As per claim 20, Siau discloses all of the features of claim 17 as discloses above wherein Siau also discloses wherein: the third direction is perpendicular to the first direction and to the second direction, or the third direction crosses the first direction and the second direction and is non-perpendicular to the first direction and to the second direction (See Figure 4A, -[in Figure 4A – direction of LBL , WL , GBL are perpendicular) ], See Para [0071]-[0076]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho (U.S. Pub. No. 2011/0032785 A1) in view of Gotti et al. (U.S. Pub. No. 2013/0048935 A1).
As per claim 12, Cho discloses all of the features of claim 7 as discloses above.
Cho does not teach the limitations: phase change memory cells positioned at intersections between the plurality of conductive lines and digit lines.
However Gotti teaches the limitations: phase change memory cells positioned at intersections between the plurality of conductive lines and digit lines (See Para [0004], i.e. Each access line is connected to a row of phase change memory cells and each digit line is connected to a column of phase change memory cells, See Para [0052]-[0056]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Gotti into the
teaching of Cho because it would allow for reducing energy requirement to generate
heat to produce a detectable resistance change in a phase change memory cells (See
Para [0005]-[0006]).
Allowable Subject Matter
Claims 3-5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph and overcome the rejection(s) under Double Patenting, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 9 and 10 would be allowable if overcome the rejection(s) under Double Patenting, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to claims 3-5, the prior art does not teach the limitations of claim 3, wherein 4 and 5 depend on claim 3.
With respect to claims 9 and 10, the prior art does not teach the limitations of
claim 9, wherein claim 10 depend on claim 9.
With respect to claims 18 and 19, the prior art does not teach the limitations of claim 18, wherein claim 19 depend on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NHA T NGUYEN/Primary Examiner, Art Unit 2851