DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 11/11/2022 for application number 18/054,724.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Independent claim 1 (representative of independent 12) recites:
A quantum state preparation circuit generation method, performed by a computer device, the method comprising: obtaining a target vector; generating a quantum state intermediate preparation circuit for preparing the target vector on N qubits, the quantum state intermediate preparation circuit comprising N qubit uniform control gates, and N being a positive integer greater than or equal to 2; and converting each of the N qubit uniform control gates into a diagonal unitary matrix and a single bit gate to obtain a quantum state preparation circuit for preparing the target vector on the N qubits by: implementing the diagonal unitary matrix in a recursive manner using a unitary operator of a first type and a unitary operator of a second type, the unitary operator of the first type being configured to perform phase shift on quantum states of n qubits, and the unitary operator of the second type being configured to restore quantum states of last rt qubits in the n qubits to quantum states when the diagonal unitary matrix is inputted, wherein 1 rt<n<N, and rt and n are integers.
(2A, prong 1) The underlined portions of the claim recite an abstract idea, specifically a mathematical calculation. See, e.g. para. 0082-0187 of the specification as published, which show the mathematical equations and calculations used convert the qubit uniform control gates into a quantum state preparation circuit. The Examiner notes that the claimed, “quantum state preparation circuit,” as used in the claim and specification is not an actual physical circuit but a specification for a circuit that can later be executed on a quantum computer, see para. 0225-26 as published.
(2A, prong 2) This judicial exception is not integrated into a practical application. The claims include the additional elements of (1) generic computer elements (computer in claims 1 and 11, a circuit to execute instructions in claim 12), (2) obtaining a target vector, and (3) generating a quantum state intermediate preparation circuit. Additional element (1) is a mere instruction to apply the exception, because it merely adds a generic computer after-the-fact to the abstract idea. Element (2) is insignificant extra-solution activity, because it amounts to mere data gathering necessary for the mathematical calculation (i.e. the mathematical calculations need a target vector). Element (3) is also a mere instruction to apply because the element only recites the idea of a solution (that a quantum state intermediate preparation circuit is generated for preparing the target vector) and now how to accomplish the solution (the claims and specification do not explicitly set forth how intermediate preparation circuit is generated). Even when all of the additional elements are considered together with the abstract idea, they do not integrate the abstract idea into a practical application because they only add mere instructions to apply the exception and insignificant extra-solution activity to the mathematical calculations.
(2B) The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. Additional element (1) is a mere instruction to apply the exception, because it merely adds a generic computer after-the-fact to the abstract idea. Additional element (2) is well-understood, routine, and conventional, analogous to storing and retrieving information in memory, see MPEP 2106.05(d) citing Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Element (3) is also a mere instruction to apply because the element only recites the idea of a solution and now how to accomplish the solution. Even when all of the additional elements are considered together with the abstract idea, they do not amount to significantly more than the abstract idea itself because they only add mere instructions to apply the exception and insignificant extra-solution activity that is well-understood, routine, and conventional to the mathematical calculations. Overall, the additional elements just specify that a generic computer gets data for the mathematical calculations, and generates a quantum state intermediate preparation circuit (without specifying how to generate the intermediate circuit), for use in the mathematical calculations.
Independent claim 11 recites:
A quantum state preparation method, performed by a computer device or a quantum computer, the method comprising: obtaining a quantum state preparation circuit by converting N qubit uniform control gates into a diagonal unitary matrix and a single bit gate in a quantum state intermediate preparation circuit that prepares a target vector on N qubits, and implementing the diagonal unitary matrix in a recursive manner by using a unitary operator of a first type and a unitary operator of a second type, the unitary operator of the first type being configured to perform phase shift on quantum states of n qubits, the unitary operator of the second type being configured to restore quantum states of last rt qubits in the n qubits to quantum states when the diagonal unitary matrix is inputted, wherein 1<rt<n<N, and rt and n are integers; and executing the quantum state preparation circuit on a quantum computing device comprising the N qubits.
(2A, prong 1) The underlined portions of the claim recite an abstract idea, specifically a mathematical calculation. See, e.g. para. 0082-0187 of the specification as published, which show the mathematical equations and calculations used convert the qubit uniform control gates into a quantum state preparation circuit. The Examiner notes that the claimed, “quantum state preparation circuit,” as used in the claim and specification is not an actual physical circuit but a specification for a circuit that can later be executed on a quantum computer, see para. 0225-26 as published.
(2A, prong 2) This judicial exception is not integrated into a practical application. The claims include the additional elements of (1) generic computer elements (computer in claims 1 and 11, a circuit to execute instructions in claim 12), (2) generating a quantum state intermediate preparation circuit, and (3) executing the quantum state preparation circuit on a quantum computing device. Additional element (1) is a mere instruction to apply the exception, because it merely adds a generic computer after-the-fact to the abstract idea. Elements (2) and (3) are also a mere instruction to apply because the element only recites the idea of a solution (that a quantum state intermediate preparation circuit is generated for preparing the target vector and the circuit is executed on a quantum computer) and now how to accomplish the solution (the claims and specification do not explicitly set forth how intermediate preparation circuit is generated or details of how the circuit is executed on a quantum computer). Even when all of the additional elements are considered together with the abstract idea, they do not integrate the abstract idea into a practical application because they only add mere instructions to apply the exception to the mathematical calculations.
(2B) The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. Additional element (1) is a mere instruction to apply the exception, because it merely adds a generic computer after-the-fact to the abstract idea. Additional elements (2) and (3) are also a mere instruction to apply because the element only recites the idea of a solution and now how to accomplish the solution. Even when all of the additional elements are considered together with the abstract idea, they do not amount to significantly more than the abstract idea itself because they only add mere instructions to apply the exception to the mathematical calculations. Overall, the additional elements just specify that a first computer generates a quantum state intermediate preparation circuit (without specifying how to generate the intermediate circuit), for input to the mathematical calculations, and then implementing the output of the mathematical calculations on a quantum computer.
For dependent claims 2-10 and 13-20, (2A, prong 1) these claims add additional mathematical calculations to the mathematical calculations in the independent claim.
The Examiner notes that improvements to a technology or technical field can integrate an abstract idea into a practical application at step 2A, prong 2 or amount to significantly more than an abstract idea at step 2B. However, “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. … In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception.” See MPEP 2106.05(a). Here, the specification states that the mathematical calculations have give a technical improvement of generating quantum state preparation circuits that are not as deep, which helps speed execution to prevent decoherence (see spec. background and summary). However, in the claims, the improvement is provided by the judicial exception alone, i.e. from the mathematical calculations. The additional elements, even in combination with the abstract idea, do not provide an inventive concept, as explained above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11, 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bergholm et al., Quantum circuits with uniformly controlled one-qubit gates, see attached NPL.
In reference to claim 1, Bergholm discloses a quantum state preparation circuit generation method, performed by a computer device, the method comprising: obtaining a target vector (arbitrary n-qubit quantum state, page 4, B. State preparation); generating a quantum state intermediate preparation circuit for preparing the target vector on N qubits, the quantum state intermediate preparation circuit comprising N qubit uniform control gates, and N being a positive integer greater than or equal to 2 (intermediate circuit of uniformly controlled one-cubit gates is generated, see sections II and II on pages 2-3 explaining uniformly controlled gates, and sections IV and V on pages 3-6 on how the uniformly controlled gates are used in state preparation); and converting each of the N qubit uniform control gates into a diagonal unitary matrix and a single bit gate to obtain a quantum state preparation circuit for preparing the target vector on the N qubits (see sections II and II on pages 2-3 and in particular the explanation of the recursive decomposition function f on page 3, second column and diagonal unitary matrices on page 2) by: implementing the diagonal unitary matrix in a recursive manner using a unitary operator of a first type and a unitary operator of a second type (see recursive algorithm on page 3, second column: cubits are replaced with Rz gates, which are the first type, and CNOT gates, which are the second type), the unitary operator of the first type being configured to perform phase shift on quantum states of n qubits (Rz gates control z rotation and therefore perform a phase shift), and the unitary operator of the second type being configured to restore quantum states of last
r
t
qubits in the n qubits to quantum states when the diagonal unitary matrix is inputted, wherein
1
≤
r
t
<
n
≤
N
, and
r
t
and n are integers (CNOT gate, e.g. dependent claim 10 explicitly states CNOT gates may be the second type).
In reference to claim 11, Bergholm discloses quantum state preparation method, performed by a computer device or a quantum computer, the method comprising: obtaining a quantum state preparation circuit by converting N qubit uniform control gates into a diagonal unitary matrix and a single bit gate in a quantum state intermediate preparation circuit that prepares a target vector on N qubits (intermediate circuit of uniformly controlled one-cubit gates is generated, see sections II and II on pages 2-3 explaining uniformly controlled gates, and sections IV and V on pages 3-6 on how the uniformly controlled gates are used in state preparation); and implementing the diagonal unitary matrix in a recursive manner busing a unitary operator of a first type and a unitary operator of a second type (see sections II and II on pages 2-3 and in particular diagonal unitary matrices on page 2, and the explanation of the recursive decomposition function f on page 3, second column: cubits are replaced with Rz gates, which are the first type, and CNOT gates, which are the second type) the unitary operator of the first type being configured to perform phase shift on quantum states of n qubits (Rz gates control z rotation and therefore perform a phase shift), the unitary operator of the second type being configured to restore quantum states of last rt qubits in the n qubits to quantum states when the diagonal unitary matrix is inputted, wherein
1
≤
r
t
<
n
≤
N
, and
r
t
and n are integers (CNOT gate, e.g. dependent claim 10 explicitly states CNOT gates may be the second type); and executing the quantum state preparation circuit on a quantum computing device comprising the N qubits (the circuit can then be implemented on a quantum computer, see page 6, IV. Discussion).
In reference to claim 12, this claim is directed to an apparatus associated with the method claimed in claim 1 and is therefore rejected under a similar rationale.
The Examiner notes that claims 2-10 and 13-20 are deliberately omitted from the 102 / 103 rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mozafari, Zhao, Li, and Sun all teach quantum state preparation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew T. Chiusano whose telephone number is (571)272-5231. The examiner can normally be reached M-F, 10am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tamara Kyle can be reached at 571-272-4241. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW T CHIUSANO/Primary Examiner, Art Unit 2144