DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed November 11th, 2022. Claims 1-20 are pending, of which claims 1-20 are currently rejected.
Domestic Benefit
Acknowledgment is made of applicant's claim for the benefits and priority to the Provisional U.S. Application Number 63/280,233 that was filed on October 19th, 2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/11/2022, 12/01/2025 is in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-11, 13-16, and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “logic to receive a floating-point value for the first input operand”. While claim 2 specifies the first input operand as a floating-point value, claim 1 specifies the first input operand as an integer value, which is contradicting. It is unclear whether the first input operand is to be received as an integer value or floating point value. For examination purposes, the first input operand will be construed to be received as either a floating point or an integer value as consistent with ¶ 0035 of the instant specification. Appropriate correction is required.
Claims 3-11 depend upon claim 2 and are therefore also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim 13 recites the limitation “logic to receive a floating-point value for the first input operand”. While claim 13 specifies the first input operand as a floating-point value, claim 12 specifies the first input operand as an integer value, which is contradicting. It is unclear whether the first input operand is to be received as an integer value or floating point value. For examination purposes, the first input operand will be construed to be received as either a floating point or an integer value as consistent with ¶ 0035 of the instant specification. Appropriate correction is required.
Claims 14-16 depend upon claim 13 and are therefore also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim 18 recites the limitation “logic to receive a floating-point value for the first input operand”. While claim 18 specifies the first input operand as a floating-point value, claim 17 specifies the first input operand as an integer value, which is contradicting. It is unclear whether the first input operand is to be received as an integer value or floating point value. For examination purposes, the first input operand will be construed to be received as either a floating point or an integer value as consistent with ¶ 0035 of the instant specification. Appropriate correction is required.
Claims 19-20 depend upon claim 18 and are therefore also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, 17, and 18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites receiving of values to carry out a multiply-add operation. Below are the limitations of claim 1 that recite an abstract idea under mathematical concepts or mental steps:
A first input operand comprising an integer value and second and third input operands comprising floating-point values; and (mathematical concepts)
Fused multiply-add to process the first, second and third input operands to produce a floating-point result (mathematical concepts)
All limitations as indicated describe “mathematical concepts” or “mental steps”.
At Step 2A Prong 2, these are the additional elements recited in claim 1:
A floating-point unit incorporating functionality to enable a fused multiply-add instruction
Logic to receive
Fused multiply-add logic
These additional elements are generic computer components and do not integrate the judicial exception into a practical application of the exception. See MPEP 2106.05(f). All additional elements represent no more than mere instructions to apply the judicial exception on a computer. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
There are insignificant extra-solution activities that must be made of note:
Logic to receive (insignificant extra-solution activity)
At Step 2B, there are no additional elements claimed that amount to significantly more than the recited judicial exception. These additional elements are at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept.
In regards to the insignificant extra-solution activity found in this limitation “logic to receive”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains well, understood, routine and conventional even upon reconsideration. Thus, this limitation does not amount to significantly more.
Even when considered in combination, these additional elements represent mere instructions to apply an exception, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 2, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Below are the limitations of claim 2 that recite an abstract idea under mathematical concepts or mental steps:
A first input operand comprising an integer value and second and third input operands comprising floating-point values; and (mathematical concepts)
A floating-point value for the first input operand (mathematical concepts)
Wherein in response to the first input operand comprising the floating-point value
Processes the first, second, and third input operands to produce the floating-point result (mathematical concepts)
All limitations as indicated describe “mathematical concepts” or “mental steps”.
At Step 2A Prong 2, these are the additional elements recited in claim 2:
Logic to receive a floating-point value
These additional elements are generic computer components and do not integrate the judicial exception into a practical application of the exception. See MPEP 2106.05(f). All additional elements represent no more than mere instructions to apply the judicial exception on a computer. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
There are insignificant extra-solution activities that must be made of note:
Logic to receive a floating-point value (insignificant extra-solution activity)
At Step 2B, there are no additional elements claimed that amount to significantly more than the recited judicial exception. These additional elements are at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept.
In regards to the insignificant extra-solution activity found in this limitation “logic to receive a floating-point value”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains well, understood, routine and conventional even upon reconsideration. Thus, this limitation does not amount to significantly more.
Even when considered in combination, these additional elements represent mere instructions to apply an exception, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 17, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites receiving of values to carry out a multiply-add operation Below are the limitations of claim 17 that recite an abstract idea under mathematical concepts or mental steps:
A method for performing a fused multiply-add (mathematical concepts)
A first input operand comprising an integer value and a second and third input operands comprising floating-point values (mathematical concepts); and
Processing the first, and second, and third input operands to produce a floating-point result (mathematical concepts)
All limitations as indicated describe “mathematical concepts” or “mental steps”.
At Step 2A Prong 2, these are the additional elements recited in claim 17:
A fused multiply-add instruction
Receiving a first input operand
These additional elements are generic computer components and do not integrate the judicial exception into a practical application of the exception. See MPEP 2106.05(f). All additional elements represent no more than mere instructions to apply the judicial exception on a computer and in the case of the instruction, to merely generally link the abstract idea to a computing environment. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
There are insignificant extra-solution activities that must be made of note:
receiving a first input operand (insignificant extra-solution activity)
At Step 2B, there are no additional elements claimed that amount to significantly more than the recited judicial exception. These additional elements are at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept.
In regards to the insignificant extra-solution activity found in this limitation “receiving a first input operand”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains well, understood, routine and conventional even upon reconsideration. Thus, this limitation does not amount to significantly more.
Even when considered in combination, these additional elements represent mere instructions to apply an exception, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 18, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Below are the limitations of claim 18 that recite an abstract idea under mathematical concepts or mental steps:
A floating-point value for the first input operand,
Wherein in response to the first input operand comprising the floating-point value,
Processing the first, second and third input operands to produce the floating-point result.
All limitations as indicated describe “mathematical concepts” or “mental steps”.
At Step 2A Prong 2, these are the additional elements recited in claim 18:
Receiving a floating-point value
These additional elements are generic computer components and do not integrate the judicial exception into a practical application of the exception. See MPEP 2106.05(f). All additional elements represent no more than mere instructions to apply the judicial exception on a computer. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
There are insignificant extra-solution activities that must be made of note:
receiving a floating-point value (insignificant extra-solution activity)
At Step 2B, there are no additional elements claimed that amount to significantly more than the recited judicial exception. These additional elements are at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept.
In regards to the insignificant extra-solution activity found in this limitation “receiving a floating-point value”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains well, understood, routine and conventional even upon reconsideration. Thus, this limitation does not amount to significantly more.
Even when considered in combination, these additional elements represent mere instructions to apply an exception, which do not provide an inventive concept. The claim is not eligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 17-18 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Siu et al. (7225323) included in the IDS filed 11/11/2022 (hereinafter “Siu”).
Regarding claim 1, Siu teaches:
A floating-point unit incorporating functionality to enable a fused multiply-add instruction, comprising:
logic to receive a first input operand comprising an integer value and second and third input operands comprising floating-point values (receiving of operands for various instructions such as FMAD (floating point FMA Fig. 3 302 first table) and IMAD (integer multiply add FMA Fig. 3 302 second table) to carry out floating point or integer operations (Abstract, Col. 2 Lines 29-31 and Col 2 Lines 54-57),having as inputs A, B , C (Col. 2 Lines 66-67 and Col. 5 line 1) which can be either floating point or integer values, (floating point values also comprising an integer value as discussed in Col. 8 Lines 12-23) or if input received is integer and operation to be carried out is FMAD, I2F conversion can occur as discussed in Col. 14 Lines 31-39); and
fused multiply-add logic to process the first, second, and third input operands to produce a floating-point result (Fig. 1 shows FMA circuitry in order to process a b and C and produce an FMA result through FMAD or IMAD instruction).
Regarding claim 2, Siu teaches:
The floating-point unit of claim 1, further comprising:
logic to receive a floating-point value for the first input operand (receiving of operands for various instructions such as FMAD (floating point FMA Fig. 3 302 first table) and IMAD (integer multiply add FMA Fig. 3 302 second table) to carry out floating point or integer operations (Abstract, Col. 2 Lines 29-31 and Col 2 Lines 54-57),having as inputs A, B , C (Col. 2 Lines 66-67 and Col. 5 line 1) which can be either floating point or integer values, (floating point values also comprising an integer value as discussed in Col. 8 Lines 12-23)), wherein in response to the first input operand comprising the floating-point value, the fused multiply-add logic processes the first, second, and third input operands to produce the floating-point result (Col. 8 Lines 55-62 final result returned and outputted having the same format as the input, so if inputs are floating point or the instruction if floating point, output or FMA operation floating point).
Regarding claim 3, Siu teaches:
The floating-point unit of claim 2, wherein the fused multiply-add logic further performs:
selecting an exponent of the first input operand to output in response to the first input operand comprising the floating-point value (Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for FMAD and IMAD operation; also discussed at Col. 26 Lines 55-62); and
selecting a hardcoded value to output for the first input operand in response to the first input operand comprising the integer value (Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for FMAD and IMAD operation; also discussed at Col. 26 Lines 55-62).
Regarding claim 4, Siu teaches:
The floating-point unit of claim 3, wherein the selected exponent of the first input operand or the selected hardcoded value are inputted to shift amount logic to determine an amount to shift the third input operand (Col. 38 lines 18-29 exponent information including final exponent selection output from 616 used in order to determine shift amount of third operand).
Regarding claim 5, Siu teaches:
The floating-point unit of claim 3, further comprising a multiplexer to perform the selecting the exponent and the selecting the hardcoded value depending on whether the first input operand comprises the integer value or the floating-point value (Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for FMAD and IMAD operation; also discussed at Col. 26 Lines 55-62).
Claims 17 and 18 recite the method practiced by the apparatus of claims 1 and 2 respectively and are therefore rejected for the same reasons therein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-11 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Siu further in view of Moriya et al. (EP 1662667 A1) (hereinafter “Moriya”).
Regarding claim 6, while Siu teaches floating-point unit of claim 2 as well as selecting a value for the mantissa depending on the input type (Siu: Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for FMAD and IMAD operation; also discussed at Col. 26 Lines 55-62), Siu does not explicitly each selecting an absolute value for the mantissa when the input is an integer.
However, Moriya teaches absolute value selection for mantissa through floating point truncation to select absolute value for integer operands (Moriya: ¶ 0081 under modified example).
It would be obvious before the effective filing date of the claimed invention to combine the absolute value selection as taught by Moriya with the apparatus as taught by Siu because both teachings are directed towards implementation of floating-point arithmetic. One with ordinary skill in the art would be motivated to combine the teachings because doing so would help eliminate negative values, making computation more manageable and efficient (Moriya: ¶ 0081).
Regarding claim 7, Siu in view of Moriya further teaches:
The floating-point unit of claim 6, wherein the multiplier multiplies one of the selected absolute value of the first input operand and the selected mantissa of the first input operand with the mantissa of the second input operand (Siu: Col. 11 Lines 1-12 multiplication of selected mantissas; Col. 13 Lines 11-22 preparation and selection of mantissas of op A and B for multiplication).
Regarding claim 8, Siu in view of Moriya further teaches:
The floating-point unit of claim 6, further comprising a multiplexer to perform the selecting the mantissa of the first input operand and the selecting the absolute value of the first input operand depending on whether the first input operand comprises the integer value or the floating-point value (Siu: Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for FMAD and IMAD operation; also discussed at Col. 26 Lines 55-62).
Regarding claim 9, while Siu teaches the floating-point unit of claim 2 as well as selecting a value for the mantissa depending on the input type (Siu: Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for floating point and integer operation(Siu: Col. 26 Lines 55-62) and carrying out multiplication with respective mantissas to be output by the multiplier (Siu: Col. 11 Lines 1-12 multiplication of selected mantissas; Col. 13 Lines 11-22 preparation and selection of mantissas of op A and B for multiplication), Siu does not explicitly each selecting an absolute value for the mantissa and output when the input is an integer.
However, Moriya teaches absolute value selection for mantissa through floating point truncation to select absolute value for integer operands (Moriya: ¶ 0081 under modified example).
The motivation to combine with respect to claim 6 is applies equally to claim 9.
Regarding claim 10, Siu in view of Moriya teaches:
The floating-point unit of claim 9, wherein the selected output of the multiplier or the selected absolute value is inputted to an adder to add to the third input operand (Siu: Fig. 7A takes input BB from MUX 616 and inputs through 704 to 706 (adders)).
Regarding claim 11, Siu in view of Moriya teaches:
The floating-point unit of claim 9, wherein the second input operand inputted to the multiplier is limited to a power of two in response to the first input operand comprising the integer value and the multiplier being bypassed to output the absolute value of the first input operand (Siu: Col. 15 Lines 7-22 bypass paths around multiplier 414).
Claims 19-20 recite the method practiced by the apparatus of claims 6 and 9 respectively and are therefore rejected for the same reasons therein.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kaul et al. (10,474,458) included in the IDS filed 11/11/2022 (hereinafter “Kaul”) further in view of Siu.
Regarding claim 12, Kaul teaches:
A system, comprising:
a plurality of processing cores (Kaul: plurality of parallel processors 200 i.e., processor cores as shown in Fig. 2A);
a cache memory (Kaul: processors having memory crossbar 216 coupled to L2 Cache 221 i.e., cache memory as shown in Fig. 2B); and
a plurality of artificial intelligence accelerators that produce artificial intelligence processing results to return to the cache memory for processing by the processing cores (Kaul: accelerators as processing array 212 having clusters 214, to return results through I/O unit 204 back to memory crossbar 216 and therethrough the cache memory L2 as shown in Fig. 2B; also discussed in Col. 9 lines 58-66), wherein the artificial intelligence accelerators include a plurality of processing tiles having floating-point units incorporating functionality to enable a fused multiply-add instruction (Kaul: each cluster 214 includes arithmetic logic units i.e., floating point units as discussed in Col. 9 Lines 26-38).
Kaul does not explicitly teach each floating-point unit comprising:
logic to receive a first input operand comprising an integer value and second and third input operands comprising floating-point values (Siu: receiving of operands for various instructions such as FMAD (floating point FMA Fig. 3 302 first table) and IMAD (integer multiply add FMA Fig. 3 302 second table) to carry out floating point or integer operations (Abstract, Col. 2 Lines 29-31 and Col 2 Lines 54-57),having as inputs A, B , C (Col. 2 Lines 66-67 and Col. 5 line 1) which can be either floating point or integer values, (floating point values also comprising an integer value as discussed in Col. 8 Lines 12-23) or if input received is integer and operation to be carried out is FMAD, I2F conversion can occur as discussed in Col. 14 Lines 31-39); and
fused multiply-add logic to process the first, second, and third input operands to produce a floating-point result (Siu: Fig. 1 shows FMA circuitry in order to process a b and C and produce an FMA result through FMAD or IMAD instruction).
In combining Siu with Kaul, the floating-point unit of Siu as shown in Fig. 4 replaces the arithmetic logic units of Kaul.
It would be obvious before the effective filing date of the claimed invention to combine the floating point units as taught by Siu with system as taught by Kaul because both teachings are directed towards the implementation of fused multiply-add operations. One with ordinary skill in the art would be motivated to combine the teachings because the floating-point unit of Siu advantageously differentiates between operation types as well as the format of each input received (Col. 10 Lines 10-26).
Regarding claim 13, Kaul in view of Siu further teaches:
The system claim 12, further comprising:
logic to receive a floating-point value for the first input operand, wherein in response to the first input operand comprising the floating-point value (Siu: receiving of operands for various instructions such as FMAD (floating point FMA Fig. 3 302 first table) and IMAD (integer multiply add FMA Fig. 3 302 second table) to carry out floating point or integer operations (Abstract, Col. 2 Lines 29-31 and Col 2 Lines 54-57),having as inputs A, B, C (Col. 2 Lines 66-67 and Col. 5 line 1) which can be either floating point or integer values, (floating point values also comprising an integer value as discussed in Col. 8 Lines 12-23)), the fused multiply-add logic processes the first, second, and third input operands to produce the floating-point result (Siu: Col. 8 Lines 55-62 final result returned and outputted having the same format as the input, so if inputs are floating point or the instruction if floating point, output or FMA operation floating point).
The motivation to combine with respect to claim 12 applies equally to claim 13.
Regarding claim 14, Kaul in view of Siu further teaches:
The system of claim 13, wherein the fused multiply-add logic further performs:
selecting an exponent of the first input operand to output in response to the first input operand comprising the floating-point value (Siu: Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for FMAD and IMAD operation; also discussed at Col. 26 Lines 55-62); and
selecting a hardcoded value to output for the first input operand in response to the first input operand comprising the integer value (Siu: Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for FMAD and IMAD operation; also discussed at Col. 26 Lines 55-62).
The motivation to combine with respect to claim 12 applies equally to claim 14.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kaul further in view of Siu further in view of Moriya.
Regarding claim 15, while Kaul in view of Siu teaches the system of claim 13 as well as selecting a value for the mantissa depending on the input type (Siu: Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for FMAD and IMAD operation; also discussed at Col. 26 Lines 55-62), Kaul in view of Siu does not explicitly each selecting an absolute value for the mantissa when the input is an integer.
However, Moriya teaches absolute value selection for mantissa through floating point truncation to select absolute value for integer operands (Moriya: ¶ 0081 under modified example).
It would be obvious before the effective filing date of the claimed invention to combine the absolute value selection as taught by Moriya with the system as taught by Kaul in view of Siu because all teachings are directed towards implementation of floating-point arithmetic. One with ordinary skill in the art would be motivated to combine the teachings because doing so would help eliminate negative values, making computation more manageable and efficient (Moriya: ¶ 0081).
Regarding claim 16, while Kaul in view of Siu teaches the system of claim 13 as well as selecting a value for the mantissa depending on the input type (Siu: Col. 13 Lines 37-54 selection mux 616 selects a multiplication value (including mantissa and exponent) for floating point and integer operation (Siu: Col. 26 Lines 55-62) and carrying out multiplication with respective mantissas to be output by the multiplier (Siu: Col. 11 Lines 1-12 multiplication of selected mantissas; Col. 13 Lines 11-22 preparation and selection of mantissas of op A and B for multiplication), Kaul in view of Siu does not explicitly each selecting an absolute value for the mantissa and output when the input is an integer.
However, Moriya teaches absolute value selection for mantissa through floating point truncation to select absolute value for integer operands (Moriya: ¶ 0081 under modified example).
The motivation to combine with respect to claim 15 applies equally to claim 16.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ho et al. (7346643) teaches floating point processors for performing a multiply-add operation, taking in inputs of various formats as well as being able to convert intermediate results from one format to the other and route various intermediate results via multiplexers when needed.
Elmer et al. (US 2021/0157549 A1) teaches performing multiply-accumulate operations for both integers and non-integers through both shared and separate multipliers and adders.
Anderson et al. (US 2017/0185379 A1) teaches a fused multiply-add (FMA) low functional unit having registers to store respective first, second, and third floating point input operands. Final results are rounded and normalized after the FMA operation has taken place.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
Prosecution Insights