Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06/10/2026 have been fully considered but they are not persuasive.
Applicant argues that the Tolpygo reference discloses that the target thickness of the top Nb layer is 250 nm, the bottom wiring layer was 200 nm, while the thickness of the Al etched-stopped layer was 8 nm and therefore Tolpygo appears to disclose that the superconducting material forming a line is the Nb layer, not the Al layer.
However, it is unclear why this disclosure necessitates the Nb layer being designated as the first line. It appears that the Al layer meets the limitation of a superconducting material forming the first line.
Applicant argues that if the Al etched stopped layer is interpreted as the first line in Tolpygo, the first line would not be formed directly on and in contact with the first substrate.
However, the Nb layer directly underneath the Al layer is interpreted as the substrate.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 10, 13-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Tolpygo (“Deep sub-micron stud-via technology of superconductor VLSI circuits”).
Tolpygo teaches an interconnection between lines of superconducting material at least one via in contact with those lines (abstract), a first substrate, which carries at least one first line of a first superconducting material (Al, fig. 4(a)), at least one first via of a second superconducting material, different from the first superconducting material said first line, said at least one first line (Al) being disposed between said first substrate (Nb underlayer) and said first via (Nb stud, fig. 4(b)), and at least one second line above said first via and in contact with the latter (Nb Mi+1; fig. 4(f)). Additionally, it appears that the Al layer meets the limitation of a superconducting material forming the line and the Nb layer directly underneath the Al layer is interpreted as the substrate (the Al layer is contact with the Nb layer beneath (substrate) and the first via (Nb stud)).
Regarding claims 4-5, Tolpygo teaches SiO2 covering the first line (fig. 4(f)).
Regarding claim 10, Tolpygo teaches a method for producing lines of superconducting material and vias in contact with those lines (abstract) comprising forming a first substrate a first superconductor layer of at least one superconducting material, of a thickness at least equal to the thickness of a first line and a first via (Nb and Al; fig. 4(a)), etching said first superconducting layer to form a first via (fig. 4(b)), then etching said layer to form at least one first line between said first substrate and said first via (Al) (fig. 4(c)), the first layer comprising a first sub layer of a first superconducting material (Al) forming a first line and a second sub layer of a second superconducting material forming the via (Nb) (fig. 4(a)-(f)), and forming at least one second line above said first via and in contact with the via (Nb Mi+1; fig. 4(f)). Additionally, it appears that the Al layer meets the limitation of a superconducting material forming the line and the Nb layer directly underneath the Al layer is interpreted as the substrate (the Al layer is contact with the Nb layer beneath (substrate) and the first via (Nb stud)).
Regarding claim 13, Tolpygo teaches stopping at the upper surface of said first sub layer (Al) (fig. 4(b).
Regarding claims 14-18, Tolpygo teaches a second line comprising forming in advance at least one second via, then the second line (the process can be repeated as many times as there are wiring layers in the process (text associated with figure 4). Additionally, Tolpygo teaches covering the first line with a dielectric material forming a second substrate (SiO2 deposition; fig. 4(d)-(e)).
Regarding claim 19-20, Tolpygo teaches step b being carried out by partial etching of said first superconducting layer, leaving part of that layer intact (fig. 4(b)) and that the etching is carried out with photolithography (page 4 and fig. 4(a)-(f)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-3, 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tolpygo (“Deep sub-micron stud-via technology of superconductor VLSI circuits”) in view of Ou (US 2021/0184095).
Tolpygo teaches a product and method as described above in claim 1 and 10, respectively, but fails to teach that the superconducting material is chosen from TiN, inter alia.
Ou, however, teaches a superconducting nanowire (abstract) wherein the material of the superconducting nanowire is TiN, Nb, inter alia (para. 0017).
Therefore, it would have been obvious to one of ordinary skill in the art to provide the nanowire of Tolpygo as TiN in order to provide a known superconductor material for a nanowire on a circuit as taught by Ou.
Regarding claims 3 and 12, the combined prior art teach the first line is aluminum (fig. 4, Tolpygo) and first via formed of TiN (Ou).
Claim(s) 6, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tolpygo.
Regarding claim 6, Tolpygo teaches that the process (including the first lines) has a 0.5 micrometer pitch (page 3, second column). This value is close enough to less than 500 nm such that one of ordinary skill in the art would have expected them to have the same properties. MPEP 2144.05 (I).
Regarding claim 9, Tolpygo teaches that the superconductor interconnects are for use in digital circuits (5. Conclusion). Therefore, it would have been obvious to one of ordinary skill in the art to provide the substrate as part of a circuit. It appears that the substrate is contact with first line (first line interpreted as Mi (Nb), via (Al) and the substrate includes SiO2 covering the Si wafer; fig. 4(a)-(e)).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tolpygo in view of Roberts (US 2019/0267692).
Tolpygo teaches a product as described above in claim 1, but fails to teach a first line of thickness between 40-300 nm.
Roberts, however, teaches a transmission line for a qubit (abstract) wherein the etch stop layer has a thickness between 20-100 nm (para. 0089).
Therefore, it would have been obvious to one of ordinary skill in the art to provide the etch stop layer (Al) of Tolpygo having a thickness of 20-100 nm in order to provide a configuration known in the art as taught by Roberts.
Additionally, the range of Roberts overlaps with the claimed range such that the claimed range is obvious. MPEP 2144.05 (I).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tolpygo in view of Roberts (US 2019/0267692) and Renzas (US 11276727).
Tolpygo teaches a product as described above in claim 1, but fails to teach the first line has a thickness H1 and at least one via being of thickness between H1 and ½ H1.
Renzas, however, teaches a superconducting via (abstract) having a thickness of 100 nm (col. 25, line 55-col. 26, line 10).
Therefore, it would have been obvious to one of ordinary skill in the art to provide the via of Tolpygo having a thickness of 100 nm in order to provide a configuration known in the art as taught by Renzas.
Roberts teaches the etch stop layer having a thickness of 100 nm as described above with regard to claim 7, which rejection is incorporated herein by reference.
Therefore, it appears that the thickness of the etch stop layer (first line) (100 nm) and via (100 nm) overlaps with the claimed range in claim 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A WARTALOWICZ/Primary Examiner, Art Unit 1735
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