DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The foreign document (Republic of Korea 10-2022-0064172) has been translated into English and has been acknowledged. Additionally, the Applicant’s statement invoking the common ownership exception under 35 U.S.C 102(b)(2)(C) has overcome the previous rejection. Accordingly, the previous rejection over LEE et al. (U.S. 2022/0310515 A1) in the Office action mailed on 05/08/2026 is hereby withdrawn. However, a new ground of rejection under 35 U.S.C. 102(a)(1) is newly applied in view of the prior art to KIM et al. (U.S 2022/0102334 A1), as set forth below:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-8, 10, and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (U.S 2022/0102334 A1).
As to claim 1, KIM et al. disclose in Fig. 5B a three-dimensional semiconductor memory device, comprising:
a first substrate (212) comprising a cell array region (“memory cell region” MEC) and a contact region (CON) (Fig. 5B, para. [0057]);
a peripheral circuit structure (“plurality of lower circuits” CT1) on the first substrate (212) (Fig. 5B, para. [0060]);
a cell array structure (“memory cell array” MCA) on the peripheral circuit structure (“plurality of lower circuits “ CT1) (Fig. 5B, para. [0048]-[0049], [0060]), wherein the cell array structure (“memory cell array” MCA) comprises a stack structure (“gate stack” GS) comprising interlayer dielectric layers (see “insulating films” 156 in MEC and CON regions, Fig. 5B) and gate electrodes (“gate lines” 130) that are alternately stacked on the peripheral circuit structure (“plurality of lower circuits “ CT1) (Fig. 5B, para. [0055], [0056], [0060], [0073]-[0074], [0078]), a dielectric layer (“comprising “connection-unit insulating film” 114 and “interlayer insulating film” 160) on the stack structure (“gate stack” GS) (Fig. 5B, para. [0093], [0108]), and
a second substrate (comprising “insulating films” 187, 193 & 195) on the stack structure (“gate stack” GS) (Fig. 5B, para. [0095]-[0096]), wherein the gate electrodes (“gate lines” 130) comprise pad portions (“conductive pad regions” 112) having a stepwise structure on the contact region (CON) (Fig. 5B, para. [0073]-[0074], [0091]);
a vertical separation dam structure (“dam structure” DM) that penetrates the dielectric layer (comprising “connection-unit insulating film” 114 and “interlayer insulating film” 160) and at least a portion of the stack structure (“gate stack” GS), wherein the vertical separation dam structure (“dam structure” DM) penetrates at least one of the pad portions (“conductive pad regions” 112) (see Fig. 5B, para. [0098]-[0101]);
a mold structure (comprising “a plurality of insulating plugs” 104 and “insulating island” INS) that is adjacent to the vertical separation dam structure (“dam structure” DM), wherein the mold structure (comprising “a plurality of insulating plugs” 104 and “insulating island” INS) comprises a dielectric material (Fig. 5B, para. [0099], [0100], [0101]); and
through structures (comprising “second contact plugs” 126B, “insulating plug” 115, “common source line contact plugs” 162, &” interlayer insulating film” 164) that penetrate the dielectric layer (comprising “connection-unit insulating film” 114 and “interlayer insulating film” 160) and the mold structure (comprising “a plurality of insulating plugs” 104 and “insulating island” INS) (Fig. 5B, para. [0095]-[0096], [0106], [0108]).
As to claim 2, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations including the limitation: wherein the mold structure (comprising “a plurality of insulating plugs” 104 and “insulating island” INS) comprises residual interlayer dielectric layers (see “insulating films” 156 in INS) and residual sacrificial layers (“sacrificial insulating film” PL) that are alternately stacked (Fig. 5B, para. [0099]), wherein the residual interlayer dielectric layers (see “insulating films” 156 in INS) are adjacent to respective ones of the interlayer dielectric layers (see “insulating films” 156 in MEC and CON regions, Fig. 5B) opposite the vertical separation dam structure (“dam structure” DM) (see Fig. 5B, para. [0099]-[0100]), and wherein the residual sacrificial layers (“sacrificial insulating film” PL) are adjacent respective ones of the gate electrodes (“gate lines” 130) opposite the vertical separation dam structure (“dam structure” DM) (see Fig. 5B, para. [0099]).
As to claim 3, as applied to claims 1 and 2 above, KIM et al. disclose in Fig. 5B all claimed limitations including the limitation: wherein the residual interlayer dielectric layers (see “insulating films” 156 in INS) comprise silicon oxide (Fig. 5B, para. [0078]), and wherein the residual sacrificial layers (“sacrificial insulating film” PL) comprise silicon nitride (“silicon nitride film”, para. [0099]) (Fig. 5B, para. [0099]).
As to claim 4, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations including the limitation: wherein the through structures (comprising “second contact plugs” 126B, “insulating plug” 115, “common source line contact plugs” 162, &” interlayer insulating film” 164) penetrate a portion of the second substrate (comprising “insulating films” 187, 193 & 195), and wherein a top surface of each of the through structures (comprising “second contact plugs” 126B, “insulating plug” 115, “common source line contact plugs” 162, &” interlayer insulating film” 164) is in contact with the second substrate (comprising “insulating films” 187, 193 & 195) {through structures having at least 126B & 115 is in contact with the second substrate, see Fig. 5B}.
As to claim 5, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations including the device further comprising: a residual lower sacrificial layer (see “residual lower sacrificial layer PL” as annotated in Fig. 5B below) between the mold structure (comprising “a plurality of insulating plugs” 104 and “insulating island” INS) and the second substrate (comprising “insulating films” 187, 193 & 195) (see annotated Fig. 5B below), wherein the residual lower sacrificial layer (as annotated in Fig. 5B below) is in contact with the vertical separation dam structure (“dam structure” DM), and wherein the through structures (comprising “second contact plugs” 126B, “insulating plug” 115, “common source line contact plugs” 162, &” interlayer insulating film” 164) penetrate the residual lower sacrificial layer (as annotated in Fig. 5B below (see annotated Fig. 5B below).
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As to claim 7, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations including the device further comprising: vertical channel structures (“plurality of channel structures” 180) that penetrate the stack structure (“gate stack” GS) and have top surfaces in contact with the second substrate (comprising “insulating films” 187, 193 & 195), wherein bottom surfaces of the through structures (comprising “second contact plugs” 126B, “insulating plug” 115, “common source line contact plugs” 162, &” interlayer insulating film” 164) are coplanar with bottom surfaces of the vertical channel structures (“plurality of channel structures” 180) the {the through structures comprise at least the bottom surfaces of “contact plugs” 162 that are coplanar with bottom surfaces of the vertical channel structures 180} (see Fig. 5B, para. [0079]-[0080]).
As to claim 8, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations including the limitation: wherein the cell array structure (“memory cell array” MCA) further comprises conductive lines (“gate lines” 130), connection contact plugs (comprising “plurality of first contact structures” CTS1, “contact plug” 116) (Fig. 5B, para. [0055], [0095]), and connection circuit lines (comprising “conductive lines” 218) between the peripheral circuit structure (“plurality of lower circuits” CT1) and the stack structure (“gate stack” GS) (see Fig. 5B, para. [0061]-[0062]), and wherein the through structures (comprising “second contact plugs” 126B, “insulating plug” 115, “common source line contact plugs” 162, &”interlayer insulating film” 164) are electrically connected to the peripheral circuit structure (“plurality of lower circuits” CT1) through the conductive lines (130), the connection contact plugs (comprising “plurality of first contact structures” CTS1, “contact plug” 116), and/or the connection circuit lines (comprising “conductive lines” 218) (Fig. 5B, para. [0061]-[0062], [0096], [0100]-[0101]).
As to claim 10, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations including the limitation: wherein a top surface of the vertical separation dam structure (“dam structure” DM) is in contact with the second substrate (comprising “insulating films” 187, 193 & 195) (Fig. 5B).
As to claim 12, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations including the limitation: wherein the vertical separation dam structure (“dam structure” DM) has a polygonal or circular annular shape when viewed in plan (Fig. 5B).
As to claim 13, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations including the limitation: wherein an outer sidewall of the mold structure (comprising “a plurality of insulating plugs” 104 and “insulating island” INS) is in contact with an inner sidewall of the vertical separation dam structure (“dam structure” DM) (Fig. 5B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (U.S 2022/0102334 A1) in view of KIM et al. (U.S 2022/0115294 A1).
As to claim 6, as applied to claim 1 above, KIM et al. (U.S 2022/0102334 A1) disclose in Fig. 5B all claimed limitations including the limitation: wherein each of the through structures (comprising “second contact plugs” 126B, “insulating plug” 115, “common source line contact plugs” 162, &” interlayer insulating film” 164) is in a respective through structure hole (Fig. 5B, para. [0184]), wherein ones of the through structures (comprising “second contact plugs” 126B, “insulating plug” 115, “common source line contact plugs” 162, &” interlayer insulating film” 164) comprise: a barrier layer (“insulating plug” 115) that conformally overlaps an inner sidewall and a bottom surface of the respective through structure hole (Fig. 5B, para. [0095]-[0096]); and a conductive pattern (126B) in an inner space of the respective through structure hole, the inner space being surrounded by the barrier layer (“insulating plug” 115) in a plan view (see Fig. 5B, para. [0096]), wherein the barrier layer (“insulating plug” 115) comprises at least one of a silicon nitride or a silicon oxide (Fig. 5B, para. [0113]), and wherein the conductive pattern (126B) comprises at least one of a doped semiconductor, a metal (see para. [0096], 126B is inherently made from a metal), or a transition metal.
KIM et al. (U.S 2022/0102334 A1) do not disclose the barrier layer comprises at least one of titanium nitride or tantalum nitride.
However, KIM et al. (U.S 2022/0115294 A1) disclose in Fig. 6B a three-dimensional semiconductor memory device, comprising: through structures (“penetration plugs” TP1), wherein the through structures (“penetration plugs” TP1) comprise a barrier layer (“a barrier metal layer”, para. [0097]) that comprises at least one of titanium nitride or tantalum nitride (Fig. 6B, para. [0097]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the device of KIM et al. (U.S 2022/0102334 A1) by utilizing at least one of titanium nitride or tantalum nitride to form the barrier layer as taught by KIM et al. (U.S 2022/0115294 A1), in order to utilize a known barrier material recognized in the art for its superior thermal stability and excellent diffusion barrier properties.
Claim(s) 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (U.S 2022/0102334 A1) in view of LIM et al. (U.S 2022/0139456 A1).
As to claim 9, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations including the limitation: wherein the vertical separation dam structure (“dam structure” DM) is in a vertical separation dam structure trench (a trench corresponding to the vertical separation dam structure DM) (Fig. 5B), wherein the vertical separation dam structure (“dam structure” DM) comprises:
a buried pattern (buried body of DM) in an inner space of the vertical separation dam structure trench (a trench corresponding to the vertical separation dam structure DM) (Fig. 5B, para. [0098]), and wherein the buried pattern (buried body of DM) comprises an impurity-doped semiconductor material, an impurity-undoped intrinsic semiconductor material, or a polycrystalline semiconductor material (the buried pattern/body of DM may include “a polycrystalline semiconductor material”/“polysilicon film”, para. [0098]).
KIM et al. do not disclose the vertical separation dam structure comprises: a first protection layer that conformally is on an inner sidewall and a bottom surface of the vertical separation dam structure trench; a second protection layer that overlaps an inner sidewall of the first protection layer; and wherein the inner space is surrounded by the second protection layer in a plan view, wherein the first protection layer comprises a silicon oxide layer or a silicon oxynitride layer, wherein the second protection layer comprises a silicon nitride layer.
However, LIM et al. disclose in Fig. 10A a three-dimensional semiconductor memory device comprising: the vertical separation dam structure (DM) (Fig. 10A, para. [0081]-[0084]) comprises: a first protection layer (“first insulation liner” 142) that conformally is on an inner sidewall and a bottom surface of the vertical separation dam structure trench (“dam hole” DMH) (Fig. 10A, para. [0082]); a second protection layer (“second insulation liner” 144) that overlaps an inner sidewall of the first protection layer (“first insulation liner” 142) (Fig. 10A, para. [0082]); and wherein the inner space is surrounded by the second protection layer (“second insulation liner” 144) in a plan view (Fig. 10A), wherein the first protection layer (“first insulation liner” 142) comprises a silicon oxide layer (“silicon oxide”, para. [0082]) or a silicon oxynitride layer, wherein the second protection layer (“second insulation liner” 144) comprises a silicon nitride layer (“silicon nitride”, para. [0082]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the device of KIM et al. by providing the vertical separation dam structure comprises: a first protection layer that conformally is on an inner sidewall and a bottom surface of the vertical separation dam structure trench; a second protection layer that overlaps an inner sidewall of the first protection layer; wherein the inner space is surrounded by the second protection layer in a plan view, wherein the first protection layer comprises a silicon oxide layer or a silicon oxynitride layer, and wherein the second protection layer comprises a silicon nitride layer as taught by LIM et al., in order to prevent moisture penetration and improve the structure reliability of the dam structure.
As to claim 11, as applied to claim 1 above, KIM et al. disclose in Fig. 5B all claimed limitations except for the limitation: wherein a bottom surface of each of the through structures and a bottom surface of the vertical separation dam structure are coplanar with each other.
However, LIM et al. disclose in Fig. 10A a three-dimensional semiconductor memory device comprising: through structures (YDC6, D180) and a vertical separation dam structure (DM), wherein a bottom surface of each of the through structures (YDC6, D180) and a bottom surface of the vertical separation dam structure (DM) are coplanar with each other (Fig. 10A, para. [0079]-[0083], [0125]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the device of KIM et al. by providing a bottom surface of each of the through structures and a bottom surface of the vertical separation dam structure that are coplanar with each other as taught by LIM et al., in order to simplify the manufacturing process and ensure uniform etching depth across the substrate.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The foreign document (Republic of Korea 10-2022-0064172) has been translated into English and has been acknowledged.
Additionally, the Applicant’s statement invoking the common ownership exception under 35 U.S.C 102(b)(2)(C) has overcome the previous rejection over LEE et al. (U.S. 2022/0310515 A1) in the Office action mailed on 05/08/2026. However, a new ground of rejection under 35 U.S.C. 102(a)(1) is newly applied in view of the prior art to KIM et al. (U.S 2022/0102334 A1) as mentioned above.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 October 10, 2026
