DETAILED ACTION
This action is in response to the filing 02/11/2026. Claims 1-20 are pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are rejected under 35 U.S.C. 101.
Claims 1, 3-8, 10-14, and 16-20 are rejected under 35 U.S.C. 102.
Claims 2, 9, and 15 are rejected under 35 U.S.C. 103.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 for reciting abstract ideas (Step 2A; prong 1) without additional elements that integrate the judicial exception into a practical application (Step 2A; prong 2) or that amount to significantly more (Step 2B). The claims recite abstract ideas including, at least, “identifying” and “comparing” steps that are recited at a high level of generality such that they could be performed by the human mind, where the courts do not distinguish between mental process that may be performed by a human alone and a human using pen and paper, including with computer components or in a computer environment, see 2106.04(a)(2)(III)(C). Accordingly, the claims are found to contain ineligible subject matter under 35 U.S.C. 101 following a subject matter eligibility test which may be found in MPEP 2106.
Claim 1
Step 1:
The claim recites an apparatus.
Step 2A Prong 1: Abstract Idea
Claim 1 recites,
identify a plurality of fully correctable patterns… This limitation is a step that covers performance of this limitation in the mind in the form of making an observation regarding pattern matching. Therefore, this limitation recites a mental process. See MPEP 2106.04(a)(2)(III).
compare the plurality of fully correctable patterns with an error-bit pattern of correctable errors… This limitation is a step that covers performance of this limitation in the mind in the form of making an observation regarding comparison. Recited at a high level of generality, merely performing a comparison between two gathered patterns is a mental process. See MPEP 2106.04(a)(2)(III).
Step 2A Prong 2: Additional Elements
Claim 1 recites,
and generate an alert if the error-bit pattern does not match any of the plurality of fully correctable patterns. The limitation is merely sending data in the form of an alert, and has been found to be an extra-solution activity that is understood as merely nominal to the claim, see MPEP 2106.05(g)(3).
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Claim 1 additionally recites,
a substrate; … a microcontroller on the substrate; Merely performing the above step(s) on a computer in its ordinary capacity for tasks or merely adding a general-purpose computer or computer components after the fact to an abstract idea does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2).
Step 2B: Significantly More
Claim 1 recites,
and generate an alert if the error-bit pattern does not match any of the plurality of fully correctable patterns. The limitation is merely sending data in the form of an alert, and has been found to be an extra-solution activity that is understood as merely nominal to the claim, see MPEP 2106.05(g)(3).
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Claim 1 additionally recites,
a substrate; … a microcontroller on the substrate; Merely performing the above step(s) on a computer in its ordinary capacity for tasks or merely adding a general-purpose computer or computer components after the fact to an abstract idea does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2).
Claim 2 recites,
wherein one or more bits of the ECC in the memory controller are reallocated to non-error detection operations.
This limitation merely describes the ordinary task of computers assigning bit allocation. Merely performing the above step(s) on a computer in its ordinary capacity for tasks or merely adding a general-purpose computer or computer components after the fact to an abstract idea does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Claim 3 recites,
wherein the error-bit pattern is a cumulative error-bit pattern.
The above limitation merely describes data, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3). The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Claim 4 recites,
wherein the alert predicts a future uncorrectable error.
The above limitation merely describes data, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3). The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Claim 5 recites,
wherein the alert is generated further based on micro-level fault data.
The above limitation merely describes data used to generate further data (an alert), this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3). The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Claim 6 recites,
wherein the alert is generated further based on a part number associated with the memory device.
The above limitation merely describes data used to generate further data (an alert), this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3). The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Claim 7 recites,
wherein generation of the alert includes one or more of an activation of a telemetry indicator, a storage of the alert to a serial presence detect (SPD) table in the memory device, or a storage of the alert to a system non-volatile memory.
The above limitation merely describes the method data is communicated, therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3). Additionally, Merely performing the above step(s) on a computer in its ordinary capacity for tasks or merely adding a general-purpose computer or computer components after the fact to an abstract idea does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2).
Claims 8-13 are rejected under 35 U.S.C. 101 for the same reasons as Claims 1-7. Claim 8’s recitation of “a memory module” is merely adding a general-purpose computer or computer components after the fact to an abstract idea does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2).
Claims 14-20 are rejected under 35 U.S.C. 101 for the same reasons as Claims 1-7.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-8, 10-14, and 16-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Zhou et al. (U.S. PGPub No. 20220050603).
Regarding Claim 1, Zhou teaches,
An apparatus to predict failure of a memory device, comprising: a substrate (a substrate with a controller ("logic") configured to identify memory faults including predict uncorrectable errors [0139]; where the faulty prediction engine may be implemented as a microcontroller (140) [0030]; where there may be a memory module (120) [Fig. 1; (770) of Fig. 7]);
and a microcontroller on the substrate to execute an ECC-aware analysis to: identify a plurality of fully correctable patterns associated with error correction code (ECC) in a memory controller associated with the memory device (where the system looks at bit error patterns in making fault predictions, including identifying whether a fault will be fully correctable by ECC [0041]; where the faulty prediction engine may be implemented as a microcontroller (140) [0030]; where Fig. 7 is in accordance with Fig. 1 [0099]; where controller (720) may be coupled to a memory bus [0105]);
compare the plurality of fully correctable patterns with an error-bit pattern of correctable errors of data read from the memory device (where page predictor (146) of controller (140) represents the ability to generate predictions of pages to offline to avoid errors due to underlying faults (thus, "of data read from the memory module")[0038]; the page predictor compares ECC prediction information ("error-bit pattern") to ECC patterns, and where the page predictor includes determining if a fault is full correctable by ECC ("fully correctable error patterns") [0041]);
and generate an alert if the error-bit pattern does not match any of the plurality of fully correctable patterns (uncorrectable error patterns are further detected [0031; 0039]; the examiner notes that, therefore, detection of an uncorrectable error means a "not match" with a fully correctable pattern; detection of an uncorrectable error (UE) prompts candidacy for offlining a page [0041]; where the system indicates to the OS which pages should be offlined ("alert") [0038]; pages containing fully correctable errors do not necessarily need to be offlined [0080]).
Regarding Claim 3, Zhou teaches,
The apparatus of claim 1, wherein the error-bit pattern is a cumulative error-bit pattern (the error bit patterns are correlated based on historical error information ("cumulative") [0031]).
Regarding Claim 4, Zhou teaches,
The apparatus of claim 1, wherein the alert predicts a future uncorrectable error. (where pages that should be offlined prompt an indication ("alert") [0038]; indications to identify pages to offline are predictive (meaning the uncorrectable errors have not yet occurred and offlining occurs, ideally, prior to the UE) [0042])
Regarding Claim 5, Zhou teaches,
The apparatus of claim 1, wherein the alert is generated further based on micro-level fault data (uncorrectable errors (discussed above, prompting alert [0038]) may be predicted based on microlevel fault indicators [0056]).
Regarding Claim 6, Zhou teaches,
The apparatus of claim 1, wherein the alert is generated further based on a part number associated with the memory device (where uncorrectable errors prompt alert [0038]; where microlevel information is used to determine uncorrectable errors [0056]; where microlevel information may include hardware configuration information associated with the error data, such as (dual inline) memory module manufacturer part number [0045]).
Regarding Claim 7, Zhou teaches,
The apparatus of claim 1, wherein generation of the alert includes one or more of an activation of a telemetry indicator, a storage of the alert to a serial presence detect (SPD) table in the memory device, or a storage of the alert to a system non-volatile memory (where the indication of an offlining recommendation corresponding to a UE may be communicated via telemetry [0042]).
Claims 8 and 10-13 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being unpatentable over Zhou for the same reasons as Claims 1 and 3-7.
Claims 14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being unpatentable over Zhou for the same reasons as Claims 1 and 3-7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Chhabra et al. (U.S. PGPub No. 20190087354).
Regarding Claim 2, Zhou does not appear to disclose and Chhabra teaches,
The apparatus of claim 1, wherein one or more bits of the ECC in the memory controller are reallocated to non-error detection operations (in a system directed to memory integrity in addition to encryption [0003]; the system may repurpose underutilized bits, including ECC bits [0045]; where the MAC values replacing ECC data are used to detect data attacks (thus, rather than error detection) [0003]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory fault detection system of Zhou to incorporate the memory integrity features of Chhabra. The resulting combination results in increased memory integrity protection [0024] with a lower-relative-overhead by repurposing bits [0045].
Claims 9 and 15 are each rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Chhabra for the same reasoning as Claim 2.
Response to Arguments
Applicant’s arguments filed 02/11/2026 have been fully considered and are not persuasive.
Applicant argues that the rejection under 35 U.S.C. 101 should be withdrawn because “all independent claims are directed to apparatuses, which are explicitly cited as patentable subject matter.” The Examiner agrees that the independent claims recite a patent-eligible statutory category and respectfully points that this is reflected in both rejection above and the previous rejection in the OA dated 11/14/2025. There exist two criteria for determining subject matter eligibility under 35 U.S.C. 101: 1) the claimed invention must be directed to one of the four statutory category (Step 1 of the Subject Matter Eligibility (SME) test) and 2) the claimed invention must also qualify as patent-eligible subject matter, i.e., the claim must not be directed to a judicial exception unless the claim as a whole includes additional limitations amounting to significantly more than the exception (Step 2 of the SME test), see MPEP 2106. The claims are directed to a judicial exception without amounting to significantly more, as analyzed under Step 2 of the SME test. No argument or evidence have been provided as to the content of the rejection under 35 U.S.C. 101. The rejection is maintained.
Applicant argues that “Zhou fails to disclose or suggest comparison of known correctable error patterns with bit patterns representing the dedicated correctable errors of data read from memory.” The Examiner respectfully disagrees. The Examiner reproduces par. 38 & 41 of Zhou, cited above in the rejection under 35 U.S.C. 102 [emphasis added]:
[0038] In one example, controller 140 includes page predictor 146. Page predictor 146 represents the ability of controller 140 to generate a prediction of pages to offline to avoid uncorrectable errors. Page predictor 146 generates an estimate of pages for OS 114 to offline based on the underlying faults in memory [examiner note: “read from memory”] 130. System 100, through controller 140, can predict uncorrectable errors in memory 130. Page predictor 146 can determine how the UEs would affect different physical pages of memory, and indicate to OS 114 an estimate of which pages should be offlined.
[0041] Page predictor 146 looks at bit error patterns in making faulty page predictions. In one example, page predictor 146 compares error prediction information to ECC patterns [examiner note: “known” correctable error patterns]. In one example, controller 140 understands how ECC 150 applies error correction in system 100. Based on the ECC patterns or how ECC is applied at host 110, page predictor 146 can determine if a fault is fully correctable by ECC or partially correctable by ECC. If a fault is fully correctable, it is not likely to generate a UE. If the fault is only partially correctable, the fault may be prone to causing a UE, which makes the fault a good candidate for offlining a page.
Accordingly, the Examiner finds that Zhou does teach comparing known correctable error bit patterns with errors of data read from memory and maintains the rejection under 35 U.S.C. 102.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.E.W./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113