DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 18 March 2026 have been fully considered but they are not persuasive. Applicant’s arguments with respect to the prior art have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 6, 7, 12-14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Asver (U.S. Publication 2014/0133782) in view of Nakamura (U.S. Publication 2021/0136253), Bouazizi (U.S. Publication 2021/0409818), and Nagpal (U.S. Patent 11,561,826).
As to claim 1, Asver discloses a special-effect editing method (p. 1, section 0014; a visual effect editing method, reading on a special effect editing method, is disclosed), comprising:
by an editor, receiving a first editing operation, generating a first editing instruction corresponding to the first editing operation, and writing the first editing instruction into an instruction cache queue (p. 2, section 0021; p. 2-3, section 0030; p. 3, sections 0039-0040; an editing operation is received and a corresponding instruction is generated and written to an edit stack, which reads on an instruction cache queue because it is an ordered list of instructions to perform edits on an image);
by a resource manager, executing editing instructions in the instruction cache queue in sequence, and in response to executing the first editing instruction, editing a first object corresponding to the first editing instruction according to the first editing instruction (p. 4, sections 0050-0052; p. 5, section 0075; software acts as a resource manager, executing the instructions from the edit stack/queue, and editing the selected image objects in response to the instructions);
sending the second object to the graphic engine and rendering the second object by the graphic engine (fig. 4; the image is rendered in a web browser, necessitating some sort of graphic software, reading on a graphic engine, to render).
Asver does not disclose but Nakamura does disclose, by a graphic engine, loading objects corresponding to the editing instructions in the instruction cache queue in sequence (p. 2, sections 0023-0027; p. 3, section 0045; p. 5, sections 0087-0088; p. 5, sections 0097-0099; instructions in an order list, reading on a cache queue, are performed in the list order; this includes reading/loading shape unit objects for each list item). The motivation for this is to quickly execute raster/RIP operations (p. 2, sections 0022-0026). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Asver to load objects corresponding to the editing instructions in the instruction cache queue in sequence in order to quickly execute raster/RIP operations as taught by Nakamura.
Asver does not disclose, but Bouazizi does disclose upon loading a first object corresponding to the first editing instruction, sending request information for requesting loading a second object to the resource manager, the second object being an object obtained by the resource manager by editing the first object according to the first editing instruction and sending the second object to the graphic engine in response to the request information by the resource manager (p. 14, sections 0134-0135; in response to loading an object that has been instructed to be significantly changed/edited, a request is sent to a pipeline/resource manager to load the changed/edited object, which would correspond to the claimed second object; in response, the object is sent as part of the current view to a presentation/graphic engine). The motivation for this is to respond to changes significant enough to impact media access. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Asver and Nakamura to, in response to loading an object corresponding to the first editing instruction, send request information for requesting loading a second object to the resource manager, the second object being an object obtained by the resource manager by editing the first object according to the first editing instruction and send the second object to the graphic engine in response to the request information by the resource manager in order to respond to changes significant enough to impact media access as taught by Bouazizi.
Asver does not disclose, but Nagpal discloses wherein the executing the editing instructions in the instruction cache queue in sequence by the resource manager (fig. 1; the system manager acts as a resource manager and creates task/instruction queues to be executed in sequence) comprises: executing the editing instructions in the instruction cache queue in sequence (col. 1, lines 41-47; col. 8, lines 28-42; color operations, resizing, scaling, and cropping are all editing tasks/instructions to be executed from the queues in sequence) through a plurality of execution threads in parallel by the resource manager (col. 5, line 59-col. 6, line 25; the system/resource manager manages a number of parallel execution threads) wherein once any execution thread completes its current task and becomes available, it is assigned the next to-be-executed editing instruction in the instruction cache queue (fig. 4; col. 13, lines 6-25; when a thread has completed its task and is free, it dequeues the next task/instruction in its assigned queue and is assigned to complete it) and directly executes the editing instruction, without awaiting the completion of the execution of any preceding editing instruction in the same instruction cache queue (fig. 4; col. 13, lines 59-61; in “non-blocking” mode, the task/instruction is executed directly with no wait for preceding tasks/instructions in the queue).
The motivation for this is to achieve high utilization of the computing power of the system (col. 4, lines 27-35; col. 15, lines 13-33). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Asver, Nakamura, and Bouazizi to execute the editing instructions in the instruction cache queue in sequence through a plurality of execution threads in parallel by the resource manager, wherein, once any execution thread completes its current task and becomes available, it is assigned the next to-be-executed editing instruction in the instruction cache queue and directly executes the editing instruction, without awaiting the completion of the execution of any preceding editing instruction in the same instruction cache queue. in order to achieve high utilization of the computing power of the system as taught by Nagpal.
As to claim 6, Asver discloses wherein the method further comprises: before the graphic engine renders the second object, by the editor, receiving a second editing operation, generating a second editing instruction corresponding to the second editing operation, and writing the second editing instruction into the instruction cache queue (p. 2, section 0021; p. 2-3, section 0030; p. 3, sections 0039-0040; a number of editing operations are received and corresponding instructions are generated and written to an edit stack, which reads on an instruction cache queue because it is an ordered list of instructions to perform edits on an image; this would include second, third, fourth, etc. editing operations and instructions).
As to claim 7, see the rejection to claim 1.
As to claim 12, see the rejection to claim 6.
As to claim 13, see the rejection to claim 1. Further, Asver discloses an electronic device, comprising: a memory and a processor, the memory being configured to store a computer program; the processor being configured to, when executing the computer program, causes the electronic device to implement the special-effect editing method (p. 5, section 0082-p. 6, section 0088).
As to claim 14, see the rejections to claims 1 and 13.
As to claim 19, see the rejection to claim 6.
Claims 3, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Asver in view of Nakamura, Bouazizi, and Nagpal and further in view of Otsuka (U.S. Publication 2022/0261952).
As to claim 3, Asver does not disclose, but Otsuka does disclose wherein the loading the objects corresponding to the editing instructions in the instruction cache queue in sequence by the graphic engine comprises: loading the objects corresponding to the editing instructions in the instruction cache queue in sequence through a plurality of loading threads in parallel by the graphic engine (p. 5, section 0086; p. 5, section 0089-p. 6, section 0092; the command buffer reads on an instruction queue, and drawing instructions, which read on editing instructions since they edit the displayed image or frame buffer, are executed in sequence through parallel threads managed by a GPU acting as a resource manager; executing the instructions would also necessarily load objects necessary for the execution of drawing commands). The motivation for this is to streamline image generation from a plurality of applications (p. 1, section 0008). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Asver, Nakamura, Bouazizi, and Nagpal to load objects corresponding to the editing instructions in the instruction cache queue in sequence through a plurality of loading threads in parallel by the graphic engine in order to streamline image generation from a plurality of applications as taught by Otsuka.
As to claim 9, see the rejection to claim 3.
As to claim 16, see the rejection to claim 3.
Claims 4, 5, 10, 11, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Asver in view of Nakamura, Bouazizi, and Nagpal and further in view of Brown (U.S. Patent 7,928,989).
As to claim 4, Asver does not disclose, but Brown does disclose wherein the method further comprises: by the resource manager, generating a first feedback message corresponding to the first editing instruction (figs. 5a, 5b; col. 4, lines 25-49; col. 6, lines 18-35; the geometry processing unit acts as a resource manager, providing primitive resources to the next pipeline stage, and generates feedback for a transformation/editing instruction), and writing the first feedback message into a first feedback message queue (figs. 5a, 5b; col. 4, lines 25-49; the feedback is written to a feedback buffer/queue); and by the editor, reading and outputting feedback messages in the first feedback message queue in sequence (fig. 2; the buffered feedback is output to CPU, GPU, vertex processing unit, and geometry processing unit, each of which performs transformations on the data and could read on an editor; as buffer contents, the feedback would be read out and then the next data would be written into the buffer, and again read out, in sequence until processing stops). The motivation for this is to allow a graphics pipeline to directly process the results of the graphics rendering pipeline (col. 2, lines 39-52). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Asver, Nakamura, Bouazizi, and Nagpal to by the resource manager, generate a first feedback message corresponding to the first editing instruction, write the first feedback message into a first feedback message queue, and by the editor, read and output feedback messages in the first feedback message queue in sequence in order to allow a graphics pipeline to directly process the results of the graphics rendering pipeline as taught by Brown.
As to claim 5, Asver does not disclose, but Brown does disclose wherein the method further comprises: by the graphic engine, generating a second feedback message corresponding to the first editing instruction (figs. 5a, 5b; col. 4, lines 25-49; col. 6, lines 18-35; the geometry processing unit acts as a graphic engine, processing triangles and other geometry for the next pipeline stage, and generates feedback for a transformation/editing instruction; note that claim 5 is not dependent on claim 4, so there is no issue in using the geometry processing unit in Brown to teach different components in each of the claims), and writing the second feedback message into a second feedback message queue (figs. 5a, 5b; col. 4, lines 25-49; the feedback is written to a feedback buffer/queue); and by the editor, reading and outputting feedback messages in the second feedback message queue in sequence (fig. 2; the buffered feedback is output to CPU, GPU, vertex processing unit, and geometry processing unit, each of which performs transformations on the data and could read on an editor; as buffer contents, the feedback would be read out and then the next data would be written into the buffer, and again read out, in sequence until processing stops). Motivation for the combination is given in the rejection to claim 4.
As to claim 10, see the rejection to claim 4.
As to claim 11, see the rejection to claim 5.
As to claim 17, see the rejection to claim 4.
As to claim 18, see the rejection to claim 5.
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Asver in view of Nakamura, Bouazizi, and Nagpal and further in view of Uchibori (JP 2019169082 A, herein represented by a translation).
As to claim 21, Asver does not disclose, but Nagpal discloses wherein performing tasks with the objects corresponding to the editing instructions in the instruction cache queue in sequence by the graphic engine comprises (fig. 1; col. 1, lines 41-47; col. 8, lines 28-42; the system manager acts as an engine and creates task/instruction queues to be executed in sequence; color operations, resizing, scaling, and cropping are all tasks/instructions making this a graphic engine) comprises: performing tasks with the objects corresponding to the editing instructions in the instruction cache queue in sequence (col. 1, lines 41-47; col. 8, lines 28-42; color operations, resizing, scaling, and cropping are all editing tasks to be executed from the queues in sequence) through a plurality of task threads in parallel by the graphic engine (col. 5, line 59-col. 6, line 25; the system/resource manager manages a number of parallel threads) wherein once any task thread completes its current task and becomes available, it is assigned the next to-be-performed task object corresponding to an editing instruction in the instruction cache queue (fig. 4; col. 13, lines 6-25; when a thread has completed its task and is free, it dequeues the next task in its assigned queue and is assigned to complete it) and directly operates on the object, without awaiting the completion of performing tasks for the object corresponding to any preceding editing instruction in the same instruction cache queue (fig. 4; col. 13, lines 59-61; in “non-blocking” mode, the task is executed directly with no wait for preceding tasks/instructions in the queue). Motivation for the combination is given in the rejection to claim 1.
Nagpal does not teach, but Uno teaches that the task which is not waited on is a loading task (p. 6-7; when a load dependent queue is provided, further unrelated loads can be queued and performed without waiting for the completion of a preceding load instruction). The motivation for this is to efficiently use the processing units in the device. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Asver, Nakamura, Bouazizi, and Nagpal to directly perform loading tasks without waiting for completion of previous loading tasks in order to efficiently use the processing units in the device as taught by Uchibori.
As to claim 22, see the rejection to claim 21.
As to claim 23, see the rejection to claim 21.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON M RICHER whose telephone number is (571)272-7790. The examiner can normally be reached 9AM-5PM.
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/AARON M RICHER/Primary Examiner, Art Unit 2617
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