DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 101
3. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
3.1 Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 2A- Prong One
The claim(s) recite(s) an apparatus, device, and method, comprising: The step of: “emulating,…, a hardware component to provide an emulated hardware component, wherein the emulated hardware component is capable of exercising a predetermined functionality”; ”testing the emulated hardware component”; “determining, …, whether the emulated hardware component exercised the predetermined functionality during the test, wherein the determining comprises, responsive to the testing, detecting, by … of the programmable logic device, whether the emulated hardware component sequenced through a plurality of states associated with the predetermined functionality”; and “responsive to the detection of whether the emulated hardware component sequenced through the plurality of states, generating, …, an indicator representing a coverage of the predetermined functionality by the testing”, under the broadest reasonable interpretation fall under a mental concept. Therefore, the claims are directed to an abstract idea, by use of generic computer components and thus are clearly directed to an abstract idea, as constructed.
Step 2A Prong Two
This judicial exception is not integrated into a practical application because the additional limitation such as: “a programmable logic device”, “a state sequence detector”, “a hardware device”, “a memory” to store “data”, either alone or in combination, all serve to gather and process data and do not add anything more significantly to the judicial exception, but are mere instructions to apply the exception using a generic computer component that are well known, routine, and conventional activities (see specification at para 0077-0078, and fig.1, 6, 8) which can be of any type, including general-purpose computer (para 0077) previously known in the industries. Merely adding a programmable computer to perform generic computer functions does not automatically overcome an eligibility rejection. Alice, 573 U.S. at 223-24. Furthermore, the use of a general-purpose computer to apply an otherwise ineligible algorithm does not qualify as a particular machine. See Ultramerciallnc. v. Hulu, LLC, 772F.3d 709, 716-17 (Fed. Cir. 20l4); In re TLI Commc 'ns LLC v. AV Automotive, LLC, 823 F.3d 607, 613 (Fed. Cir. 2016) (mere recitation of concrete or tangible components is not an inventive concept); Eon Corp. IP Holdings LLC v. AT&T Mobility LLC, 785; and are not sufficient to amount to significantly more than the judicial exception (See further MPEP 2106.05(d)(i-iv)-f); thus are not patent eligible under 35 USC 101.
Step 2B
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because, as previously discussed above with reference to the integration of abstract idea into a practical application, the additional elements of: “a programmable logic device”, “a state sequence detector”, “a hardware device”, “a memory” to store “data”, either alone or in combination, all serve to gather and process data and do not add anything more significantly to the judicial exception, but are mere instructions to apply the exception using a generic computer component that are well known, routine, and conventional activities (see specification at para 0077-0078, and fig.1, 6, 8) which can be of any type, including general-purpose computer (para 0077) previously known in the industries. Merely adding a programmable computer to perform generic computer functions does not automatically overcome an eligibility rejection. Alice, 573 U.S. at 223-24. Furthermore, the use of a general-purpose computer to apply an otherwise ineligible algorithm does not qualify as a particular machine. See Ultramerciallnc. v. Hulu, LLC, 772F.3d 709, 716-17 (Fed. Cir. 20l4); In re TLI Commc 'ns LLC v. AV Automotive, LLC, 823 F.3d 607, 613 (Fed. Cir. 2016) (mere recitation of concrete or tangible components is not an inventive concept); Eon Corp. IP Holdings LLC v. AT&T Mobility LLC, 785; and are not sufficient to amount to significantly more than the judicial exception (See further MPEP 2106.05(d)(i-iv)-f); thus are not patent eligible under 35 USC 101. Therefore, using computer components amount to no more than mere instructions to perform the abstract, and thus are not sufficient to amount to significantly more than the recited abstract, as constructed.
3.2 Dependent claims 2-9, 11-15, 17-20 merely include limitations pertaining to further mathematical computations (claims 2, 17), “wherein: detecting whether the emulated hardware component sequenced through the plurality of states comprises determining, by the state sequence detector, whether the emulated hardware component transitioned from a first state of the plurality of states to a second state of the plurality of states; and determining whether the emulated hardware component transitioned from the first state to the second state comprises determining, by the state sequence detector, whether a conditional dependency group of a plurality of conditional dependency groups associated with the first state is satisfied” (mental process). (claims 3, 18-19); “wherein determining whether the conditional dependency group is satisfied comprises determining, by the state sequence detector, whether characteristics of a set of elements of the emulated hardware component satisfies a condition associated with the conditional dependency group” (mental process); (claims 4, 20); “wherein determining whether the emulated hardware component exercised the predetermined functionality further comprises determining whether the emulated hardware component sequenced through the plurality of states a predetermined number of times” (mental process); (claims 5, 12, and 16); “wherein determining whether the emulated hardware component exercised the predetermined functionality further comprises accessing a table stored in the programmable logic device, wherein the table comprises data defining the plurality of states” (mental process); (claim 6) “updating the table via an interface of the programmable logic device” (mental process); (claim 7); “wherein determining whether the emulated hardware component exercised the predetermined functionality further comprises accessing a table stored in the programmable logic device, wherein the table comprises data defining the predetermined number of times” (mental process); (claims 8, 17) “wherein the emulated hardware component comprises a plurality of elements associated with the predetermined functionality, and determining whether the emulated hardware component exercised the predetermined functionality further comprises tracking transitions among the plurality of states responsive to values provided the plurality of elements” (mental process); (claim 9) “ wherein generating the indicator comprises generating an indication of a number of times that the hardware component sequenced through the plurality of states” (mental process); (claim 11) “wherein the indicator represents whether a functional coverage associated with the predetermined functionality was covered” (mental process); (claim 12) “wherein the data further represents a count of a number of times for the hardware device to transition through the sequence of states for the functionality to be covered” (mental process); (claim 13) “wherein the semiconductor package further comprises: a usage monitor to, responsive to the indicator, determine a statistic representing a usage of the predetermined functionality; and a communication engine to communicate data representing the statistic with a remote computer system” (mental process); (claim 14) “wherein the communication engine to regulate the communication of the data with the remote computer system responsive to a user authorization policy” (mental process); “wherein the semiconductor package is part of a baseboard management controller, and the apparatus further comprises a processing core to execute machine readable management stack instruction to provide management functions for a computer platform”; all of which further amount to further mental process similar to that already recited by the independent claims and already addressed above and thus are further not patent eligible under 35 USC 101.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (USPG_PUB No. 2004/0254779), in view of Dahan et al. (USPG_PUB No. 2003/0140245).
5.1 In considering claims 1, 10, and 16, Wang et al. teaches a method comprising:
emulating, by a programmable logic device, a hardware component to provide an emulated hardware component (see para [0048], Each resource board 44 includes one or more emulation resource 48 such as a programmable gate array (FPGA) or any other type of programmable logic device (PLD). [0076], the emulation system employ programmable logic devices such as FPGAs to emulate various other components of the SoC at a lower level of abstraction to permit a designer to more thoroughly debug the design of such components), wherein the emulated hardware component is capable of exercising a predetermined functionality (see para [0107] The purpose of the emulation process is to collect "probe data" representing the time varying behavior of various signals that the DUT produces in response to test signals applied to its input. At step 124 of FIG. 7, debugging software running on the workstation helps a designer analyze the probe data collected during the emulation process to determine whether the emulated DUT behaved as expected. ); testing the emulated hardware component (see para [0037] An emulation system in accordance with the invention may employ a mix of hardware and software-based emulation resources to emulate portions of a DUT a testbench describes, to generate test signal inputs to the emulated DUT, and to acquire data representing the behavior of the response signals appearing at the probe points of the emulated DUT. The emulation system processes the testbench to determine which of its emulation resources to employ to emulate each portion of the DUT, to determine which resources will generate the test signals and which resources will monitor the emulated DUT's output signals. The emulation system then appropriately programs each emulation resource to carry out it assigned function.); determining, by the programmable logic device, whether the emulated hardware component exercised the predetermined functionality during the test (see para [0010], These circuits supply input signals to the FPGAs and monitor selected FPGA output signals during the emulation process to acquire "probe data" representing the behavior of the DUT output signals. Following the emulation process, a user may employ debugging software to analyze the probe data to determine whether the DUT will behave as expected. [0068] RAM 81 can be used for storing data representing successive states of FPGA output signals to be analyzed following the emulation process to determine whether the emulated DUT behaved as expected. [0107], At step 124 of FIG. 7, debugging software running on the workstation helps a designer analyze the probe data collected during the emulation process to determine whether the emulated DUT behaved as expected), wherein the determining comprises, responsive to the testing, detecting, by … of the programmable logic device, whether the emulated hardware component sequenced through a plurality of states associated with the predetermined functionality (see para [0080] FIG. 7 illustrates a process workstation 42 carries out to program the emulation system in response to a testbench a designer supplies in response to a description of the resources available in the emulation system. The workstation initially (step 110) processes the testbench to determine how to allocate resources for emulating the various modules of the DUT and for carrying out the test signal generation and DUT input and output signal monitoring functions the testbench describes. [0081] FIG. 19 is a conceptual block diagram illustrating how workstation 42 can implement the various functions of a testbench including generators 34, DUT 36 and monitors 37. Generators 34 control the test signals supplied as input to DUT 36 while monitors 37 monitor DUT output signals and store data representing their states for later analysis by debugging software. [0113] Many FPGAs can respond to a "read" command by generating a data sequence on an output "probe bus" indicating the states of the output signal of every clocked device, and can respond to a "write" command by setting the output signals of all of its internal clocked devices to states indicated by a data sequence supplied via the probe bus.); and responsive to the detection of whether the emulated hardware component sequenced through the plurality of states, generating, by the programmable logic device, an indicator representing a coverage of the predetermined functionality by the testing (para [0037], an emulation system in accordance with the invention may employ a mix of hardware and software-based emulation resources to emulate portions of a DUT a testbench describes, to generate test signal inputs to the emulated DUT, and to acquire data representing the behavior of the response signals appearing at the probe points of the emulated DUT. The emulation system processes the testbench to determine which of its emulation resources to employ to emulate each portion of the DUT, to determine which resources will generate the test signals and which resources will monitor the emulated DUT's output signals. Further [0113], generating a data sequence on an output "probe bus" indicating the states of the output signal of every clocked device, and can respond to a "write" command by setting the output signals of all of its internal clocked devices to states indicated by a data sequence supplied via the probe bus.). Wang et al. further teaches the semiconductor package comprising: memory and a hardware device comprising a plurality of elements capable of emulating portions of the DUT (see para [0090-0091], various portions of the testbench among resources 48 on resource boards 44, microprocessors included in transaction devices 49 and workstation 42 may be emulated. Hardware resources 48 such as FPGAs can emulate portions of DUT that need to be emulated at a low level. [0091] Software running on workstation 42 or on other computers connected via network 46 can emulate portions of DUT 36 such as embedded processors, memories and other large, well-tested IP cells for which only high-level emulation is necessary. Generator software 34 or monitor software 37 also running on the workstation 42 or other computer can emulate portions of the testbench supplying test signals to or monitoring output signals of portions of the DUT 36 emulated by other software running on the workstation 42 or other computers. Generators 34 and monitors 37 implemented by the transaction devices 44 can emulate portions of the testbench that supply test signals or monitor output signals of portions of the DUT 36 emulated by the local resources 48. Any generator 34 or monitor 37 can also control test signals inputs or monitor output signals of remote resources.), of claim 10 and 15; but he does not specifically state that a state sequence detector is used in the process.
Dahan et al. teaches the use of a state sequence detector, including monitoring whether component sequenced through the plurality of states (see para [0104], Once the entry point address is detected, the SSM transitions to state 601 if all of the entry conditions are met, if not, it transitions to violation state 630 where violation signal 304 is asserted.[0105] Each of the states 601-615 must be sequentially traversed by detecting the correct entry sequence address and corresponding entry condition signals or else the SSM transitions to violation state 630. If the sequence is correctly traversed, then secure mode state 620 is entered and security signal 302 is asserted. [0106] In a similar manner, each address of the activation sequence must appear to transition to states 602-615 and finally to secure mode state 620. An incorrect address, address timing, or an incorrect change in a condition signal will result in a transition to violation state 630, such as indicated at arc 601a).
Wang et al. and Dahan et al. are analogous art because they are from the same field of endeavor and that the model analyzes by Dahan et al. is similar to that of Wang et al. Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (]0004]).
5.2 As per claims 2, 19, the combination of Wang et al. and Dahan et al. teaches that wherein: detecting whether the emulated hardware component sequenced through the plurality of states comprises determining, by the state sequence detector, whether the emulated hardware component transitioned from a first state of the plurality of states to a second state of the plurality of states (see Dahan et al. para [0105] Each of states 601-615 must be sequentially traversed by detecting the correct entry sequence address and corresponding entry condition signals or else the SSM transitions to violation state 630. If the sequence is correctly traversed, then secure mode state 620 is entered and security signal 302 is asserted. [0106] For example, in order to transition from state 600 to state 601, the address of the entry point instruction must appear along with all of the correct condition signals listed in Table 1. The next address that appears must be the address of the next sequential instruction in order to transition to state 602, otherwise the SSM transitions to violation state 630. In a similar manner, each address of the activation sequence must appear to transition to states 602-615 and finally to secure mode state 620. An incorrect address, address timing, or an incorrect change in a condition signal will result in a transition to violation state 630, such as indicated at arc 601a. Similarly, the activation sequence is aborted if the status signals indicate that any one of the activation sequence accesses is cacheable); and determining whether the emulated hardware component transitioned from the first state to the second state comprises determining, by the state sequence detector, whether a conditional dependency group of a plurality of conditional dependency groups associated with the first state is satisfied (see Dahan et al. para [0104] Referring again to FIG. 6 state 600 is an idle state during which the SSM monitors address bus 330 looking for ESA[EP]. Once the entry point address is detected, the SSM transitions to state 601 if all of the entry conditions are met, if not, it transitions to violation state 630 where violation signal 304 is asserted. [0105] Each of states 601-615 must be sequentially traversed by detecting the correct entry sequence address and corresponding entry condition signals or else the SSM transitions to violation state 630. If the sequence is correctly traversed, then secure mode state 620 is entered and security signal 302 is asserted. [0106] For example, in order to transition from state 600 to state 601, the address of the entry point instruction must appear along with all of the correct condition signals listed in Table 1. The next address that appears must be the address of the next sequential instruction in order to transition to state 602, otherwise the SSM transitions to violation state 630. In a similar manner, each address of the activation sequence must appear to transition to states 602-615 and finally to secure mode state 620. An incorrect address, address timing, or an incorrect change in a condition signal will result in a transition to violation state 630, such as indicated at arc 601a. see further Wang et al. para [0107], At step 124 of FIG. 7, debugging software running on the workstation helps a designer analyze the probe data collected during the emulation process to determine whether the emulated DUT behaved as expected and if not, to determine what may be wrong with the DUT design). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (]0004]).
5.3 Regarding claim 3, the combination of Wang et al. and Dahan et al. teaches that wherein determining whether the conditional dependency group is satisfied comprises determining, by the state sequence detector, whether characteristics of a set of elements of the emulated hardware component satisfies a condition associated with the conditional dependency group (see Dahan et al. para [0104] Referring again to FIG. 6 state 600 is an idle state during which the SSM monitors address bus 330 looking for ESA[EP]. Once the entry point address is detected, the SSM transitions to state 601 if all of the entry conditions are met, if not, it transitions to violation state 630 where violation signal 304 is asserted. [0105] Each of states 601-615 must be sequentially traversed by detecting the correct entry sequence address and corresponding entry condition signals or else the SSM transitions to violation state 630. If the sequence is correctly traversed, then secure mode state 620 is entered and security signal 302 is asserted. [0106] For example, in order to transition from state 600 to state 601, the address of the entry point instruction must appear along with all of the correct condition signals listed in Table 1. The next address that appears must be the address of the next sequential instruction in order to transition to state 602, otherwise the SSM transitions to violation state 630. In a similar manner, each address of the activation sequence must appear to transition to states 602-615 and finally to secure mode state 620. An incorrect address, address timing, or an incorrect change in a condition signal will result in a transition to violation state 630, such as indicated at arc 601a. see further Wang et al. para [0107], At step 124 of FIG. 7, debugging software running on the workstation helps a designer analyze the probe data collected during the emulation process to determine whether the emulated DUT behaved as expected and if not, to determine what may be wrong with the DUT design.). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (]0004]).
5.4 As per claims 4, 20, the combination of Wang et al. and Dahan et al. teaches that wherein determining whether the emulated hardware component exercised the predetermined functionality further comprises determining whether the emulated hardware component sequenced through the plurality of states a predetermined number of times (see Dahan et al. para [0104] Referring again to FIG. 6 state 600 is an idle state during which the SSM monitors address bus 330 looking for ESA[EP]. Once the entry point address is detected, the SSM transitions to state 601 if all of the entry conditions are met, if not, it transitions to violates state 630 where violation signal 304 is asserted. [0105] Each of states 601-615 must be sequentially traversed by detecting the correct entry sequence address and corresponding entry condition signals or else the SSM transitions to violation state 630. If the sequence is correctly traversed, then secure mode state 620 is entered and security signal 302 is asserted. [0106] For example, in order to transition from state 600 to state 601, the address of the entry point instruction must appear along with all of the correct condition signals listed in Table 1. The next address that appears must be the address of the next sequential instruction in order to transition to state 602, otherwise the SSM transitions to violation state 630. In a similar manner, each address of the activation sequence must appear to transition to states 602-615 and finally to secure mode state 620. An incorrect address, address timing, or an incorrect change in a condition signal will result in a transition to violation state 630, such as indicated at arc 601a. see further Wang et al. para [0113] Another way to reset the emulator to a state it had at the start of some period of interest during a previous emulation process is to drive it directly to that state. Many FPGAs can respond to a "read" command by generating a data sequence on an output "probe bus" indicating the states of the output signal of every clocked device, and can respond to a "write" command by setting the output signals of all of its internal clocked devices to states indicated by a data sequence supplied via the probe bus. [0114] Referring to FIGS. 3 and 4, when operating in the variable debugging mode, local bus controller 74 can respond to a block read command in an incoming packet from workstation 42 by signaling any one of FPGAs F1-F8 the packet addresses to return a block of data via a probe bus 71 to memory controller 83 indicating the states of signals appearing at each of its internal clocked devices (latches or flip-flops). That block of data therefore acts as a "snapshot" of the state of the FPGA). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.5 Regarding claim 5, the combination of Wang et al. and Dahan et al. teaches that wherein determining whether the emulated hardware component exercised the predetermined functionality further comprises accessing a table stored in the programmable logic device, wherein the table comprises data defining the plurality of states (Dahan et al. fig.6, para [0106], For example, in order to transition from state 600 to state 601, the address of the entry point instruction must appear along with all of the correct condition signals listed in Table 1. The next address that appears must be the address of the next sequential instruction in order to transition to state 602, otherwise the SSM transitions to violation state 630. In a similar manner, each address of the activation sequence must appear to transition to states 602-615 and finally to secure mode state 620. An incorrect address, address timing, or an incorrect change in a condition signal will result in a transition to violation state 630, such as indicated at arc 601a.). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.6 As per claim 6, the combination of Wang et al. and Dahan et al. teaches the step of updating the table via an interface of the programmable logic device (see Wang et al. para [0076], the emulation system will preferably employ programmable logic devices such as FPGAs to emulate various other components of the SoC at a lower level of abstraction to permit a designer to more thoroughly debug the design of such components. [0093] As described in more detail below, the workstation 42 then analyzes the modified testbench to identify the clock signals that are to control the timing of logic operations within the DUT, and to modify the gate level description of any clock signal gating logic when necessary to eliminate clock signal skew problems (step 114).). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.7 As per claim 7, the combination of Wang et al. and Dahan et al. teaches that wherein determining whether the emulated hardware component exercised the predetermined functionality further comprises accessing a table stored in the programmable logic device, wherein the table comprises data defining the predetermined number of times (Dahan et al. fig.6, para [0106], For example, in order to transition from state 600 to state 601, the address of the entry point instruction must appear along with all of the correct condition signals listed in Table 1. The next address that appears must be the address of the next sequential instruction in order to transition to state 602, otherwise the SSM transitions to violation state 630. In a similar manner, each address of the activation sequence must appear to transition to states 602-615 and finally to secure mode state 620. An incorrect address, address timing, or an incorrect change in a condition signal will result in a transition to violation state 630, such as indicated at arc 601a.). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (]0004]).
5.8 Regarding claim 8, the combination of Wang et al. and Dahan et al. teaches that wherein the emulated hardware component comprises a plurality of elements associated with the predetermined functionality (see fig.3, 6, para [0048] FIG. 3 illustrates an example of an emulation system 40 in accordance with the invention including a computer workstation 42, one or more resource boards 44, and a packet routing network 46 comprising one or more buses that may be interconnected by conventional network routers, switches or hubs. Each resource board 44 includes one or more emulation resource 48 such as a programmable gate array (FPGA) or any other type of programmable logic device (PLD),), and determining whether the emulated hardware component exercised the predetermined functionality further comprises tracking transitions among the plurality of states responsive to values provided the plurality of elements (see Wang et al. para [0051], The transaction device 49 of each resource board 44 is designed not only to transmit and receive packets but may also to communicate with the local emulation resources 48 on that resource board using communication protocols that are appropriate to those resources. [0119] An interrupt causes microprocessor 70 (or event handler hardware local controller 50 may implement) to execute an interrupt routine telling it to signal local controller 50 to temporarily halt the system clock(s) controlling DUT logic operations and to initiate a snapshot operation wherein it saves data representing the current state of emulation resources 48 in RAM 81 (FIG. 7) and to also save data indicating the current test cycle count). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.9 With regards to claim 9, the combination of Wang et al. and Dahan et al. teaches that wherein generating the indicator comprises generating an indication of a number of times that the hardware component sequenced through the plurality of states (dr Wang et al. para [0113] Another way to reset the emulator to a state it had at the start of some period of interest during a previous emulation process is to drive it directly to that state. Many FPGAs can respond to a "read" command by generating a data sequence on an output "probe bus" indicating the states of the output signal of every clocked device, and can respond to a "write" command by setting the output signals of all of its internal clocked devices to states indicated by a data sequence supplied via the probe bus. [0119] An interrupt causes microprocessor 70 (or event handler hardware local controller 50 may implement) to execute an interrupt routine telling it to signal local controller 50 to temporarily halt the system clock(s) controlling DUT logic operations and to initiate a snapshot operation wherein it saves data representing the current state of emulation resources 48 in RAM 81 (FIG. 7) and to also save data indicating the current test cycle count). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (]0004]).
5.10 With regards to claim 11, the combination of Wang et al. and Dahan et al. teaches that wherein the indicator represents whether a functional coverage associated with the predetermined functionality was covered (see Wang et al. para [0068] RAM 81 can be used for storing data representing successive states of FPGA output signals to be analyzed following the emulation process to determine whether the emulated DUT behaved as expected. In such case local bus controller 74 is programmed to periodically sample the states of selected FPGA output signals and to pass data representing those states to memory controller 83 for storage in RAM 81. [0107] The purpose of the emulation process is to collect "probe data" representing the time varying behavior of various signals that the DUT produces in response to test signals applied to its input. At step 124 of FIG. 7, debugging software running on the workstation helps a designer analyze the probe data collected during the emulation process to determine whether the emulated DUT behaved as expected and if not, to determine what may be wrong with the DUT design.). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.11 As per claim 12, the combination of Wang et al. and Dahan et al. teaches that wherein the data further represents a count of a number of times for the hardware device to transition through the sequence of states for the functionality to be covered (see Wang et al. para [0119] An interrupt causes microprocessor 70 (or event handler hardware local controller 50 may implement) to execute an interrupt routine telling it to signal local controller 50 to temporarily halt the system clock(s) controlling DUT logic operations and to initiate a snapshot operation wherein it saves data representing the current state of emulation resources 48 in RAM 81 (FIG. 7) and to also save data indicating the current test cycle count.). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.12 With regards to claim 13, the combination of Wang et al. and Dahan et al. teaches that wherein the semiconductor package further comprises: a usage monitor to, responsive to the indicator, determine a statistic representing a usage of the predetermined functionality (see Wang et al. para [0077], The display graphically depicts how emulation resources are allocated by displaying an arrow extending from each block representing a DUT component to a block representing the resource to be used to emulate it. The designer can modify a resource allocation by using a mouse to drag the head of an arrow from one resource to another, however the resource allocation software will notify the user when the emulation resource the user selects to emulate an IC module is not of an appropriate type or capacity for emulating that resource. [0080], The workstation initially (step 110) processes the testbench to determine how to allocate resources for emulating the various modules of the DUT and for carrying out the test signal generation and DUT input and output signal monitoring functions the testbench describes.
[0081] FIG. 19 is a conceptual block diagram illustrating how workstation 42 can implement the various functions of a testbench including generators 34, DUT 36 and monitors 37. Generators 34 control the test signals supplied as input to DUT 36 while monitors 37 monitor DUT output signals and store data representing their states for later analysis by debugging software.); and a communication engine to communicate data representing the statistic with a remote computer system (see para [0053], In a "co-validation mode of operation", workstation 42 (or any other computer that may be connected to packet routing network 46) can emulate some portions of an IC while emulation resources 48 on resource boards 44 emulate other portions of the IC. [0088] Generators 34 or monitors 37 implemented by microprocessors 70 can interact with local or remote resources 48 or software running in workstation 42 emulating portions of DUT 36 in the same way, by read and write accessing appropriate memory addresses. Transactors 35 and 38 handle all of the low-level activities needed to carry out the interaction.). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.13 Regarding claim 14, the combination of Wang et al. and Dahan et al. teaches that wherein the communication engine to regulate the communication of the data with the remote computer system responsive to a user authorization policy (see Dahan et al. para [0123], No operation in the activation sequence or environment setting sequence can use the stacks until the secure stacks are set in order to prevent a security breach via the stacks, such as to restrict access. This can only be done in safe way after the environment setting sequence properly set the TLB as described in "Memory management in secure mode,".). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.14 As per claim 15, the combination of Wang et al. and Dahan et al. teaches that wherein the semiconductor package is part of a baseboard management controller (see para [0056] Example FPGA Resource Board. [0057-0058] FIG. 4 illustrates an example of one type of resource board 44 of FIG. 3 in more detailed block diagram form. The example resource board 44 includes a transaction device circuit 49 formed by an I/O block 52 and a resource controller 50. I/O block 52 includes a pair of transceivers 54 and 55 for transmitting and receiving packets via networks 46 of FIG. 3.), and the apparatus further comprises a processing core to execute machine readable management stack instruction to provide management functions for a computer platform (see Wang et al. para [0076] When processing a testbench describing SoC 90, workstation 42 (FIG. 3) determines the nature of the various components of the SoC DUT and other portions of the testbench to be emulated and then allocates available emulation resources for emulating each component. Since the IP component designers will have already tested the functionality of IP components such as processor 91 and memory 92 that may be included in SoC 90, a system for emulating SoC 90 employing IP components need only emulate the behavior of those IP components at a relatively high level of abstraction, a task which for a suitably programmed workstation is well-suited. On the other hand, the emulation system will preferably employ programmable logic devices such as FPGAs to emulate various other components of the SoC at a lower level of abstraction to permit a designer to more thoroughly debug the design of such components.). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.15 As per claim 17, the combination of Wang et al. and Dahan et al. teaches a memory coupled to the state sequence detector, wherein the memory to store data representing criteria used by the state sequence detector to determine whether the emulated device transitions through the predetermined sequence of states during the test (see Wang et al. para [0068] RAM 81 can be used for storing data representing successive states of FPGA output signals to be analyzed following the emulation process to determine whether the emulated DUT behaved as expected. [0107] The purpose of the emulation process is to collect "probe data" representing the time varying behavior of various signals that the DUT produces in response to test signals applied to its input. At step 124 of FIG. 7, debugging software running on the workstation helps a designer analyze the probe data collected during the emulation process to determine whether the emulated DUT behaved as expected and if not, to determine what may be wrong with the DUT design. See further Dahan et al. para [0105] Each of states 601-615 must be sequentially traversed by detecting the correct entry sequence address and corresponding entry condition signals or else the SSM transitions to violation state 630. If the sequence is correctly traversed, then secure mode state 620 is entered and security signal 302 is asserted. [0106] For example, in order to transition from state 600 to state 601, the address of the entry point instruction must appear along with all of the correct condition signals listed in Table 1. The next address that appears must be the address of the next sequential instruction in order to transition to state 602, otherwise the SSM transitions to violation state 630). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
5.16 Regarding claim 18, the combination of Wang et al. and Dahan et al. teaches that wherein the data further represents sets of dependency groups, wherein each set of dependency groups representing at least one criterion to be satisfied for a state transition of the sequence of states (see Wang et al. para [0011], These circuits supply input signals to the FPGAs and monitor selected FPGA output signals during the emulation process to acquire "probe data" representing the behavior of the DUT output signals. Following the emulation process, a user may employ debugging software to analyze the probe data to determine whether the DUT will behave as expected.). Therefore, it would have been obvious to person of skilled in the art at the time of filing of the applicant’s invention to combine the method of Dahan et al. with that of Wang et al. because Dahan et al. teaches the improvement of the performance of the system (para [0004]).
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
6.1 Mittal et al. (USPG_PUB No. 2024/0111660) teaches a method for managing high performance simulation representation of an emulation.
6.2 Schulbert et al. (USPG_PUB No. 2004/0025122) teaches a method and system for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level.
6.3 Zawalski et al. (2012/0317533) teaches a method and system for dynamically injecting errors to a user design having internal states and parameters is run in a functional design verification system.
6.4 Cruz (USPG_PUB No. 2022/0043954) teaches methods and systems for verifying a property of an integrated circuit hardware design. The method includes formally verifying, using a formal verification tool, that the property is true for the hardware design under a constraint that an instantiation of the hardware design transitions to a quiescent state at a symbolic time.
7. Claims 1-20 are rejected and this action is non-final. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRE PIERRE-LOUIS whose telephone number is (571)272-8636. The examiner can normally be reached M-F 9:00 AM-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMERSON C PUENTE can be reached at 571-272-3652. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDRE PIERRE LOUIS/Primary Patent Examiner, Art Unit 2187 May 8, 2026
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