DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 10th, 2026 has been entered.
Status of the Claims
Claim 1 has been amended. Claims 14-27 have been previously withdrawn. Claims 1-13 are currently examined herein.
Status of the Rejection
All 35 U.S.C. § 103 rejections from the previous office action are withdrawn in view of Applicant’s amendments.
New grounds of rejection under 35 U.S.C. § 103 rejections are necessitated by the Applicant’s amendments as outlined below.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2 and 4-13 are rejected under 35 U.S.C. 103 as being unpatentable over Cicero (2018/0266980 A1, provided in IDS submitted on 11/23/2022).
Regarding Claim 1, Cicero teaches a method for forming a nanopore cell (a process for constructing an electrochemical cell of a nanopore-based sequencing chip in Figs 13A-13G [para. 0108]), comprising:
providing a device structure (device structure described in paras. 0108-0116) comprising:
a conductive layer (conductive layer 1302 in Fig. 13A [para. 0110]) disposed on a top portion of a substrate (conductive layer 1302 is disposed in a top portion of the substrate, see Figure 13A [para. 0110]); and
an interconnect dielectric layer (a dielectric layer 1303 in Fig. 13A [para. 0110]) overlying the conductive layer (as illustrated in Fig. 13A, dielectric layer 1703 overlays conductive layer 1302);
removing a portion of the interconnect dielectric layer to form an electrode support surface (the layer of dielectric 1303 is etched to create an opening to expose a top surface of conductive layer 1302 [para. 0110]) comprising an exposed island of the conductive layer surrounded by a remaining portion of the interconnect dielectric layer (as illustrated in Figure 13A, an exposed island is created of conductive layer 1302, surrounded by dielectric 1303);
depositing a porous electrode material on the electrode support surface (a porous electrode layer 1310 is formed on the conductive layer 1302 [para. 0111]);
forming a porous electrode layer over the exposed island of the conductive layer (a porous electrode layer 1310 grown in columns is formed on the conductive layer 1302 in Fig. 13B [para. 0111]), wherein the porous electrode layer comprises columns of the porous electrode material oriented in the same direction and extending perpendicularly from the electrode support surface (as illustrated in Fig. 13B, columns of porous electrode material extend perpendicular from conductor layer 1302);
depositing a protective layer (a sacrificial metal layer, such as Ti layer 1311, in Fig. 13C [para. 0112]) on the seamless porous electrode layer (sacrificial metal layer 1311 is deposited on top of the porous electrode layer 1310 [para. 0112]);
patterning the porous electrode layer and the protective layer to form a working electrode island (the sacrificial metal layer, such as Ti layer 1311, and the porous TiN electrode layer 1310 are patterned to form a patterned stacked layer 1312 in Fig. 13D [para. 0113]), wherein the columns of the porous electrode material that form the working electrode island are oriented in the same direction (as illustrated in Fig. 13D, the patterned stacked layer 1312 is oriented in the same direction);
depositing and patterning a hydrophobic cladding (dielectric layer 1314, such as polyamide, in Fig. 13E [para. 0114]; which is etched to create a cavity 1316 [para. 0115]) on the working electrode island to form the sidewalls of a well of the nanopore cell (dielectric layer 1314 is deposited on the stacked layer 1312 to form the sidewalls of the nanopore cell in Fig. 13E [para. 0114]); and
removing at least a portion of the protective layer to expose the porous electrode layer to the well (the protective Ti layer 1311 is removed to expose a portion of the top surface area of porous TiN layer 1310 in Fig. 13G [para. 0116]), wherein the exposed porous electrode layer forms at least a portion of a bottom wall of the well of the nanopore cell (as illustrated in Figure 13G, the working electrode comprised of porous TiN 1310 forms at least a bottom portion of a bottom wall of the well).
Cicero does not explicitly teach removing a portion of the interconnect dielectric layer to form a planar electrode support surface, wherein the exposed island of the conductive layer and the remaining portion of the interconnect dielectric layer that surrounds the exposed island are coplanar, and wherein the porous electrode layer and the working electrode island are seamless.
However, in some embodiments Cicero teaches wherein the exposed island of the conductive layer and the remaining portion of the interconnect dielectric layer that surrounds the exposed island are coplanar (a polishing method may be used to remove the excess working electrode material to form the working electrode 710 having a top surface that is substantially coplanar to the top surface of the adjacent dielectric layers [para. 0134]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the step of removing a portion of the interconnect dielectric layer of Cicero to form a planar electrode support surface, wherein the exposed island of the conductive layer and the remaining portion of the interconnect dielectric layer that surrounds the exposed island are coplanar, as taught by Cicero, as using a coplanar surface of dielectric layers and working electrode allows for more working electrode surface area and better process control (Cicero, [para. 0134]). In addition, as the electrode support surface has been modified to be planar and no dielectric walls are present when depositing the porous electrode material, the porous electrode layer and the working electrode island are now seamless.
Regarding Claim 2, modified Cicero teaches the method of claim 1.
Cicero teaches wherein the porous electrode material comprises porous TiN (titanium nitride) (the porous electrode 1310 can be TiN [para. 0111]).
Regarding Claim 4, modified Cicero teaches the method of claim 1.
Cicero teaches wherein removing a portion of the interconnect dielectric comprises blanket etching a portion of the interconnect dielectric (dielectric 1303 is etched to expose a top surface of conductive layer 1302 [para. 0110]).
Regarding Claim 5, modified Cicero teaches the method of claim 1.
Cicero teaches wherein the protective layer is comprised of a dielectric material (protective layer can be formed using a silicon oxide [para. 0098]).
Regarding Claim 6, modified Cicero teaches the method of claim 1.
Cicero teaches wherein the protective layer is comprised of silicon oxide (protective layer can be formed using a silicon oxide [para. 0098]).
Regarding Claim 7, modified Cicero teaches the method of claim 1.
Cicero teaches wherein the protective layer is comprised of a metal material (sacrificial layer 1311 can be a metal such as titanium [para. 0112]).
Regarding Claim 8, modified Cicero teaches the method of claim 1.
Cicero teaches wherein the protective layer is comprised of titanium (sacrificial layer 1311 can be a metal such as titanium [para. 0112]).
Regarding Claim 9, modified Cicero teaches the method of claim 1.
Cicero teaches wherein removing at least a portion of the protective layer to expose the porous electrode layer comprises applying removal reagents to the protective layer (sacrificial Ti layer 1311 is removed by a wet etching process using hydrofluoric acid to expose the top surface area of the porous electrode TiN layer 1310 [para. 0116]).
Regarding Claim 10, modified Cicero teaches the method of claim 9.
Cicero teaches wherein the removal reagents comprise hydrofluoric acid (removal reagent can be hydrofluoric acid [para. 0116]).
Regarding Claim 11, modified Cicero teaches the method of claim 9.
Cicero teaches wherein the removal reagents are applied using a wet etching process (sacrificial Ti layer 1311 may be etched by a wet etching process [para. 0116]).
Regarding Claim 12, modified Cicero teaches the method of claim 9.
Cicero teaches wherein the removal reagents are applied to the protective layer without damaging the interconnect dielectric layer (etching processing using reagents, such as hydrofluoric acid, does not damage the polyimide layer 1312, which is the dielectric layer [para. 0116]).
Regarding Claim 13, modified Cicero teaches the method of claim 1.
Cicero teaches wherein the seamless porous electrode layer and the protective layer are patterned using photolithography and dry etching (patterning of the sacrificial metal layer and the porous TiN electrode layer can be carried out using known lithography patterning process and etching process, such as reactive ion etching [para. 0113]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cicero, as applied to claim 1 above, and in further view of Wei (Label free electrochemiluminescence protocol for sensitive DNA detection with a tris(2,2’-bipyridyl)ruthenium(II) modified electrode based on nucleic acid oxidation. Electrochemistry Communications. 2007; 9, pages 1474-1479).
Regarding Claim 3, modified Cicero teaches the method of claim 1.
Cicero is silent on wherein the porous electrode material comprises a ruthenium containing material.
Wei teaches an electrochemical sensor for detecting DNA (abstract), and teaches an electrode material comprises a ruthenium containing material (working electrode was coated with a carbon nanotube/Nafion/ruthenium(bpy)32+ composite film [first para. col. 1, page 1476]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the porous electrode material deposited on the planar electrode support of modified Cicero to include a ruthenium containing material, as taught by Wei, as ruthenium based electrodes allow for sensitive detection of nucleic acids, such as DNA (Wei, [Conclusion, page 1479]).
Response to Arguments
Applicant’s arguments, see Remarks pgs. 1-5, filed 04/10/2026, with respect to the 35 U.S.C 103 rejections have been fully considered.
Applicant’s Argument #1:
Applicant has amended independent claim 1 to recite “wherein the exposed island of the conductive layer and the remaining portion of the interconnect dielectric layer that surrounds the exposed island are coplanar” and “wherein the seamless porous electrode layer comprises columns of the porous electrode material oriented in the same direction and extending perpendicularly from the planar electrode support surface”, which is not taught by the cited prior art (see for example Fig. 13 of the instant application.
Applicant further states that as the seamless electrode is made as the porous electrode material is deposited on the planar electrode support surface, and notes that both cited prior art of Cicero and Foster teach depositing the electrode material into a well having sidewalls, which would form a seam in the electrode at the corner of the well where horizontally growing crystals would colloid with vertically growing crystals.
Examiner’s Response #1:
Applicant’s arguments have been fully considered, but are moot in view of the new grounds of rejection.
Applicant’s Argument #2:
Applicant argues that dependent claim 3 is allowable as the secondary reference of Wei does not cure the deficiencies of claim 1.
Examiner’s Response #2:
Applicant’s arguments have been fully considered, but are moot in view of the new grounds of rejection.
Conclusion
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/R.L.G./Examiner, Art Unit 1795
/SHIZHI QIAN/Primary Examiner, Art Unit 1795
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