Prosecution Insights
Last updated: April 19, 2026
Application No. 18/058,980

PHOTONIC INTEGRATED CIRCUIT PACKAGES INCLUDING SUBSTRATES WITH GLASS CORES

Non-Final OA §103
Filed
Nov 28, 2022
Examiner
BLEVINS, JERRY M
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
1072 granted / 1227 resolved
+19.4% vs TC avg
Minimal +5% lift
Without
With
+4.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
1255
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
57.0%
+17.0% vs TC avg
§102
30.4%
-9.6% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1227 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 2, 5, 6, 10, 12, 13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0130467 (“POLOMOFF”) in view of US 2020/0098736 (“LIAO”). Regarding claim 1, POLOMOFF teaches a photonic assembly (100), comprising: a substrate (146), including: a core (116) having a surface, wherein a material of the core includes glass (pars. [0027], [0036]); and a dielectric material (140; par. [0032]) on a portion of the surface of the core (FIG. 2), the dielectric material including conductive pathways (par. [0032]); a photonic integrated circuit (PIC) (112) having an active surface, wherein the PIC is coupled to surface of the core with the active surface of the PIC facing away from the surface of the core (FIGs. 1, 2; pars. [0030]-[0034]); a first optical component (118A) optically coupled to a lateral surface of the PIC and to the surface of the core (FIG. 2); and a second optical component (118B) coupled to the core, wherein the second optical component is optically coupled to the PIC by an optical pathway through the core and the first optical component (FIGs. 1, 2). POLOMOFF does not teach a processor integrated circuit (XPU) electrically coupled to the conductive pathways in the dielectric material and to the active surface of the PIC. LIAO teaches a processor integrated circuit (XPU) (400a) electrically coupled to conductive pathways in a dielectric material (216a) and to an active surface of a PIC (100a; FIG. 1C; par. [0027]). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the assembly of POLOMOFF so as to include the XPU of LIAO. The motivation would have been to achieve desired optical processing. Regarding claim 17, POLOMOFF teaches a photonic assembly (100), comprising: a substrate (146), including: a core (116) having a surface, wherein a material of the core includes glass (pars. [0027], [0036]); and a dielectric material (140; par. [0032]) on a portion of the surface of the core (FIG. 2), the dielectric material including conductive pathways (pars. [0030]-[0034]); a photonic integrated circuit (PICs) (112) having an active surface, wherein the PIC is coupled to the surface of the core with the active surface facing away from the surface of the core (FIGs. 1, 2; pars. [0030]-[0034]); a first optical component (118a), optically coupled to a lateral surface of the PIC and to the surface of the core (FIGs. 1, 2); and a second optical component (118b) coupled to the core, wherein the second optical component is optically coupled to the PIC by optical pathways through the core and the first optical component (FIGs. 1, 2). POLOMOFF does not teach a processor integrated circuit (XPU) electrically coupled to the conductive pathways in the dielectric material and to the active surface of the PIC. LIAO teaches a processor integrated circuit (XPU) (400a) electrically coupled to conductive pathways in a dielectric material (216a) and to an active surface of a PIC (100a; FIG. 1C; par. [0027]). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the assembly of POLOMOFF so as to include the XPU of LIAO. The motivation would have been to achieve desired optical processing. The additional limitations appear to merely involve duplication. It has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). As such, it would have been obvious to one of ordinary skill in the art at the effective filing date to duplicate the parts of POLOMOFF in view of LIAO as set forth in the instant claim. Regarding claims 2 and 18, POLOMOFF teaches that the first optical component includes a glass block, a glass block with a reflector, a glass block with a curved surface, a glass block with a mirror reflector, a glass block with a multi-directional reflector, a glass block with a waveguide, a glass block with a laser written waveguide, an optical lens, a micro-lens, a planar lens, or a gradient-index (GRIN) lens, and combinations thereof (par. [0030]). Regarding claim 5, POLOMOFF teaches that the optical pathway includes a waveguide (FIG. 2; par. [0038]). Regarding claims 6 and 10, POLOMOFF in view of LIAO renders obvious the limitations of the base claim 1. The additional limitations appear to merely involve duplication. It has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). As such, it would have been obvious to one of ordinary skill in the art at the effective filing date to duplicate the parts of POLOMOFF in view of LIAO as set forth in the instant claims. Regarding claim 12, POLOMOFF teaches a photonic assembly (100), comprising: a substrate (146), including: a core (116) having a surface, wherein a material of the core includes glass (pars. [0027], [0036]); a dielectric (140) with conductive traces on a portion of the surface of the core (par. [0032]); a photonic integrated circuit (PIC) (112) having an active surface and an opposed second surface (FIGs. 1, 2), wherein the PIC is optically coupled to the surface of the core with the active surface of the PIC facing towards the surface of the core (FIGs. 1, 2; pars. [0030]-[0034]); and an optical component (118a) coupled to the core, wherein the optical component is optically coupled to the PIC by an optical pathway through the core (FIGs. 1, 2). POLOMOFF does not teach a processor integrated circuit (XPU) electrically coupled to the conductive pathways in the dielectric material and to the active surface of the PIC. LIAO teaches a processor integrated circuit (XPU) (400a) electrically coupled to conductive pathways in a dielectric material (216a) and to an active surface of a PIC (100a; FIG. 1C; par. [0027]). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the assembly of POLOMOFF so as to include the XPU of LIAO. The motivation would have been to achieve desired optical processing. Regarding claim 13, POLOMOFF teaches that the core includes a waveguide (FIG. 2; par. [0038]). Claims 3, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over POLOMOFF in view of LIAO as applied to claims 1, 12, and 17, respectively, above, and further in view of US 2022/0244465 (“WINZER”). POLOMOFF in view of LIAO renders obvious the limitations of the respective base claims. POLOMOFF does not teach that the plurality of second optical components includes a fiber connector. WINZER teaches an optical component (950, 983, 988) coupled to a PIC (896), wherein the optical component is a fiber connector (pars. [0521], [0528]). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the device of POLOMOFF so as to comprise a fiber connector, as taught by WINZER. The motivation would have been to permit optical coupling to outside optical and optoelectronic devices. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over POLOMOFF in view of LIAO as applied to claim 1 above, and further in view of US 2021/0066269 (“YANG”). POLOMOFF in view of LIAO renders obvious the limitations of the base claim 1. POLOMOFF does not teach that the PIC is coupled to the surface of the core by a die attach film (DAF), a non-conductive adhesive, a B-stage underfill, or a polymer film with adhesive property. YANG teaches a PIC coupled to a surface of a core by a DAF (par. [0022]). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the device of POLOMOFF such that the PIC is coupled to the surface of the core by a die attach film, as taught by YANG. The motivation would have been to improve adherence (par. [0022]). Claims 7-9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over POLOMOFF in view of LIAO as applied to claims 1 and 17 above, and further in view of US 2021/0041649 (“BRUSBERG”). Regarding claims 7, 9, and 20, POLOMOFF in view of LIAO renders obvious the limitations of the respective base claims. POLOMOFF does not teach an IC that is electrically coupled to the PIC by the conductive pathways in the dielectric material. BRUSBERG teaches an IC (562, 662) that is electrically coupled to a PIC (570, 670) by conductive pathways in a dielectric material (534, 634). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the device of POLOMOFF such that an IC is electrically coupled to the PIC by the conductive pathways in the dielectric material, as taught by BRUSBERG. The motivation would have been to allow for application-specific electronic connectivity (pars. [0054], [0060]). Regarding claim 8, POLOMOFF teaches an interconnect die (134) embedded in the dielectric material (FIGs. 1, 2; pars. [0032], [0033]). When combined with the teachings of LIAO and BRUSBERG, as above, the interconnect die would be electrically coupled to the XPU and the IC as claimed. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over POLOMOFF in view of LIAO as applied to claim 1 above, and further in view of US 2016/0091679 (“CHOU”). POLOMOFF in view of LIAO renders obvious the limitations of the base claim 1. POLOMOFF does not teach that the second optical component is coupled by a plug or a socket. CHOU teaches an optical component (14) coupled by a plug or a socket (20). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the device of POLOMOFF such that the optical component is coupled by a plug or a socket, as taught by CHOU. The motivation would have been to allow for selective engagement and disengagement. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over POLOMOFF in view of LIAO as applied to claim 12 above, and further in view of US 2016/0327241 (“WHEATLEY”). POLOMOFF in view of LIAO renders obvious the limitations of the base claim 12. POLOMOFF does not teach that the core includes a reflector. WHEATLEY teaches core that includes a reflector (pars. [0016], [0021]). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the device of POLOMOFF such that the core includes a reflector, as taught by WHEATLEY. The motivation would have been to enhance optical uniformity (par. [0016]). Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over POLOMOFF in view of LIAO as applied to claim 12 above, and further in view of US 2022/0003948 (“ZHOU”). POLOMOFF in view of LIAO renders obvious the limitations of the base claim 12. POLOMOFF does not teach that the PIC includes through-substrate vias (TSVs). ZHOU teaches a PIC including TSVs (pars. [0041], [0088], [0095]). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the device of POLOMOFF such that the PIC includes TSVs, as taught by ZHOU. The motivation would have been to increase bandwidth (par. [0095]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY M BLEVINS whose telephone number is (571)272-8581. The examiner can normally be reached Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached at 571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JERRY M BLEVINS/Primary Examiner, Art Unit 2874
Read full office action

Prosecution Timeline

Nov 28, 2022
Application Filed
Jun 06, 2023
Response after Non-Final Action
Dec 22, 2025
Non-Final Rejection — §103
Apr 06, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12601879
Flexible Push-Pull Boot with a Transition Member
2y 5m to grant Granted Apr 14, 2026
Patent 12601867
IMAGE LIGHT GUIDE WITH ZONED DIFFRACTIVE OPTIC
2y 5m to grant Granted Apr 14, 2026
Patent 12604409
PHOTONIC INTEGRATED CIRCUIT EMBEDDED SUBSTRATE AND PHOTONIC INTEGRATED CIRCUIT PACKAGE
2y 5m to grant Granted Apr 14, 2026
Patent 12601868
OPTICAL WAVEGUIDE ARRANGEMENT WITH IMPROVED CAPACITY
2y 5m to grant Granted Apr 14, 2026
Patent 12596230
METHOD FOR MANUFACTURING A PHOTONIC CHIP
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+4.9%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 1227 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month