DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 4/6/2026.
Withdrawn objections and rejections
The specification objection has been withdrawn.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-7, 9, 11-13, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall et al. (U.S. 2014/0289494), in view of Seal et al. (U.S. 2012/0131312).
As per claim 1:
Ould-Ahmed-Vall disclosed a computer program product for facilitating processing within a computing environment, the computer program product comprising:
one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media (Ould-Ahmed-Vall: Figure 1 element 120, paragraphs 58-60) to perform a method comprising:
obtaining an instruction to be executed within the computing environment, the instruction including an operation code indicating a reduce instruction (Ould-Ahmed-Vall: Figures 3G-H and 4A elements 397-398, 402, and 416, paragraphs 85, 92, and 99)(The fetch stage obtains a vector horizontal majority voting instruction (i.e. reduce instruction), which contains an opcode, that is executed in the execute stage.); and
executing the instruction, the executing including:
selecting a field of a source operand stored in a source location, the source location designated using the instruction and the field including a plurality of bits (Ould-Ahmed-Vall: Figures 3G-H, 14A-B, and 15-16, paragraphs 85, 91-92, 96, 138-139, and 142-149)(The vector horizontal majority voting instruction indicates a source register (i.e. source location) in the instruction encoding. The immediate value allows for specifying a selected number of bits/data elements in the source operand to perform the majority vote operation on.);
performing an operation on the plurality of bits of the field to obtain a result, the result reducing the plurality of bits to a set of bits, the set of bits comprising one or more bits and having fewer bits than the plurality of bits (Ould-Ahmed-Vall: Figures 3G-H, 14A-B, and 15-16 elements 1425, 1470-1485, 1530, and 1630, paragraphs 85, 91-92, 96, 138-139, and 142-149)(The vector horizontal majority voting instruction indicates a source register (i.e. source location) in the instruction encoding. Executing the operation reduces a plurality of selected bits/data elements to a single bit within the destination register.); and
placing the result in a target location, the target location specified using the instruction (Ould-Ahmed-Vall: Figures 3G-H, 14A-B, and 15-16 elements 1425, 1470-1485, 1560, and 1660, paragraphs 85, 91-92, 96, 138-139, and 142-149)(The vector horizontal majority voting instruction indicates a source register (i.e. source location) in the instruction encoding. Executing the operation reduces a plurality of selected bits/data elements to a single bit within the destination register.).
Ould-Ahmed-Vall failed to teach the operation specified using a selected field of the instruction separate from one or more fields of the instruction specifying the operation code, and wherein the operation is one operation of a plurality of operations specified using the selected field of the instruction.
However, Seal combined with Ould-Ahmed-Vall disclosed the operation specified using a selected field of the instruction separate from one or more fields of the instruction specifying the operation code, and wherein the operation is one operation of a plurality of operations specified using the selected field of the instruction (Seal: Figures 13-15, paragraphs 194 and 198-199)(Ould-Ahmed-Vall: Figures 3F-H elements 382, 384, 387-389, and 397-398, paragraphs 84-85, 91-92, and 96)(Ould-Ahmed-Vall disclosed an embodiment of the encoded majority vote instruction that includes an opcode and a sub-opcode field describing the type of operation, but doesn’t explicitly state that the sub-opcode field identifies performing a vector horizontal majority vote operation. Seal disclosed using a sub-opcode within a logical instruction to select between various logical functions. The combination implements the encoding of Seal within the encoding of the majority vote instruction, which allows for a sub-opcode value to select performing a logical majority vote operation amongst a plurality of different sub-opcode logical operations.).
The advantage of using sub-opcode values within instruction encoding is that it allows for expanding the number of distinct operations a processor can perform while preserving the number of opcodes being used by the set of instructions. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the sub-opcodes of Seal within the instruction encoding of Ould-Ahmed-Vall for the above advantage.
As per claim 2:
Ould-Ahmed-Vall and Seal disclosed the computer program product of claim 1, wherein the set of bits includes one bit (Ould-Ahmed-Vall: Figures 3G-H, 14A-B, and 15-16 elements 1425, 1470-1485, 1560, and 1660, paragraphs 85, 91-92, 96, 138-139, and 142-149)(The vector horizontal majority voting instruction indicates a source register (i.e. source location) in the instruction encoding. Executing the operation reduces a plurality of selected bits/data elements to a single bit within the destination register.).
As per claim 3:
Ould-Ahmed-Vall and Seal disclosed the computer program product of claim 1, wherein the operation is a logical operation applied horizontally across the field proceeding one bit at a time, and wherein the result is one bit resulting from applying the logical operation to the plurality of bits of the field (Ould-Ahmed-Vall: Figures 3G-H, 14A-B, and 15 elements 1425, 1470-1485, 1560, and 1580, paragraphs 85, 91-92, 96, 138-139, and 142-147)(The vector horizontal majority voting instruction indicates a source register (i.e. source location) in the instruction encoding. Executing the operation reduces a plurality of selected bits/data elements to a single bit within the destination register. Executing the operation can be performed iteratively for a given bit of the source register in an embodiment.).
As per claim 6:
Ould-Ahmed-Vall and Seal disclosed the computer program product of claim 1, wherein the source location is a register, and the target location is another register (Ould-Ahmed-Vall: Figures 3G-H, paragraph 91).
As per claim 7:
Ould-Ahmed-Vall and Seal disclosed the computer program product of claim 1, wherein the source location is a vector register and the source operand is a vector including a plurality of fields (Ould-Ahmed-Vall: Figures 3G-H, paragraph 91).
As per claim 9:
Ould-Ahmed-Vall and Seal disclosed the computer program product of claim 1, wherein the source operand includes a plurality of fields of data to be reduced, and wherein the selecting, performing and placing are performed for each of the fields of the plurality of fields of data to be reduced (Ould-Ahmed-Vall: Figures 3G-H, 14A-B, and 15-16 elements 1425, 1470-1485, 1560, and 1660, paragraphs 85, 91-92, 96, 138-139, and 142-149)(The vector horizontal majority voting instruction indicates a source register in the instruction encoding. Executing the operation reduces a plurality of selected bits/data elements to a single bit within the destination register. The majority voting operation is performed on the entire source operand.).
As per claim 11:
Claim 11 essentially recites the same limitations of claim 1. Claim 11 additionally recites the following limitations:
a processor in communication with the memory (Ould-Ahmed-Vall: Figure 1A elements 102 and 120, paragraphs 58-60).
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 2. Therefore, claim 12 is rejected for the same reason(s) as claim 2.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 3. Therefore, claim 13 is rejected for the same reason(s) as claim 3.
As per claim 16:
Claim 16 essentially recites the same limitations of claim 1. Therefore, claim 16 is rejected for the same reasons as claim 1.
As per claim 17:
The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claim 2. Therefore, claim 17 is rejected for the same reason(s) as claim 2.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 3. Therefore, claim 18 is rejected for the same reason(s) as claim 3.
Claims 4-5, 8, 10, 14-15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall et al. (U.S. 2014/0289494), in view of Seal et al. (U.S. 2012/0131312), further in view of Official Notice.
As per claim 4:
Ould-Ahmed-Vall and Seal disclosed the computer program product of claim 1, wherein the operation is a logical AND operation, the logical AND operation being included in the plurality of operations included in the selected field (Seal: Figures 13-15, paragraphs 194 and 198-199)(Ould-Ahmed-Vall: Figures 14A-B elements 1403-1405 and 1470-1485, paragraphs 138-143)(The combination implements the encoding of Seal within the encoding of the majority vote instruction, which allows for a sub-opcode value to select performing a logical majority vote operation amongst a plurality of different sub-opcode logical operations. The combination allows for further sub-opcode values (e.g. AND) to be selected within the logical horizontal operations. Lastly, official notice is given that AND gates can be used to implement comparison functions for the advantage of reducing circuit gate costs. Thus, it would have been obvious to one of ordinary skill in the art to implement the comparison logic using AND gates.).
As per claim 5:
Ould-Ahmed-Vall and Seal disclosed the computer program product of claim 1, wherein the operation is selected from a group of operations consisting of a logical AND, a logical OR, a logical exclusive OR, a logical Not AND, a logical Not OR, and a logical Not exclusive OR, the selected field including the operations of the group of operations (Seal: Figures 13-15, paragraphs 194 and 198-199)(Ould-Ahmed-Vall: Figures 14A-B elements 1403-1405 and 1470-1485, paragraphs 138-143)(The combination implements the encoding of Seal within the encoding of the majority vote instruction, which allows for a sub-opcode value to select performing a logical majority vote operation amongst a plurality of different sub-opcode logical operations. The combination allows for further sub-opcode values (e.g. AND, OR, XOR) to be selected within the logical horizontal operations. Official notice is given that AND gates can be used, out of a group of AND, OR, NOT, and XOR gates, to implement comparison functions for the advantage of reducing circuit gate costs. Thus, it would have been obvious to one of ordinary skill in the art to implement the comparison logic using AND gates. Lastly, official notice is given that AND, OR, XOR operations can be inversed using a NOT gate for the advantage of reducing circuit gate costs. Thus, it would have been obvious to one of ordinary skill in the art to implement the comparison logic using NOT gates in conjunction with AND, OR, and XOR gates.).
As per claim 8:
Ould-Ahmed-Vall and Seal disclosed the computer program product of claim 1, wherein the instruction provides an indication of an offset, and wherein the placing the result in the target location includes using the offset to place the result in the target location (Ould-Ahmed-Vall: Figures 3G-H, paragraphs 91-92)(Ould-Ahmed-Vall disclosed the use of memory operands for the majority vote function. Official notice is given that memory operands can be implemented using base and offset addresses for the advantage of correctly placing data to the required memory address. Thus, it would have been obvious to one of ordinary skill in the art to implement destination memory operands in the majority vote function using base and offset addresses.).
As per claim 10:
Ould-Ahmed-Vall and Seal disclosed the computer program product of claim 1, wherein the instruction includes a source instruction field and an extension instruction field to be used to specify the source location (Ould-Ahmed-Vall: Figures 3G-H elements 374 and 391, paragraphs 91-92)(The prefix bytes (i.e. extension field) can be used to identify different size source operands.), a target instruction field to be used to specify the target location (Ould-Ahmed-Vall: Figures 3G-H elements 374, paragraphs 91-92), a mask field to be used to specify a size of the field of the source operand (Ould-Ahmed-Vall: Figures 3G-H, paragraphs 91-92 and 96)(The instructions include a mask field/element.), the selected field to be used to specify the operation to be performed (Seal: Figures 13-15, paragraphs 194 and 198-199)(Ould-Ahmed-Vall: Figures 3G-H elements 397-398, paragraphs 91-926)(The combination implements the encoding of Seal within the encoding of the majority vote instruction, which allows for a sub-opcode value to select performing a logical horizontal operation amongst a plurality of different sub-opcode logical operations.), and an offset instruction field to be used to specify an offset into the target location (Ould-Ahmed-Vall: Figures 3G-H, paragraphs 91-92)(Ould-Ahmed-Vall disclosed the use of memory operands for the majority vote function. Official notice is given that memory operands can be implemented using base and offset addresses for the advantage of correctly placing data to the required memory address. Thus, it would have been obvious to one of ordinary skill in the art to implement destination memory operands in the majority vote function using base and offset addresses.).
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 8. Therefore, claim 14 is rejected for the same reason(s) as claim 8.
As per claim 15:
The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claim 10. Therefore, claim 15 is rejected for the same reason(s) as claim 10.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 8. Therefore, claim 19 is rejected for the same reason(s) as claim 8.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 10. Therefore, claim 20 is rejected for the same reason(s) as claim 10.
Response to Arguments
The arguments presented by Applicant in the response, received on 4/6/2026 are considered persuasive.
Applicant argues regarding claims 1, 11, and 16:
“Applicant respectfully submits that one or more aspects of applicant's claimed invention is patentable over Ould-Ahmed-Vall, alone or in combination with the Official Notice. For example, applicant respectfully submits that it appears that Ould-Ahmed-Vall, alone or in combination with the Official Notice, fails to describe, teach or suggest, at the very least, one or more of applicant's claimed aspects of "performing an operation on the plurality of bits of the field to obtain a result, the result reducing the plurality of bits to a set of bits, the set of bits comprising one or more bits and having fewer bits than the plurality of bits, the operation specified using a selected field of the instruction separate from one or more fields of the instruction specifying the operation code, and wherein the operation is one operation of a plurality of operations specified using the selected field of the instruction," as recited in independent claim 1.
Although Ould-Ahmed-Vall mentions "instructions to provide vector horizontal majority voting" (paragraph 96), applicant respectfully submits that it appears that, at least, one or more of the following claimed aspects "the operation specified using a selected field of the instruction separate from one or more fields of the instruction specifying the operation code, and wherein the operation is one operation of a plurality of operations specified using the selected field of the instruction" is not described, taught or suggested by Ould-Ahmed-Vall, alone or in combination with the Official Notice. There does not appear to be a description, teaching or suggestion of a "reduce instruction" in which "the executing the instruction" includes "performing an operation on the plurality of bits of the field to obtain a result, the result reducing the plurality of bits to a set of bits, the set of bits comprising one or more bits and having fewer bits than the plurality of bits, the operation specified using a selected field of the instruction separate from one or more fields of the instruction specifying the operation code, and wherein the operation is one operation of a plurality of operations specified using the selected field of the instruction." For at least the above reasons, applicant respectfully submits that independent claim 1 is patentable, and respectfully requests an indication of allowance for independent claim 1.”
This argument is found to be persuasive for the following reason. The examiner agrees that Ould-Ahmed-Vall failed to teach the newly claimed limitation. However, a new ground of rejection has been given due to amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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