DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This communication is responsive to application filed on 11/29/2022.
Claims 1-9 are presented for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on 04/27/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/29/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is NOT invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use the word “means” or “step” or a term used as a substitute for “means” that is a generic placeholder but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitations are: a part condition acquisition step, a part arrangement order acquisition step, a boundary line acquisition step, a part arrangement step, a boundary line updating step, a first repetition step, a part type change step, a second repetition step, a provisional arrangement step, in claims 1-9.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 (Does this claim fall within at least one statutory category?):
Claims 1-8 are directed to a method.
Therefore, claims 1-8 fall into at least one of the four statutory categories.
Step 2A, Prong 1: ((a) identify the specific limitation(s) in the claim that recites an abstract idea: and (b) determine whether the identified limitation(s) falls within at least one of the groups of abstract ideas enumerates in MPEP 2106.04(a)(2)):
Claim 1:
A method for automatically arranging parts on a CAD for automatically arranging a plurality of types of parts in an arrangement area on a CAD tool (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity), two directions perpendicular to each other in the arrangement area being an X-direction and a Y- direction, and the plurality of types of parts being each a rectangle having a side parallel to the X-direction or the Y-direction, the method comprising:
a part condition acquisition step for acquiring a part boundary condition, which is set for each of the types of the parts, representing the type of the part to be permitted to be arranged adjacent to the part [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)];
a part arrangement order acquisition step for acquiring an arrangement order, which is set for each of the types of the parts, of the part in the arrangement area [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)];
a boundary line acquisition step for arranging a boundary line parallel to an area termination end line as a line representing a termination end of the arrangement area in the X-direction or the Y-direction and acquiring a boundary line boundary condition representing the parts arranged in two regions separated by the boundary line [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)];
a part arrangement step for comparing the part boundary condition set for the part and the boundary line boundary condition set for the boundary line arranged in the arrangement area and arranging the part when the conditions match each other [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)];
a boundary line updating step for updating the boundary line and the boundary line boundary condition after arranging the part in the part arrangement step [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)];
a first repetition step for repeatedly performing the part arrangement step and the boundary line updating step [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)];
a part type change step for changing, when the part boundary condition and the boundary line cannot match each other, the type of the part to be arranged to the part to be arranged next in order [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)]; and
a second repetition step for repeatedly performing the part arrangement step, the boundary line updating step, the first repetition step, and the part type change step according to the arrangement order [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)].
Step 2A, Prong 2 (1. Identifying whether there are any additional elements recited in the claim beyond the judicial exception; and 2. Evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application): The claim is directed to the judicial exception.
Claim 1 recites additional element of “CAD tool”. This additional element recited at a high level of generality (e.g. a generic computer element for performing a generic computer functions) such that it amounts to no more than mere application of the judicial exception using generic computer component(s). Accordingly, the additional element(s) of each of these claims do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Further, claims recite the term “automatically” implies that a generic function that may be utilize to perform the arrangement of the parts.
Step 2B: (Does the claim recite additional elements that amount to significantly more than the judicial exception? No): As discussed above with respect to the integration of the abstract into a practical application, the additional element of “CAD tool” is well-understood, routine, and conventional. Further, the additional term of “automatically arranging” may considered to be well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity).
[Claim 2] The method for automatically arranging parts on a CAD according to claim 1, further comprising a provisional arrangement step for updating the boundary line assuming [ “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)] that the part has been arranged before performing the method for automatically arranging parts on a CAD (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity) according to claim 1, wherein the provisional arrangement step includes a step of performing provisional arrangement by updating the boundary line assuming that the part has been arranged [ “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)] according to the method for automatically arranging parts on a CAD (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity) according to claim 1, and a step of calculating dimensions of a gap region where the provisional arrangement has not been performed from the boundary line after the provisional arrangement and adjusting dimensions of the part such that the gap region is eliminated [mathematical concepts].
[Claim 3] The method for automatically arranging parts on a CAD (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity)according to claim 1, wherein the part boundary condition includes a first boundary condition representing the type of the part to be permitted to be arranged adjacent to each of sides of the part, a second boundary condition representing the type of the part to be permitted to be arranged diagonally adjacent to each of corners of the part, and a rotation condition representing a rotational angle to be permitted when the part is arranged, and the boundary line boundary condition includes a third boundary condition representing presence or absence and the type of the parts arranged in two regions separated by the boundary line or indicating that the two regions are outside of an arrangement area of the part [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)].
[Claim 4] The method for automatically arranging parts on a CAD (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity) according to claim 3, further comprising in the part arrangement step, comparing the first boundary condition and the second boundary condition for the part with the third boundary condition for the boundary line, and arranging, when the first boundary condition for two sides of the part and the third boundary condition for the two boundary lines match each other, the part to contact the two boundary lines that match each other or arranging, when the second boundary condition for the part and the third boundary condition for the two boundary lines match each other, the part to contact a vertex formed by the two boundary lines that match the corner of the part, and in the boundary line updating step, deleting the boundary line that overlaps the side of the arranged part and setting, on the side of the part that does not overlap the boundary line, the new boundary line and the third boundary condition [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)].
[Claim 5] The method for automatically arranging parts on a CAD (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity) according to claim 1, wherein a plurality of blocks each having the parts arranged therein according to the method for automatically arranging parts on a CAD according to claim 1 are arranged in at least one of an X-direction and a Y-direction, or the plurality of blocks are arranged to overlap one another in a direction perpendicular to the X-direction and the Y-direction [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)].
[Claim 6] The method for automatically arranging parts on a CAD (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity) according to claim 1, wherein the arrangement area has a polygonal shape [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)].
[Claim 7] The method for automatically arranging parts on a CAD (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity) according to claim 6, wherein the polygonal shape is defined by the boundary line during or after completion of arrangement of the part [mathematical concepts and/or “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion)].
[Claim 8] The method for automatically arranging parts on a CAD (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity) according to claim 1, wherein the part boundary condition is automatically set from arrangement data of the part created in the past (well-understood, routine and conventional activity (MPEP 2144.04 (III) – automation of a known process or manual activity).
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 9 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim recites “a program” to perform the recited steps. The claim does not fall within at least one of the four categories of patent eligible subject matter because the claimed “a program” is not limited to a statutory subject matter.
In addition, independent claim 9 recites limitations analogous in scope to those of independent claim 1. Therefore, similar analysis to claim 1 is applied to claim 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2017/0161424 A1 issued to TSAI et al in view of US Publication No. 2007/0174807 A1 issued to Kumashiro et al.
[Claim 1] TSAI et al discloses a method for automatically arranging parts on a CAD for automatically arranging a plurality of types of parts in an arrangement area on a CAD tool, two directions perpendicular to each other in the arrangement area being an X-direction and a Y- direction, and the plurality of types of parts being each a rectangle having a side parallel to the X-direction or the Y-direction, the method comprising:
a part condition acquisition step for acquiring a part boundary condition, which is set for each of the types of the parts, representing the type of the part to be permitted to be arranged adjacent to the part (See: Abstract, designing a semiconductor device includes establishing boundary conditions for a layout of each cell of a plurality of cells, wherein each cell has a plurality of features, and boundary conditions are established based on a proximity of each feature to a cell boundary of a corresponding cell. The method includes determining whether the layout of each cell is colorable based on a number of masks used to manufacture a layer of the semiconductor device, a minimum spacing requirement for the plurality of features, and the established boundary conditions. The method includes forming a layout of the layer of the semiconductor device by abutting a first cell of the plurality of cells with a second cell of the plurality of cells. The method includes reporting the layout of the layer of the semiconductor device as colorable without analyzing the layout of the layer of the semiconductor device; [0021] In some embodiments, multiple cells are designed in operation 110. In some embodiments, each cell designed in operation 110 has a different function);
a boundary line acquisition step for arranging a boundary line parallel to an area termination end line as a line representing a termination end of the arrangement area in the X-direction or the Y-direction and acquiring a boundary line boundary condition representing the parts arranged in two regions separated by the boundary line (See: par [0024] In operation 120a, boundary conditions are introduced based on a risk of a feature near a boundary of the cell being located within a G0 spacing of features in an abutting cell following design of the layer of the semiconductor device. A sensitivity region is defined within the cell based on G0 spacing of a process used to form the layer of the semiconductor device. The sensitivity region is used to define a risk factor for features which contact or overlap the sensitivity region. In some embodiments, the risk factors are determined based on an amount of overlap between the feature and the sensitivity region; [0032] The sensitivity region extends around an entirety of the cell adjacent to the cell boundary. In some embodiments, a width of the sensitivity region is constant around the periphery of the cell. In some embodiments, a width of the sensitivity region varies within the cell based on a concentration of features within the cell or a manufacturing process used for forming the layer of the semiconductor device);
a part arrangement step for comparing the part boundary condition set for the part and the boundary line boundary condition set for the boundary line arranged in the arrangement area and arranging the part when the conditions match each other (See: [0024] In operation 120a, boundary conditions are introduced based on a risk of a feature near a boundary of the cell being located within a G0 spacing of features in an abutting cell following design of the layer of the semiconductor device. A sensitivity region is defined within the cell based on G0 spacing of a process used to form the layer of the semiconductor device. The sensitivity region is used to define a risk factor for features which contact or overlap the sensitivity region. In some embodiments, the risk factors are determined based on an amount of overlap between the feature and the sensitivity region; [0032] The sensitivity region extends around an entirety of the cell adjacent to the cell boundary. In some embodiments, a width of the sensitivity region is constant around the periphery of the cell. In some embodiments, a width of the sensitivity region varies within the cell based on a concentration of features within the cell or a manufacturing process used for forming the layer of the semiconductor device; [0033] The sensitivity region acts as a reference point for determining the risk factors. For example, a feature which does not contact or overlap with the sensitivity region has a risk factor of zero in some embodiments. A feature which contacts an edge of the sensitivity region, but does not overlap the sensitivity region has a risk factor of one in some embodiments. Features which overlap with the sensitivity region have a risk factor ranging from two to n, where n is the number of masks used to form the layer of the semiconductor device);
a boundary line updating step for updating the boundary line and the boundary line boundary condition after arranging the part in the part arrangement step (See: [0024] In operation 120a, boundary conditions are introduced based on a risk of a feature near a boundary of the cell being located within a G0 spacing of features in an abutting cell following design of the layer of the semiconductor device. A sensitivity region is defined within the cell based on G0 spacing of a process used to form the layer of the semiconductor device. The sensitivity region is used to define a risk factor for features which contact or overlap the sensitivity region. In some embodiments, the risk factors are determined based on an amount of overlap between the feature and the sensitivity region; [0025] In operation 120b, the n-patterning conflict analysis is performed on the cell which includes the boundary conditions. The n-patterning conflict analysis is used to reduce the risk that the features which overlap the sensitivity region in the cell will be within a G0 spacing of features in an abutting cell following formation of the layer of the semiconductor device; [0026] If operation 120b determines that the cell is not n-colorable, method 100 returns to operation 110 and the cell is modified. In some embodiments, the cell is modified based on instructions from the designer. In some embodiments, the cell is modified to change a location of at least one feature in the cell relative to a cell boundary. In some embodiments, the cell is modified to change a location of at least one feature in the cell relative to another feature in the cell);
a first repetition step for repeatedly performing the part arrangement step and the boundary line updating step (See: [0026] If operation 120b determines that the cell is not n-colorable, method 100 returns to operation 110 and the cell is modified. In some embodiments, the cell is modified based on instructions from the designer. In some embodiments, the cell is modified to change a location of at least one feature in the cell relative to a cell boundary. In some embodiments, the cell is modified to change a location of at least one feature in the cell relative to another feature in the cell);
a part type change step for changing, when the part boundary condition and the boundary line cannot match each other, the type of the part to be arranged to the part to be arranged next in order (See: [0026] If operation 120b determines that the cell is not n-colorable, method 100 returns to operation 110 and the cell is modified. In some embodiments, the cell is modified based on instructions from the designer. In some embodiments, the cell is modified to change a location of at least one feature in the cell relative to a cell boundary. In some embodiments, the cell is modified to change a location of at least one feature in the cell relative to another feature in the cell); and
a second repetition step for repeatedly performing the part arrangement step, the boundary line updating step, the first repetition step, and the part type change step according to the arrangement order (See: [0026] If operation 120b determines that the cell is not n-colorable, method 100 returns to operation 110 and the cell is modified. In some embodiments, the cell is modified based on instructions from the designer. In some embodiments, the cell is modified to change a location of at least one feature in the cell relative to a cell boundary. In some embodiments, the cell is modified to change a location of at least one feature in the cell relative to another feature in the cell; [0027] If operation 120b determines that the cell is n-colorable, method 100 proceeds to operation 130).
TSAI et al does not specify but Kumashiro et al discloses a part arrangement order acquisition step for acquiring an arrangement order, which is set for each of the types of the parts, of the part in the arrangement area (See: Abstract, the OPC is applied only to the cell boundary portions after respective OPC-applied cells are arranged on the chip, so that a dimensional precision in vicinity of the cell boundaries can be ensured; [0023] According to this method, since the same block can be completed by one process a cell by dividing the layout data into cells in the OPC processing step and then applying the OPC to each cell, a processing time can be greatly reduced. Also, if the OPC is applied only to the block boundary portions after respective OPC-applied blocks are arranged on the chip, a dimensional precision such as a gate dimension in vicinity of the block boundary, or the like can be ensured; [0081] In the above embodiment 1, the frequently occurring boundary portions in the combination of the neighboring cell arrangements are selected).
It would have been obvious before the effective filing date to combine semiconductor device manufacturing as taught by Kumashiro et al to designing a semiconductor device method of TSAI et al would be to reduce influences of the optical proximity effect in a semiconductor device (Kumashiro et al, par [0002]).
[Claim 2] Kumashiro et al discloses the method for automatically arranging parts on a CAD according to claim 1, further comprising a provisional arrangement step for updating the boundary line assuming that the part has been arranged before performing the method for automatically arranging parts on a CAD according to claim 1, wherein the provisional arrangement step includes a step of performing provisional arrangement by updating the boundary line assuming that the part has been arranged according to the method for automatically arranging parts on a CAD according to claim 1, and a step of calculating dimensions of a gap region where the provisional arrangement has not been performed from the boundary line after the provisional arrangement and adjusting dimensions of the part such that the gap region is eliminated (See: [0088] Therefore, in step 5004, a dimensional shrinkage is applied simply to the patterns whose cell boundary portions are thickened after the cells that underwent the OPC process in step 5003 are arranged in a chip. As a result, the high-speed process can be attained by simplifying the process while keeping the precision; [0089] In this manner, the after-OPC pattern in the cell boundary area becomes thicker than the optimal solution when the correction is applied on a single-cell basis. Therefore, the corrected shape that is close to the optimal solution can be calculated in a short TAT by causing the after-OPC pattern to shrink simply after the arrangement).
[Claim 3] TSAI et al discloses the method for automatically arranging parts on a CAD according to claim 1, wherein the part boundary condition includes a first boundary condition representing the type of the part to be permitted to be arranged adjacent to each of sides of the part, a second boundary condition representing the type of the part to be permitted to be arranged diagonally adjacent to each of corners of the part, and a rotation condition representing a rotational angle to be permitted when the part is arranged, and the boundary line boundary condition includes a third boundary condition representing presence or absence and the type of the parts arranged in two regions separated by the boundary line or indicating that the two regions are outside of an arrangement area of the part. (See: Abstract, designing a semiconductor device includes establishing boundary conditions for a layout of each cell of a plurality of cells, wherein each cell has a plurality of features, and boundary conditions are established based on a proximity of each feature to a cell boundary of a corresponding cell. The method includes determining whether the layout of each cell is colorable based on a number of masks used to manufacture a layer of the semiconductor device, a minimum spacing requirement for the plurality of features, and the established boundary conditions. The method includes forming a layout of the layer of the semiconductor device by abutting a first cell of the plurality of cells with a second cell of the plurality of cells. The method includes reporting the layout of the layer of the semiconductor device as colorable without analyzing the layout of the layer of the semiconductor device; [0032] The sensitivity region extends around an entirety of the cell adjacent to the cell boundary. In some embodiments, a width of the sensitivity region is constant around the periphery of the cell. In some embodiments, a width of the sensitivity region varies within the cell based on a concentration of features within the cell or a manufacturing process used for forming the layer of the semiconductor device; [0080] designing a semiconductor device. The method includes establishing boundary conditions for a layout of each cell of a plurality of cells, wherein each cell of the plurality of cells has a plurality of features, and establishing boundary conditions for the layout of each cell of the plurality of cells is based on a proximity of each feature of the plurality of features to a cell boundary of a corresponding cell of the plurality of cells. The method further includes determining whether the layout of each cell of the plurality of cells is colorable based on a number of masks used to manufacture a layer of the semiconductor device, a minimum spacing requirement for the plurality of features, and the established boundary conditions. The method further includes forming a layout of the layer of the semiconductor device by abutting a first cell of the plurality of cells with a second cell of the plurality of cells. The method further includes reporting the layout of the layer of the semiconductor device as colorable without analyzing the layout of the layer of the semiconductor device).
[Claim 4] TSAI et al discloses the method for automatically arranging parts on a CAD according to claim 3, further comprising in the part arrangement step, deleting the boundary line that overlaps the side of the arranged part and setting, on the side of the part that does not overlap the boundary line, the new boundary line and the third boundary condition (See: [0024] In operation 120a, boundary conditions are introduced based on a risk of a feature near a boundary of the cell being located within a G0 spacing of features in an abutting cell following design of the layer of the semiconductor device. A sensitivity region is defined within the cell based on G0 spacing of a process used to form the layer of the semiconductor device. The sensitivity region is used to define a risk factor for features which contact or overlap the sensitivity region. In some embodiments, the risk factors are determined based on an amount of overlap between the feature and the sensitivity region; [0025] In operation 120b, the n-patterning conflict analysis is performed on the cell which includes the boundary conditions. The n-patterning conflict analysis is used to reduce the risk that the features which overlap the sensitivity region in the cell will be within a G0 spacing of features in an abutting cell following formation of the layer of the semiconductor device; [0034] The risk factor for features which overlap the sensitivity region is determined based on an amount of overlap. In some embodiments, thresholds for determining the risk factor are evenly distributed within the sensitivity region. In some embodiments, thresholds for determining the risk factor are non-uniformly distributed within the sensitivity region. For example, in a triple patterning process, i.e., n=3, the threshold between a risk factor of two and a risk factor of three is a center line of the sensitivity region in some embodiments. In some embodiments, the threshold between the risk factor of two and the risk factor of three is displaced from the center line of the sensitivity region. Factors to be considered for placement of the thresholds for determining the risk factor for each of the overlapping features include the G0 spacing, the concentration of features within the cell and an overall size of the semiconductor device. As the G0 spacing increases, the threshold for the risk factor moves farther from the cell boundary, in some embodiments. As the concentration of features within the cell increases, the threshold for the risk factors moves farther from the cell boundary, in some embodiments. As the overall size of the semiconductor device increases, the threshold for the risk factors moves closer to the cell boundary, in some embodiments).
TSAI et al does not specify but Kumashiro et al discloses comparing the first boundary condition and the second boundary condition for the part with the third boundary condition for the boundary line (See: par [0093] The lithography verification processing portion 8 does the simulation of the cells selected by the verification selecting portion 7 by using the output data of the OPC processing portion 3, and then compares the simulation result with the corresponding layout data to verify whether or not a difference between them is less than a predetermined value. Also, the boundary area lithography verification processing portion 9 does the simulation of the cells selected by the verification selecting portion 7 by using the output data of the boundary area OPC processing portion 6, and then compares the simulation result with the corresponding layout data to verify whether or not a difference between them is less than a predetermined value), and arranging, when the first boundary condition for two sides of the part and the third boundary condition for the two boundary lines match each other (See: Fig. 1 OPC layout), the part to contact the two boundary lines that match each other or arranging, when the second boundary condition for the part and the third boundary condition for the two boundary lines match each other (See: Fig. 1 OPC layout), the part to contact a vertex formed by the two boundary lines that match the corner of the part, and in the boundary line updating step (See: Fig. 1 OPC layout).
It would have been obvious before the effective filing date to combine semiconductor device manufacturing as taught by Kumashiro et al to designing a semiconductor device method of TSAI et al would be to reduce influences of the optical proximity effect in a semiconductor device (Kumashiro et al, par [0002]).
[Claim 5] Kumashiro et al discloses the method for automatically arranging parts on a CAD according to claim 1, wherein a plurality of blocks each having the parts arranged therein according to the method for automatically arranging parts on a CAD according to claim 1 are arranged in at least one of an X-direction and a Y-direction, or the plurality of blocks are arranged to overlap one another in a direction perpendicular to the X-direction and the Y-direction (See: Abstract, to provide a semiconductor device manufacturing method of making a pattern formation possible with high precision at a high speed, the same block can be completed by one process a cell by dividing the layout data into cells in the OPC processing step and then applying the OPC to each cell, and the OPC is applied only to the cell boundary portions after respective OPC-applied cells are arranged on the chip, so that a dimensional precision in vicinity of the cell boundaries can be ensured. Also, since the patterns on the cell boundary portions are caused to shrink uniformly, the OPC of the cell boundary portions can be simplified and thus the fast process can be applied; Fig. 1 OPC layout and corresponding texts).
[Claim 6] TSAI et al discloses the method for automatically arranging parts on a CAD according to claim 1, wherein the arrangement area has a polygonal shape (See: 0051] Features 330 represent elements within standard cell 300 for implementing a function of the standard cell. Features 330 are depicted a rectangular shapes for simplicity. In some embodiments, features 330 include non-rectangular shapes, e.g, oval shapes, polygonal shapes, curvilinear shapes, free form shapes or other suitable shapes. In some embodiments, features 330 include interconnect structures, contact structures, gate structures, or other suitable structures).
[Claim 7] TSAI et al discloses the method for automatically arranging parts on a CAD according to claim 6, wherein the polygonal shape is defined by the boundary line during or after completion of arrangement of the part (See: 0051] Features 330 represent elements within standard cell 300 for implementing a function of the standard cell. Features 330 are depicted a rectangular shapes for simplicity. In some embodiments, features 330 include non-rectangular shapes, e.g, oval shapes, polygonal shapes, curvilinear shapes, free form shapes or other suitable shapes. In some embodiments, features 330 include interconnect structures, contact structures, gate structures, or other suitable structures).
[Claim 8] TSAI et al discloses the method for automatically arranging parts on a CAD according to claim 1, wherein the part boundary condition is automatically set from arrangement data of the part created in the past (See: [0021] In some embodiments, multiple cells are designed in operation 110. In some embodiments, each cell designed in operation 110 has a different function. In some embodiments, at least one cell designed in operation 110 has a same function as at least one other cell designed in operation 110, but has a different layout. In some embodiments, the designed cell is stored in a cell library for later use by a designer; [0022] In some embodiments, previously designed cells are imported into method 100 in operation 110. In some embodiments, the previously designed cells are imported from a cell library. In some embodiments, the cell libraries are designed for different manufacturing processes which have different G0 spacings between features of a cell).
As per Claim 9: The instant claim recites substantially same limitation as the above rejected claim 1, and therefore rejected under the same rationale.
Conclusion
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KIBROM K. GEBRESILASSIE
Primary Examiner
Art Unit 2189
/KIBROM K GEBRESILASSIE/Primary Examiner, Art Unit 2189 04/07/2026
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