Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 2018/0269229 A1 – hereinafter Or-Bach) in view of Tang et al. (“Ultrashort Channel Silicon Nanowire Transistors with Nickel Silicide Source/Drain Contacts” – hereinafter Tang) and further in view of Diorio et al. (US 2003/0206437 A1 – hereinafter Diorio).
In regards to claim 1, Or-Bach teaches A device comprising:
a lower device formed on a substrate; (Fig. 1a, 1b, and 2 teaches element 110 which is a substrate and para. [0003-0004] teaches 3D stacking of semiconductor devices or chips and para. [0009-0011] teaches stacking devices on the substrate wherein it cites “a multilevel semiconductor device, comprising: a first level comprising a first array of first memory cells; a second level comprising a second array of second memory cells, said first level is overlaid by said second level, wherein at least one of said first memory cells comprises a vertically oriented first transistor, and wherein at least one of said second memory cells comprises a vertically oriented second transistor, …”. Also see para. [0087] which cites “FIG. 3A illustrates the starting material structure for these vertically oriented 3D memories. On top of a substrate such as Si, Ge, SiGe, SOI, strained layered substrate, or substrate with buried cut layer, are deposited interchanging layers of designated source/drain (S/D) material 302 and designated channel material 304 layer in between.”)
an interlayer insulating layer formed on the substrate to cover the lower device; (Or-Bach fig. 33A teaches interlayer oxide layer; 11a shows an interlayer oxide (11001)between NPN stack pillar on the substrate, also see figures 28 that shows an interlayer oxide between layers. Also see para. [0066] that cites “The alternating-porosity multilayer can be converted later into alternating multilayer of monocrystalline-Si over insulating SiO2 ,…” and para [0072] teaches valleys filled with isolation oxide. )
a synapse device having a Schottky barrier transistor structure and formed on the interlayer insulating layer, (Or-Bach Figures 33A-33D shows the inter layer oxide (interlayer insulating layer) with devices formed on it (NPN stack, ONO gate stack), and para. [0358] teaches using the 3D NOR fabric floating body memory structure for a synapse type circuit. Also see figs. 8a-8e); and
a vertical connection wiring formed in the interlayer insulating layer to electrically connect the lower device and the synapse upper device. (Para. [0041] and fig. 28 teaches a side cut view of the 3D NOR structure with RRAM pillars, with interlayer oxide (interlayer insulating layer) between RRAM active region above and below it. Then figures 33A-33D shows NPN device layers (upper device) on top of the inter layer oxide (interlayer insulating layer) and lower device (figure 28) connected by the vertical conductor pillars (vertical connection wiring). Also, para. [0274-0275] cites “[0275] FIG. 32B illustrates an alternative in which multiple RRAM/OTP pillars 3202 may have programmable connection 3232 to a shared Y direction strip 3234 as part of the Y direction connection fabric 3230 constructed as part of the overlaying control circuits.” Which teaches the vertical wiring between the insulating layer connected the upper and lower devices.)
However, Or-Bach does not explicitly disclose a neuromorphic device comprising a device having a Schottky barrier transistor structure and formed on the interlayer insulating layer, the synapse device including a channel, a floating gate, a control gate, a source having a first Schottky junction with the channel, and a drain having a second Schottky junction with the channel.
Tang discloses a device having a Schottky barrier transistor structure, (Tang abstract states “At such channel lengths, high maximum on-currents of 890 (μA/μm) and a maximum transconductance of 430 (μS/μm) were obtained, which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs).” Also see figures 2a-c along with its accompanying text, fig. 3a-f along with accompanying text and the “Material Considerations in Nanochannel Silicidation” section discloses a the Schottky barrier transistor structure.) a source having a first Schottky junction with the channel, and a drain having a second Schottky junction with the channel (Tang page 3984 Conclusion first paragraph teaches Si nanowire SB-Fet when it cites “Multiple nickel silicide phases grow simultaneously with NiSi2 as the reaction front. The NiSi2/Si metal semiconductor contacts are type-a interfaces…”. Also see page 3981 left column first paragraph cites “Annealing of the sample was performed on an in situ TEM heating stage (Gatan 628 single tilt heating holder) at 425 °C, and the reaction was monitored in real time. Initially, nickel silicide formed at the source/drain Ni/Si contact and grew inward by transforming Si NWs. The remaining Si segment of the NW shrinks as the reaction proceeds. Figure 1a−g shows a series of TEM snapshots during the reaction process.”, this teaches that during silicadation, NiSi2 grows inward from both the Ni source and drain into the Si nanowires. This means there is NiSi2 segment connected to Si segment connected to NiSi2 segment along the nanowire, thus the source region is NiSi2 contacting one end of the Si channel forming a first NiSi2/Si Schottky junction (type-A interface) and the drain region is the other NiSi2 segment on the other side of the channel (Si segment) forming a second NiSi2/Si Schottky junction. Also see figure 4b and its corresponding text that teaches source and drain connected by the channel.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Or-Bach with that of Tang in order to allow for using a device having a Schottky barrier transistor structure as the both references teach a Schottky barrier transistor and the Tang reference gives details on the structure of the Schottky barrier transistor. It provides the benefit of better performance as discloses in the abstract of Tang wherein it states “At such channel lengths, high maximum on-currents of 890 (μA/μm) and a maximum transconductance of 430 (μS/μm) were obtained, which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs).”.
However, Or-Bach in view of Thang does not explicitly disclose a neuromorphic device comprising and the synapse device including a floating gate and a control gate.
Diorio discloses a neuromorphic device comprising and the synapse device including a floating gate and a control gate. (Diorio para. [0022] and figures 6-7 teaches a pFET synapse, which is a neuromorphic device. Figs. 7a-7c teaches a floating gate, control gate and tunnel. Also, para. [0062] teaches the present invention is a synapse transistor that can be used digital CMOS silicon circuits that learn autonomously and various forms of memory storage.)
It would have been obvious to one of ordinary skill in the art before the earlies effective filing date of the claimed invention to modify the teachings of the Or-Bach in view of Tang with that of Diorio in order to allow using a synapse transistors comprising a source, drain, floating gate, and control gate as both reference deal with using synapses and transistors. The benefit of doing so the synapse transistor of Diorio allows for autonomous learning as cited in para. [0062] of Diorio and para. [0061] of Diorio that states “Those of ordinary skill in the art will now realize that the devices described herein may be formed on a conventional semiconductor substrate or they may as easily be formed as a thin film transistor (TFT) above the substrate, or on an insulator (SOI) or on glass (SOG).” Thus, allowing the synapse transistors of Diorio to integrated into the semiconductor of Or-Bach.
In regards to claim 2, Or-Bach in view of Tang in view of Diorio disclose the neuromorphic device of claim 1, wherein the first Schottky junction comprises a metal silicide formed between a first side surface of the channel and a metal constituting the source through a low temperature process, wherein the second Schottky junction comprises a metal silicide formed between a second side surface of the channel and a metal constituting the drain through the low temperature process, and wherein the low temperature process is performed at less than 500 ℃. (Or-Back figures 8H-8L shows the protection of the channel, sidewall of the source and drain, the metal (Co, Ti, Ni,..) and annealed to metal silicide at the sidewalls. Also, para. [0148] teaches the silicide region may be in direct contract with the channel thus forming the Schottky barrier for the source and drain. Also, para. [0083] cites “The epitaxial process of multilayers of an n + type layer over a p type layer could be done at low temperatures such as below about 400° C . , 400 - 500° C . ,…”, this would be low temperature below 500° C.)
In regards to claim 3, Or-Bach in view of Tang in view of Diorio disclose the neuromorphic device of claim 1, wherein the source and drain each include a silicide of at least one selected from a group consisting of tungsten, titanium, cobalt, nickel, erbium, ytterbium, samarium, yttrium, gadolinium, terbium, cerium, platinum, and iridium. (Or-Bach fig. 8I teaches Co (cobalt), Ti (titanium), and Ni (nickel) as well as any other metals. This is also stated in para. [0151] where it states “FIG . 81 illustrates the structure after deposition of the silicide material 830 such as Co , Ti , Ni or other metals as desired .”.)
In regards to claim 4, Or-Bach in view of Tang in view of Diorio disclose the neuromorphic device of claim 1, wherein the channel of the synapse device includes silicon. (Or-Bach para. [0088-0089] cites “[0088] For example the composition of the S/D layers 302 could be N + silicon while the channel layers 304 could be P type silicon and the selective etch process would utilize anodic etching as detailed in U.S. Pat. No . 8,470,689 and as was described herein. [ 0089 ] An alternative is to use P + + silicon for the S/D layers 302 and N silicon for channel layers 304 and the later selective etch would utilize the NH OH solution as taught by Golod et al .”)
In regards to claim 5, Or-Back in view of Tang in view of Diorio disclose the neuromorphic device of claim 1, wherein the synapse device further includes a first insulating layer disposed between the channel and the floating gate and a second insulating layer disposed between the floating gate and the control gate, and at least one of the first and second insulating layers includes at least one selected from a group consisting of a silicon oxide, a silicon nitride, a silicon oxynitride, and a high-k material having a dielectric constant greater than 7.5. (Or-Bach para. [0100, 0105, 0130-0131 and 0147] teaches a dielectric multilayer of tunneling oxide layer, charge-trap layer such as silicon nitride, and blocking oxide forming the charge stack, thus it teaches an oxide-nitride-oxide stack which is a 3 layers gate dielectric over the channel region. Further para. [0130 teaches using high-k (wherein k is electric constant, and high means significantly greater than 3.9). Diorio para. [0066] teaches double poly process is used which provides a capacitively couples control, this along with figure 7 discloses a poly2 control grate, poly1 floating gate and interpoly dielectric. Tang page 3983 teaches second paragraph teaches a dielectric constant between 3.9 and 22, which covers greater than 7.5.)
In regards to claim 6, Or-Bach in view of Tang in view of Diorio disclose the neuromorphic device of claim 1, wherein the floating gate of the synapse device includes a polycrystalline silicon layer, an amorphous silicon layer, a metal oxide layer, a silicon nitride layer, a silicon nanocrystal layer, a metal nanocrystal layer, a silicon oxide nanocrystal layer, a metal oxide nanocrystal layer, or a combination thereof. (Diorio claim 7 cites “7. The device in accordance with claim 6, wherein said floating gate comprises polysilicon.”; Diorio claims 13-14 cite “13. The device in accordance with claim 12, wherein said floating gate comprises a layer of deposited n type amorphous silicon which has been recrystallized. 14. The device in accordance with claim 12, wherein said floating gate comprises a layer of deposited p type amorphous silicon which has been recrystallized.”; Diorio claim 80 cites “80. The floating gate device in accordance with claim 76, wherein said floating gate comprises metal.”; Diorio claim 81 cites “81. The floating gate device in accordance with claim 76, wherein said floating gate comprises polycrystalline silicon.”; Or-Bach para. [0100 and 0105] teaches silicon nitride charge-storage layer within the floating gate.)
In regards to claim 7, Or-Bach in view of Tang in view of Diorio disclose the neuromorphic device of claim 1, wherein the lower device includes a metal oxide semiconductor device. (Diorio para [0014] teaches the device is a p-channel MOSFET used for implementing the floating gate memory, and para. [0065 and 0067] teaches the synapse transistor is two MOSFETs, wherein MOSFET is metal-oxide-semiconductor field-effect transistor.)
In regards to claim 8, Or-Bach in view of Tang in view of Diorio disclose the neuromorphic device of claim 1, wherein the lower device includes a transistor device, the transistor device including a channel region, a source region, a drain region, a gate insulating layer, and a gate electrode, and the vertical connection wiring is configured to electrically interconnect the source of the synapse device and the source region of the transistor device. (Diorio fig. 7 shows a floating gates synapse transistor that is a MOSFET including a channel region between source and drain, a gate oxide (gate insulating layer), and a polysilicon gate/floating gate and control gate. Or-Back Para. [0041] and fig. 28 teaches a side cut view of the 3D NOR structure with RRAM pillars, with interlayer oxide (interlayer insulating layer) between RRAM active region above and below it. Then figures 33A-33D shows NPN device layers (upper device) on top of the inter layer oxide (interlayer insulating layer) and lower device (figure 28) connected by the vertical conductor pillars (vertical connection wiring).)
In regards to claim 9, Or-Bach in view of Tang in view of Diorio disclose the neuromorphic device of claim 1, wherein a footprint of the synapse device overlaps a footprint of the lower device. (Or-Back figures 3a-3h and 4a-4c shows a stack of NPN vertical transistors in the 3D Nor architecture, wherein each layer and devices as the same footprint, thus overlaps.)
In regards to claim 10, it is the method of claim 1 with similar limitations and thus rejected using the same reasoning found in claim 1.
In regards to claim 11, Or-Bach in view of Tang in view of Diorio disclose the method of fabricating a neuromorphic device of claim 10, wherein the forming of the synapse device includes: forming a metal layer bonded to first and second side surfaces of the channel; and forming the first and second Schottky junctions by performing a heat treatment process to change portions of the metal layer adjoining the first and second side surfaces of the channel into a metal silicide. (Or-Back figures 8H-8L shows the protection of the channel, sidewall of the source and drain, the metal (Co, Ti, Ni,..) and annealed to metal silicide at the sidewalls. Also, para. [0148] teaches the silicide region may be in direct contract with the channel thus forming the Schottky barrier for the source and drain. Also, para. [0083] cites “The epitaxial process of multilayers of an n + type layer over a p type layer could be done at low temperatures such as below about 400° C . , 400 - 500° C . ,…”, this would be low temperature below 500° C.)
In regards to claim 12, Or-Bach in view of Tang in view of Diorio disclose the method of fabricating a neuromorphic device of claim 11, wherein the forming of the synapse device includes: after forming the first and second Schottky junctions, removing a portion of the metal layer which has not been changed into the metal silicide. (Or-Back para. [0153] cites “FIG . 8K illustrates the structure after removal of unused silicidation metal and the protection oxide 821 exposing the channel regions 834 .”, which is would be metal not changed.)
In regards to claim 13, Or-Bach in view of Tang in view of Diorio disclose the method of fabricating a neuromorphic device of claim 11, wherein the heat treatment process is performed at a temperature of less than 500℃. (Or-Back para. [0083] cites “The epitaxial process of multilayers of an n + type layer over a p type layer could be done at low temperatures such as below about 400° C . , 400 - 500° C . ,…”, this would be low temperature below 500° C.)
In regards to claim 14, Or-Bach in view of Tang in view of Diorio disclose the method of fabricating a neuromorphic device of claim 11, wherein the heat treatment process is performed using rapid thermal annealing (RTA), furnace annealing, laser annealing, or a combination thereof. (Or-Back para. [0152] cites “FIG . 8J illustrates the structure after performing the silicidation, of the exposed S/D regions, by annealing the structure using techniques such optical heating using spike, flash or laser processes or alternatively microwave or heating oven.”)
In regards to claim 15, Or-Bach in view of Tang in view of Diorio disclose the method of fabricating a neuromorphic device having a three-dimensional stacked structure of claim 11, wherein the metal layer includes at least one selected from a group consisting of tungsten, titanium, cobalt, nickel, erbium, ytterbium, samarium, yttrium, gadolinium, terbium, cerium, platinum, and iridium. (Or-Bach figure 8I teaches metal used are Co (cobalt), Ti (titanium), and Ni (nickel) as well as any other metals.)
In regards to claim 16, Or-Bach in view of Tang in view of Diorio disclose the method of fabricating a neuromorphic device of claim 11, wherein, before the forming of the metal layer, the forming of the synapse device further includes: forming a channel material layer on the interlayer insulating layer;(Or-Bach forms channel material layer (P-type Si/SiGe, element 304 figure 3a) on interlayer insulating layer (oxide values 308/316/318 figs. 3f, 3e, 3b) via epi stack (NPN stack figure 3A). Fig. 3a shows alternating channel material 304 (p-type) prior to oxide/insulator base. Fig. 3B shows ridge etching element 307 wherein valleys are filled with oxide interlayer insulating (element 308). Or-Bach para. [0087] shows interchanging layers of source/drain material 302 and channel material 304 between them. ) forming a gate stack including the floating gate and the control gate on the channel material layer; (Fig. 3D, 3E and 4A and paragraph [0099-0100 and 0105] teaches ONO stack 312 (tunneling oxide/charge storage/control oxide = floating gate) on the channels 319 and 314 for control gate) and forming the channel from the channel material layer by etching portions of the channel material layer on first and second sides of the gate stack. Fig. 3E and 3F teaches a two step etching process, before forming metal layer in figure 8I).
In regards to claim 17, it is the method embodiment of claim 7 with similar limitations and thus rejected using the same reasoning found in claim 7.
In regards to claim 18, it is the method embodiment of claim 8 with similar limitations and thus rejected using the same reasoning found in claim 8.
In regards to claim 19, it is the method embodiment of claim 9 with similar limitations and thus rejected using the same reasoning found in claim 9.
Conclusion
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/PAULINHO E SMITH/ Primary Examiner, Art Unit 2127