DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/1/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 2016/0050769) in view of Appelt et al. (US 6,290,860).
Regarding claim 9, Yoshida teaches a component carrier (Figs. 1-3), comprising:
a dielectric layer structure (same as 3), covered by a metal foil (4);
an electroless metal layer (6) on the metal foil (as shown in Figs. 2-3); and
a multi-stage electroplating structure (7+9) on the electroless metal layer (as shown in Fig. 3);
wherein the multi-stage electroplating structure comprises a plating layer (7) followed by a pattern plating layer (same as 9 that becomes 10 in Fig. 3-2) formed by pattern plating (same as shown in Fig. 3);
wherein the plating layer serves as a bond enhancing layer for an interlayer connection (7 serves as bonding enhancing layer for 9/10).
Yoshida does not teach the plating layer is a flash plating layer formed by flash plating; and wherein a thickness of the flash plating layer is constant. However, Appelt teaches a flashing plating layer (28, Fig. 4) formed by flash plating followed by pattern plating (col. 5, ln. 66- col. 6, ln. 4: “…flash plating followed by pattern plating…”), and wherein a thickness of the flash plating layer is constant (thickness of 28 in Fig. 4 appears to be constant). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plating layer is a flash plating layer formed by flash plating; and wherein a thickness of the flash plating layer is constant in Yoshida, as taught by Appelt, in order to ensure a uniform and strong adhesion of the plating layer. Also note the limitation, the multi-stage electroplating structure is formed by flash plating followed by pattern plating, is considered a product-by-process claim. “[E]ven though product-by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 10, Yoshida in view of Appelt teaches the component carrier according to claim 9, and Yoshida further teaches wherein the dielectric layer structure (3), covered by the metal foil (4), is formed on only part of a base (1 and/or 2); and wherein the electroless metal layer (6) is formed partially on the metal foil (4) and partially on the base (as shown in Figs. 2-3).
Regarding claim 11, Yoshida in view of Appelt teaches the component carrier according to claim 9, and Yoshida further teaches wherein the dielectric layer structure and the metal foil are patterned to expose a base (1 and/or 2) by a via (via at 5) extending through the patterned dielectric layer structure and the patterned metal foil (as shown in Figs. 1-3).
Regarding claim 12, Yoshida in view of Appelt teaches the component carrier according to claim 11, and Yoshida further teaches wherein the via is at least partially filled by part of the electroless metal layer and by part of the multi-stage electroplating structure (filled by part of 6, 7, 9 as shown in Figs. 2, 3).
Regarding claim 13, Yoshida in view of Appelt teaches the component carrier according to claim 11, and Yoshida further teaches wherein the multi-stage electroplating structure has a larger thickness in the via compared to a smaller thickness above the dielectric layer structure (thickness of 7+9 is larger at 5 than above 3 as shown in Fig. 3).
Regarding claim 14, Yoshida in view of Appelt teaches the component carrier according to claim 10, and Yoshida further teaches wherein the base comprises a stack (1 and/or 2) comprising at least one electrically conductive layer structure (1) and/or at least one electrically insulating layer structure (2).
Regarding claim 15, Yoshida in view of Appelt teaches the component carrier according to claim 9, and Yoshida further teaches wherein the metal foil has a thickness of less than 5 μm (can be less than 5 μm, see [0031]).
Regarding claim 16, Yoshida in view of Appelt teaches the component carrier according to claim 9, and Yoshida further teaches wherein the electroless metal layer has a thickness of not more than 2 μm (preferably 0.5 to 1.0 μm, see [0038]).
Regarding claim 17, Yoshida in view of Appelt teaches the component carrier according to claim 9, and Yoshida further teaches wherein the multi-stage electroplating structure (7+9) has a maximum thickness of at least 10 μm (7+9 can be greater than 10 μm, see [0039, 0041]).
Regarding claim 18, Yoshida in view of Appelt teaches the component carrier according to claim 9, and Yoshida further teaches wherein a pattern plating structure (same as 9) of the multi-stage electroplating structure has a thickness of at least 5 times of a thickness of a flash plating structure (same as 7) of the multi-stage electroplating structure (thickness of 9 can be at least 5 times thickness of 7, see [0039, 0041]; for example when 7 has a thickness of 0.5 μm and 9 has a thickness of 10 μm).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Appelt, and further in view of Matsuura (US 10,763,002).
Regarding claim 19, Yoshida in view of Appelt teaches the component carrier according to claim 9, and Yoshida further teaches wherein the metal foil, the electroless metal layer and the multi-stage electroplating structure form an electrically conductive structure (structure shown in Fig. 3-2).
Yoshida does not explicitly teach form the electrically conductive structure with a line/space ratio of not more than 20 μm /20 μm. However, Matsuura teaches an electrically conductive structure with a line/space ratio of not more than 20 μm /20 μm (col. 1, ln. 57-col. 2, ln. 17: “…recently, it has been desired to form a wiring pattern with a highly miniaturized line/space (L/S) of as thin as (13 μm or less)”/(13 μm or less)…). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the electrically conductive structure with a line/space ratio of not more than 20 μm /20 μm in Yoshida in view of Appelt, as taught by Matsuura, in order to increase circuit density for devices with limited footprint.
Regarding claim 20, Yoshida in view of Appelt and Matsuura teaches the component carrier according to claim 19, and Yoshida further teaches comprising at least one of the following features: wherein the electrically conductive structure is a trace (same as 10); wherein the electrically conductive structure is free of an undercut (no undercut as shown in Fig. 3).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Appelt and Matsuura.
Regarding claim 21, Yoshida teaches a component carrier (Figs. 1-3), comprising:
a dielectric layer structure (same as 3) covered by a metal foil (4);
an electroless metal layer (6) on the metal foil (as shown in Figs. 2-3); and
a multi-stage electroplating structure (7+9) on the electroless metal layer (as shown in Fig. 3);
wherein the multi-stage electroplating structure comprises a plating layer (7) followed by a pattern plating layer (same as 9 that becomes 10 in Figs. 3-2) formed by pattern plating (same as shown in Fig. 3), wherein the plating layer serves as a bond enhancing layer for an interlayer connection (7 serves as a bonding enhancing layer for 9/10);
wherein an electrically conductive structure (structure shown in Fig. 3-2) formed by the combination of the metal foil, the electroless metal layer.
Yoshida does not teach the plating layer is a flash plating layer formed by flash plating. However, Appelt teaches a flashing plating layer (28, Fig. 4) formed by flash plating followed by pattern plating (col. 5, ln. 66- col. 6, ln. 4: “…flash plating followed by pattern plating…”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plating layer is a flash plating layer formed by flash plating in Yoshida, as taught by Appelt, in order to ensure a uniform and strong adhesion of the plating layer. Also note the limitation, the multi-stage electroplating structure is formed by flash plating followed by pattern plating, is considered a product-by-process claim. “[E]ven though product-by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Yoshida in view of Appelt does not teach the multi-stage electroplating structure is arranged in a line/space ratio of not more than 20 μm / 20 μm. However, Matsuura teaches an electrically conductive structure with a line/space ratio of not more than 20 μm /20 μm (col. 1, ln. 57-col. 2, ln. 17: “…recently, it has been desired to form a wiring pattern with a highly miniaturized line/space (L/S) of as thin as (13 μm or less)”/(13 μm or less)…). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the electrically conductive structure with a line/space ratio of not more than 20 μm /20 μm in Yoshida in view of Appelt, as taught by Matsuura, in order to increase circuit density for devices with limited footprint.
Response to Arguments
Applicant's arguments with respect to claims 9-21 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/JAMES WU/Primary Examiner, Art Unit 2841