DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
1. Claims 1-2, 8-9, and 15 are currently amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Response to Amendment
2. Regarding 35 U.S.C. 101 Rejections:
Applicant’s arguments with respect to 35 U.S.C. 101 rejections have been fully considered and are persuasive. The 35 U.S.C. 101 rejections have been withdrawn.
3. Regarding Prior Art Rejections:
The arguments regarding the rejections under 35 U.S.C. § 102(a) and 35 U.S.C. § 103 challenge certain limitations. These limitations are newly added and were therefore not addressed in the previous rejection; therefore, the arguments are moot. The amendments are newly addressed by the new grounds of rejection under 35 U.S.C. § 103.
Applicant’s arguments with respect to claim(s) 1, 8, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-5, 7-12, 14-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sato US 20190018776 A1 in view of Okamura et al. US 20200159918 A1.
6. With regard to claim 1, Sato teaches:
A method comprising:
detecting, at a first time and at a fast hang avoidance (FHA) controller, that an FHA condition for a resource request exceeds a first threshold for FHA activation on at least one FHA component in a first system scope of a plurality of system scopes, the first system scope including a first plurality of requestors ([0027] The crossbar unit (XB) 14 includes four queues (buffers) Q11, Q12, Q21, and Q22 each corresponding to a holding unit, arbitration units (selectors) 15 and 18, a deadlock controller 16, and a suppression unit 17. The requests REQF and REQN input to the crossbar unit (XB) 14 are stored in one of the queues (buffers) Q11, Q12, Q21, and Q22 based on reception destination (issuance destination) information in the requests. Each of the queues (buffers) Q11, Q12, Q21, and Q22 has a plurality of entries; [0032] When it is determined that the deadlock state occurs, the deadlock controller 16 performs shifting to the deadlock resolution mode and outputs a suppression signal QAS (value “1”) for suppressing an issuance of a new request from the own node from the ring bus. In addition, when the number of entries being used in the remote queue Q11 reaches the number of the usable entries, the deadlock controller 16 outputs a busy signal BSYO (value “1”) to another node of the previous stage; [0042] The comparison circuit 415 outputs “1” when the count value CNTC is equal to or larger than the threshold A [...]; [0044] That is, in the normal mode, the result of the comparison between the count value CNTC and the threshold A is output as the busy signal BSYO. In the deadlock resolution mode, the result of the comparison between the count value CNTC and the threshold B is output as the busy signal BSYO. Accordingly, in the normal mode, when the number of entries used in the remote queue Q11 reaches the threshold A, the transmission of a request from another node of the previous stage to the own node is suppressed. In addition, in the deadlock resolution mode, when the number of entries used in the remote queue Q11 reaches the threshold B, the transmission of a request from another node of the previous stage to the own node is suppressed.);
determining a first FHA request status for the resource request and the FHA controller based on activation settings for the FHA controller, a requestor type for the resource request, and the first system scope ([0027] The crossbar unit (XB) 14 includes four queues (buffers) Q11, Q12, Q21, and Q22 each corresponding to a holding unit, arbitration units (selectors) 15 and 18, a deadlock controller 16, and a suppression unit 17. The requests REQF and REQN input to the crossbar unit (XB) 14 are stored in one of the queues (buffers) Q11, Q12, Q21, and Q22 based on reception destination (issuance destination) information in the requests. Each of the queues (buffers) Q11, Q12, Q21, and Q22 has a plurality of entries; [0032] The deadlock controller 16 determines whether the deadlock state occurs, based on the busy signal BSYI input from another node of the next stage and the signals Q11W and Q11R output from the remote queue Q11. When it is determined that the deadlock state occurs, the deadlock controller 16 performs shifting to the deadlock resolution mode and outputs a suppression signal QAS (value “1”) for suppressing an issuance of a new request from the own node from the ring bus. In addition, when the number of entries being used in the remote queue Q11 reaches the number of the usable entries, the deadlock controller 16 outputs a busy signal BSYO (value “1”) to another node of the previous stage; [0033] According to the suppression signal QAS output from the deadlock controller 16, the suppression unit 17 controls the transmission of the request from the local queue Q12 to the arbitration unit 15. When the value of the suppression signal QAS is “1,” the suppression unit 17 suppresses the transmission of the request from the local queue Q12 to the arbitration unit 15, and suppresses the issuance of a new request to the ring bus.); and
activating, based on the first FHA request status, FHA mechanisms on the at least one FHA component within the first system scope ([0032] When it is determined that the deadlock state occurs, the deadlock controller 16 performs shifting to the deadlock resolution mode and outputs a suppression signal QAS (value “1”) for suppressing an issuance of a new request from the own node from the ring bus. In addition, when the number of entries being used in the remote queue Q11 reaches the number of the usable entries, the deadlock controller 16 outputs a busy signal BSYO (value “1”) to another node of the previous stage; [0042] The comparison circuit 415 outputs “1” when the count value CNTC is equal to or larger than the threshold A [...]; [0044] Accordingly, in the normal mode, when the number of entries used in the remote queue Q11 reaches the threshold A, the transmission of a request from another node of the previous stage to the own node is suppressed.);
detecting, at a second time, the FHA condition for the resource request exceeds a second threshold for FHA activation on a plurality of FHA components in a second system scope of the plurality of system scopes, wherein the second system scope includes the first plurality of requestors of the first system scope and at least one additional requestor ([0046] First, in operation S501, the deadlock controller 16 determines whether the deadlock state occurs. In the normal mode, when both the count values CNTA and CNTB of the counters 401 and 402 are larger than the threshold T, the deadlock controller 16 determines that the deadlock state occurs, and the operation proceeds to operation S502. That is, in the normal mode, when the busy signals BSYI and BSYO are continuously output for a longer time than the threshold T, the deadlock controller 16 determines that the remote queues Q11 of the own node and another node of the next stage are clogged, and thus, the deadlock state occurs; [0047] Next, in operation S502, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1,” and performs shifting to the deadlock resolution mode (entry extension mode). Subsequently, in operation S503, the deadlock controller 16 sets the suppression signal QAS to “1” so as to suppress the issuance of a new request from the own node to the ring bus, as a result of the change of the flag held by the flag holding circuit 409 to “1.”);
determining a second FHA request status for the resource request and the FHA controller based on the activation settings for the FHA controller and the second system scope ([0047] Next, in operation S502, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1,” and performs shifting to the deadlock resolution mode (entry extension mode). Subsequently, in operation S503, the deadlock controller 16 sets the suppression signal QAS to “1” so as to suppress the issuance of a new request from the own node to the ring bus, as a result of the change of the flag held by the flag holding circuit 409 to “1.”); and
activating, based on the second FHA request status, FHA mechanisms on the plurality of FHA components in the second system scope ([0047] Next, in operation S502, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1,” and performs shifting to the deadlock resolution mode (entry extension mode). Subsequently, in operation S503, the deadlock controller 16 sets the suppression signal QAS to “1” so as to suppress the issuance of a new request from the own node to the ring bus, as a result of the change of the flag held by the flag holding circuit 409 to “1.”).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
7. With regard to claim 2, Sato further teaches:
wherein activating the first FHA mechanisms on the at least one FHA component within the first system scope comprises blocking the first plurality of requestors from sending additional resource requests, and wherein activating the first FHA mechanisms on the plurality of FHA components in the second system scope comprises blocking the at least one additional requestor from sending additional resource request ([0044] Accordingly, in the normal mode, when the number of entries used in the remote queue Q11 reaches the threshold A, the transmission of a request from another node of the previous stage to the own node is suppressed. In addition, in the deadlock resolution mode, when the number of entries used in the remote queue Q11 reaches the threshold B, the transmission of a request from another node of the previous stage to the own node is suppressed.).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
8. With regard to claim 3, Sato further teaches:
wherein activating the FHA mechanisms on the at least one FHA component in the first system scope comprises:
transmitting an FHA request to the at least one FHA component in the first system scope ([0050] In operation S601, when the crossbar unit (XB) 14 of the node 10 receives a request which is not addressed to the own node, from another node of the previous stage, the crossbar unit (XB) 14 stores the received request in the remote queue Q11. At this time, the signal Q11W output from the remote queue Q11 becomes “1,” and the count value CNTC of the counter 411 of the deadlock controller 16 increases by 1; [0054] Meanwhile, when it is determined that both the count values CNTA and CNTB of the counters 401 and 402 are larger than the threshold T, that is, the deadlock state occurs, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1.” Accordingly, the deadlock controller 16 performs a shifting to the deadlock resolution mode and makes the extension entries 302 usable.).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
9. With regard to claim 4, Sato further teaches:
wherein determining the first FHA request status comprises:
determining a capability of the FHA controller to enable FHA activation within first system scope ([0032] The deadlock controller 16 determines whether the deadlock state occurs, based on the busy signal BSYI input from another node of the next stage and the signals Q11W and Q11R output from the remote queue Q11. When it is determined that the deadlock state occurs, the deadlock controller 16 performs shifting to the deadlock resolution mode and outputs a suppression signal QAS (value “1”) for suppressing an issuance of a new request from the own node from the ring bus. In addition, when the number of entries being used in the remote queue Q11 reaches the number of the usable entries, the deadlock controller 16 outputs a busy signal BSYO (value “1”) to another node of the previous stage.); and
determining, based on a current state of the FHA controller and a general system state, a blocking condition for enabling FHA activation, wherein the first FHA request status comprises an enabled activation status when the capability of the FHA controller and the blocking condition both indicate FHA activation is allowed for the FHA condition at the FHA controller ([0044] Accordingly, in the normal mode, when the number of entries used in the remote queue Q11 reaches the threshold A, the transmission of a request from another node of the previous stage to the own node is suppressed.; [0052] Meanwhile, as a result of the determination in operation S602, when it is determined that the busy signal BSYI is “1,” the deadlock controller 16 determines whether the number of entries used in the remote queue Q11 is equal to or larger than the threshold A, in operation S604. As a result, when it is determined that the number of entries used in the remote queue Q11 is equal to or larger than the threshold A, the operation proceeds to operation S605, and otherwise, the operation returns to operation S601.).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
10. With regard to claim 5, Sato further teaches:
further comprising:
generating an internal FHA request at the FHA controller prior to activating FHA mechanisms ([0032] The deadlock controller 16 determines whether the deadlock state occurs, based on the busy signal BSYI input from another node of the next stage and the signals Q11W and Q11R output from the remote queue Q11.);
detecting, based on a current state of the FHA controller and a general system state, that an FHA activation for the FHA controller is masked ([0032] When it is determined that the deadlock state occurs, the deadlock controller 16 performs shifting to the deadlock resolution mode and outputs a suppression signal QAS (value “1”) for suppressing an issuance of a new request from the own node from the ring bus; [0034] FIG. 4 is a view illustrating an example of a configuration of the deadlock controller 16 according to the first embodiment. The deadlock controller 16 includes counters 401, 402, and 411, logical OR operation circuits (OR circuits) 403 and 404, threshold holding circuits 405, 412, 413, and 414, comparison circuits 406, 407, 415, and 416, a logical AND operation circuit (AND circuit) 408, a flag holding circuit 409, and a selector 418; [0035] The counter 401 counts a time period during which the busy signal BSYI is output (the value is “1”) from another node of the next stage, and outputs a count value CNTA. The counter 402 counts a time period during which the busy signal BSYO is output (the value is “1”) from the own node, and outputs a count value CNTB. For example, when the busy signal BSYI is “1,” the counter 401 increments the count value CNTA by 1 per cycle of a clock signal (not illustrated), and when the output of the OR circuit 403 becomes “1,” the counter 401 clears the count value CNTA to “0.” In addition, for example, when the busy signal BSYO is “1,” the counter 402 increments the count value CNTB by 1 per cycle of a clock signal (not illustrated), and when the output of the OR circuit 404 becomes “1,” the counter 402 clears the count value CNTB to “0.”); and
wherein activating FHA mechanisms comprises:
activating the internal FHA request on the FHA controller ([0046] First, in operation S501, the deadlock controller 16 determines whether the deadlock state occurs. In the normal mode, when both the count values CNTA and CNTB of the counters 401 and 402 are larger than the threshold T, the deadlock controller 16 determines that the deadlock state occurs, and the operation proceeds to operation S502. That is, in the normal mode, when the busy signals BSYI and BSYO are continuously output for a longer time than the threshold T, the deadlock controller 16 determines that the remote queues Q11 of the own node and another node of the next stage are clogged, and thus, the deadlock state occurs.); and
suppressing activation at one or more other FHA components in the first system scope ([0047] Next, in operation S502, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1,” and performs shifting to the deadlock resolution mode (entry extension mode). Subsequently, in operation S503, the deadlock controller 16 sets the suppression signal QAS to “1” so as to suppress the issuance of a new request from the own node to the ring bus, as a result of the change of the flag held by the flag holding circuit 409 to “1.”).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
11. With regard to claim 7, Sato further teaches:
further comprising:
detecting a completion of the resource request at the FHA controller ([0048] In addition, in operation S504, when the number of the usable entries in the remote queue Q11 increases (extends), the deadlock controller 16 sets the busy signal BSYO to “0” so as to release the state of suppressing the reception of a request via the ring bus and receive a request from another node of the previous stage. ); and
deactivating the FHA mechanisms on the at least one FHA component within the first system scope ([0048] Then, in operation S505, the deadlock controller 16 waits until requests are sequentially processed and the number of entries used in the remote queue Q11 becomes less than the threshold C1. In operation S506, when the number of entries used in the remote queue Q11 becomes less than the threshold C, the deadlock controller 16 changes the flag held by the flag holding circuit 409 to “0,” and performs shifting from the deadlock resolution mode to the normal mode.).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
12. Regarding claim 8, it is rejected under the same reasoning as claim 1 above. Therefore, it is rejected under the same rationale.
13. Regarding claim 9, it is rejected under the same reasoning as claim 2 above. Therefore, it is rejected under the same rationale.
14. Regarding claim 10, it is rejected under the same reasoning as claim 3 above. Therefore, it is rejected under the same rationale.
15. Regarding claim 11, it is rejected under the same reasoning as claim 4 above. Therefore, it is rejected under the same rationale.
16. Regarding claim 12, it is rejected under the same reasoning as claim 5 above. Therefore, it is rejected under the same rationale.
17. Regarding claim 14, it is rejected under the same reasoning as claim 7 above. Therefore, it is rejected under the same rationale.
18. With regard to claim 15, Sato teaches:
A method comprising:
receiving, at a fast hang avoidance (FHA) controller for a first level in a system, a resource request for a resource, the first level including a first plurality of requestors ([0026] The CPU 11 performs an arithmetic processing and issues a request. According to the received request, the memory controller 13 performs data write or data read with respect to the memory 12. The crossbar unit (XB) 14 determines a reception destination of a packet such as the request transmitted via the ring bus (RING), and controls the transmission of the packet. Further, the crossbar unit (XB) 14 detects the deadlock state and performs a control to suppress the occurrence of the deadlock; [0027] The crossbar unit (XB) 14 includes four queues (buffers) Q11, Q12, Q21, and Q22 each corresponding to a holding unit, arbitration units (selectors) 15 and 18, a deadlock controller 16, and a suppression unit 17. The requests REQF and REQN input to the crossbar unit (XB) 14 are stored in one of the queues (buffers) Q11, Q12, Q21, and Q22 based on reception destination (issuance destination) information in the requests. Each of the queues (buffers) Q11, Q12, Q21, and Q22 has a plurality of entries.);
detecting, at the FHA controller, a current FHA activation status ([0032] When it is determined that the deadlock state occurs, the deadlock controller 16 performs shifting to the deadlock resolution mode and outputs a suppression signal QAS (value “1”) for suppressing an issuance of a new request from the own node from the ring bus. In addition, when the number of entries being used in the remote queue Q11 reaches the number of the usable entries, the deadlock controller 16 outputs a busy signal BSYO (value “1”) to another node of the previous stage; [0042] The comparison circuit 415 outputs “1” when the count value CNTC is equal to or larger than the threshold A [...]; [0044] Accordingly, in the normal mode, when the number of entries used in the remote queue Q11 reaches the threshold A, the transmission of a request from another node of the previous stage to the own node is suppressed.);
determining active FHA mechanisms for the resource request based on a request type for the resource request, FHA settings at the FHA controller, and the current FHA activation status ([0027] The crossbar unit (XB) 14 includes four queues (buffers) Q11, Q12, Q21, and Q22 each corresponding to a holding unit, arbitration units (selectors) 15 and 18, a deadlock controller 16, and a suppression unit 17. The requests REQF and REQN input to the crossbar unit (XB) 14 are stored in one of the queues (buffers) Q11, Q12, Q21, and Q22 based on reception destination (issuance destination) information in the requests. Each of the queues (buffers) Q11, Q12, Q21, and Q22 has a plurality of entries; [0032] The deadlock controller 16 determines whether the deadlock state occurs, based on the busy signal BSYI input from another node of the next stage and the signals Q11W and Q11R output from the remote queue Q11. When it is determined that the deadlock state occurs, the deadlock controller 16 performs shifting to the deadlock resolution mode and outputs a suppression signal QAS (value “1”) for suppressing an issuance of a new request from the own node from the ring bus. In addition, when the number of entries being used in the remote queue Q11 reaches the number of the usable entries, the deadlock controller 16 outputs a busy signal BSYO (value “1”) to another node of the previous stage; [0033] According to the suppression signal QAS output from the deadlock controller 16, the suppression unit 17 controls the transmission of the request from the local queue Q12 to the arbitration unit 15. When the value of the suppression signal QAS is “1,” the suppression unit 17 suppresses the transmission of the request from the local queue Q12 to the arbitration unit 15, and suppresses the issuance of a new request to the ring bus.); and
processing the resource request according to the active FHA mechanisms, comprising:
blocking the first plurality of requestors from sending additional resource requests ([0032] When it is determined that the deadlock state occurs, the deadlock controller 16 performs shifting to the deadlock resolution mode and outputs a suppression signal QAS (value “1”) for suppressing an issuance of a new request from the own node from the ring bus. In addition, when the number of entries being used in the remote queue Q11 reaches the number of the usable entries, the deadlock controller 16 outputs a busy signal BSYO (value “1”) to another node of the previous stage; [0042] The comparison circuit 415 outputs “1” when the count value CNTC is equal to or larger than the threshold A [...]; [0044] Accordingly, in the normal mode, when the number of entries used in the remote queue Q11 reaches the threshold A, the transmission of a request from another node of the previous stage to the own node is suppressed.);
receiving at a second FHA controller for a second level in a system, a second resource request for the resource, the second level including the first plurality of requestors and at least one additional requestor detecting a second FHA activation status ([0046] First, in operation S501, the deadlock controller 16 determines whether the deadlock state occurs. In the normal mode, when both the count values CNTA and CNTB of the counters 401 and 402 are larger than the threshold T, the deadlock controller 16 determines that the deadlock state occurs, and the operation proceeds to operation S502. That is, in the normal mode, when the busy signals BSYI and BSYO are continuously output for a longer time than the threshold T, the deadlock controller 16 determines that the remote queues Q11 of the own node and another node of the next stage are clogged, and thus, the deadlock state occurs; [0047] Next, in operation S502, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1,” and performs shifting to the deadlock resolution mode (entry extension mode). Subsequently, in operation S503, the deadlock controller 16 sets the suppression signal QAS to “1” so as to suppress the issuance of a new request from the own node to the ring bus, as a result of the change of the flag held by the flag holding circuit 409 to “1.”.);
determining active FHA mechanisms for the second resource request based on a second request type for the second resource request, FHA settings at the FHA controller, and the second FHA activation status ([0047] Next, in operation S502, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1,” and performs shifting to the deadlock resolution mode (entry extension mode). Subsequently, in operation S503, the deadlock controller 16 sets the suppression signal QAS to “1” so as to suppress the issuance of a new request from the own node to the ring bus, as a result of the change of the flag held by the flag holding circuit 409 to “1.”); and
processing the resource request according to the active FHA mechanisms for the second resource request ([0047] Next, in operation S502, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1,” and performs shifting to the deadlock resolution mode (entry extension mode). Subsequently, in operation S503, the deadlock controller 16 sets the suppression signal QAS to “1” so as to suppress the issuance of a new request from the own node to the ring bus, as a result of the change of the flag held by the flag holding circuit 409 to “1.”).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
19. With regard to claim 16, Sato further teaches:
further comprising:
receiving an FHA request from at least one external FHA controller ([0032] The deadlock controller 16 determines whether the deadlock state occurs, based on the busy signal BSYI input from another node of the next stage and the signals Q11W and Q11R output from the remote queue Q11.);
determining an applicability of the FHA request to the FHA controller ([0044] Accordingly, in the normal mode, when the number of entries used in the remote queue Q11 reaches the threshold A, the transmission of a request from another node of the previous stage to the own node is suppressed.; [0052] Meanwhile, as a result of the determination in operation S602, when it is determined that the busy signal BSYI is “1,” the deadlock controller 16 determines whether the number of entries used in the remote queue Q11 is equal to or larger than the threshold A, in operation S604. As a result, when it is determined that the number of entries used in the remote queue Q11 is equal to or larger than the threshold A, the operation proceeds to operation S605, and otherwise, the operation returns to operation S601.); and
setting the current FHA activation status as active based on the applicability of the FHA request ([0046] First, in operation S501, the deadlock controller 16 determines whether the deadlock state occurs. In the normal mode, when both the count values CNTA and CNTB of the counters 401 and 402 are larger than the threshold T, the deadlock controller 16 determines that the deadlock state occurs, and the operation proceeds to operation S502. That is, in the normal mode, when the busy signals BSYI and BSYO are continuously output for a longer time than the threshold T, the deadlock controller 16 determines that the remote queues Q11 of the own node and another node of the next stage are clogged, and thus, the deadlock state occur; [0047] Next, in operation S502, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1,” and performs shifting to the deadlock resolution mode (entry extension mode). Subsequently, in operation S503, the deadlock controller 16 sets the suppression signal QAS to “1” so as to suppress the issuance of a new request from the own node to the ring bus, as a result of the change of the flag held by the flag holding circuit 409 to “1.”).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
20. With regard to claim 17, Sato further teaches:
further comprising:
activating at least one FHA mechanisms via the FHA controller according to the FHA request wherein active FHA mechanisms comprise one or more of:
blocking, at the FHA controller, new requests from resource requestors ([0032] The deadlock controller 16 determines whether the deadlock state occurs, based on the busy signal BSYI input from another node of the next stage and the signals Q11W and Q11R output from the remote queue Q11. When it is determined that the deadlock state occurs, the deadlock controller 16 performs shifting to the deadlock resolution mode and outputs a suppression signal QAS (value “1”) for suppressing an issuance of a new request from the own node from the ring bus.);
altering a handling of the new requests at the FHA controller using one or more controller hang avoidance mechanisms ([0032] n addition, when the number of entries being used in the remote queue Q11 reaches the number of the usable entries, the deadlock controller 16 outputs a busy signal BSYO (value “1”) to another node of the previous stage; [0033] According to the suppression signal QAS output from the deadlock controller 16, the suppression unit 17 controls the transmission of the request from the local queue Q12 to the arbitration unit 15. When the value of the suppression signal QAS is “1,” the suppression unit 17 suppresses the transmission of the request from the local queue Q12 to the arbitration unit 15, and suppresses the issuance of a new request to the ring bus.); and
altering handling of the new requests or pending requests at the resource, wherein the resource processes the new requests according to one or more resource provider hang avoidance mechanisms ([0047] Next, in operation S502, the deadlock controller 16 changes the flag that is held by the flag holding circuit 409 and indicates the deadlock resolution mode, to “1,” and performs shifting to the deadlock resolution mode (entry extension mode). Subsequently, in operation S503, the deadlock controller 16 sets the suppression signal QAS to “1” so as to suppress the issuance of a new request from the own node to the ring bus, as a result of the change of the flag held by the flag holding circuit 409 to “1.”; [0048] In addition, in operation S504, when the number of the usable entries in the remote queue Q11 increases (extends), the deadlock controller 16 sets the busy signal BSYO to “0” so as to release the state of suppressing the reception of a request via the ring bus and receive a request from another node of the previous stage. Then, in operation S505, the deadlock controller 16 waits until requests are sequentially processed and the number of entries used in the remote queue Q11 becomes less than the threshold C1. In operation S506, when the number of entries used in the remote queue Q11 becomes less than the threshold C, the deadlock controller 16 changes the flag held by the flag holding circuit 409 to “0,” and performs shifting from the deadlock resolution mode to the normal mode.).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
21. With regard to claim 20, Sato further teaches:
further comprising:
receiving, from an external FHA controller, an FHA deactivation notice corresponding to active FHA mechanisms at the FHA controller ([0048] In addition, in operation S504, when the number of the usable entries in the remote queue Q11 increases (extends), the deadlock controller 16 sets the busy signal BSYO to “0” so as to release the state of suppressing the reception of a request via the ring bus and receive a request from another node of the previous stage.);
deactivating the active FHA mechanisms at the FHA controller ([0048] Then, in operation S505, the deadlock controller 16 waits until requests are sequentially processed and the number of entries used in the remote queue Q11 becomes less than the threshold C1. In operation S506, when the number of entries used in the remote queue Q11 becomes less than the threshold C, the deadlock controller 16 changes the flag held by the flag holding circuit 409 to “0,” and performs shifting from the deadlock resolution mode to the normal mode.); and
passing new resource requests at the FHA controller to corresponding requested resources ([0048] In operation S506, when the number of entries used in the remote queue Q11 becomes less than the threshold C, the deadlock controller 16 changes the flag held by the flag holding circuit 409 to “0,” and performs shifting from the deadlock resolution mode to the normal mode).
Although Sato describes a deadlock resolution mode in order to effectively combat deadlocks by determining when to switch the system into a deadlock resolution mode based on comparisons to thresholds, Sato refers to only deadlocks, which to one of ordinary skill in the art, would understand to be a condition where multiple tasks are frozen because each holds a resource the other needs. Sato does not specifically teach of hangs.
However, in analogous art, Okamura teaches that a hang is caused by a deadlock:
[0103] Let us assume that, at this point, an inter-controller deadlock has occurred between the controller 12A and the controller 12B (S83). As a result, at the controller 12A and the controller 12B where the inter-controller deadlock has occurred, a CPU hang occurs due to the inter-controller deadlock (S84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato with the teachings of Okamura where a hang occurs because of a deadlock. By showing that hangs can be caused by deadlocks, one can equate deadlocks and hangs. Therefore, the deadlock components are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller.
22. Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sato US 20190018776 A1 and Okamura et al. US 20200159918 A1, as applied in claim 1, in view of Klemm et al. US 7243267 B2.
With regard to claim 6, Sato and Okamura teach the method of claim 1 but fails to explicitly teach wherein the FHA condition comprises a pending time for a resource request, and wherein the first threshold for FHA activation comprises a time threshold for the first system scope.
However, in analogous art, Klemm teaches:
wherein the FHA condition comprises a pending time for a resource request (Col. 5, lines 64-67, where the activity is deemed excessive when it exceeds user-specified thresholds for duration and frequency; raised and caught exception; Examiner’s Note: Threads have a time condition that is specified by the user.), and
wherein the first threshold for FHA activation comprises a time threshold for the first system scope (Col. 5, lines 40-67, Having met these conditions, JAS can detect the following target application and JVM events that potentially impact the availability of the target application: process crash due to a fault in the virtual machine or application native code process termination due to an external force such as a machine shutdown or kill signal to the process; process hang (process execution time exceeds user-specified threshold); thread failure due to an uncaught exception; thread termination without an exception (if a thread is supposed to run forever, its termination would indicate a problem); thread starvation (one or more threads in the application rarely or never obtain the CPU because other threads dominate the CPU); thread hang (thread execution time exceeds user-specified threshold); illegal or excessive number of threads relative to a user-specified threshold; application exits with an error code (call to System.exit(n) where n is different from a user-specified number that indicates a normal application completion) excessive garbage collector activity, where the activity is deemed excessive when it exceeds user-specified thresholds for duration and frequency; raised and caught exception.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato and Okamura with the teachings of Klemm wherein the FHA condition comprises a pending time for a resource request, and wherein the first threshold for FHA activation comprises a time threshold for the first system scope. Okamura shows that hangs can be caused by deadlocks, allowing one to equate deadlocks and hangs. Therefore, the deadlock components in Sato are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller. Moreover, Klemm teaches of detecting hangs in a Java specific environment. There are user-defined thresholds in Klemm that allow an activity to be deemed excessive when it surpasses said thresholds. For example, the JAS is able to detect when a process hang occurs because the process execution time has exceeded a user-defined threshold. This allows the application to exit with an error code (call to System.exit(n) where n is different from a user-specified number that indicates a normal application completion), as discussed in Klemm (Col. 5, lines 61-63). Therefore, deploying a hang avoidance mechanism that allows the user to determine that there is an error and correct it accordingly.
Regarding claim 13, it is rejected under the same reasoning as claim 6 above. Therefore, it is rejected under the same rationale.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sato US 20190018776 A1 and Okamura et al. US 20200159918 A1, as applied in claim 15, in further view of Shibaike et al. US 20220369291 A1.
With regard to claim 18, Sato and Okamura teach the method of claim 15 but fails to explicitly teach wherein determining active FHA mechanisms for the resource request comprises: determining, from FHA settings at the FHA controller and the resource request, an FHA override setting, wherein the FHA controller processes the resource request without implementing FHA mechanisms when the FHA override setting indicates an FHA override for the resource request.
However, in analogous art, Shibaike teaches:
wherein determining active FHA mechanisms for the resource request comprises:
determining, from FHA settings at the FHA controller and the resource request, an FHA override setting, wherein the FHA controller processes the resource request without implementing FHA mechanisms when the FHA override setting indicates an FHA override for the resource request ([0108] Pre-emption means that a transmission for which resources have already been allocated is stopped, and the already allocated resources are used for another transmission that has been requested later, but has lower latency/higher priority requirements; Examiner’s Note: The resources allocated to other transmissions are given to transmissions that have higher priority. FHA mechanism of suspension based on a threshold is overridden for a task of higher priority. Even though resources had already been allocated (similarly to how the threshold has been reached), any new requests should be temporarily suspended, but since this transmission has a higher priority, it is allocated resources.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato and Okamura with the teachings of Shibaike wherein determining active FHA mechanisms for the resource request comprises: determining, from FHA settings at the FHA controller and the resource request, an FHA override setting, wherein the FHA controller processes the resource request without implementing FHA mechanisms when the FHA override setting indicates an FHA override for the resource request. Okamura shows that hangs can be caused by deadlocks, allowing one to equate deadlocks and hangs. Therefore, the deadlock components in Sato are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller. Similarly, Shibaike teaches of resource allocation in order to enact congestion control or collision avoidance. Shibaike teaches that the resources allocated to other transmissions are given to transmissions that have higher priority. FHA mechanism of suspension based on a threshold is overridden for a task of higher priority. Even though resources had already been allocated (similarly to how the threshold has been reached), any new requests should be temporarily suspended, but since this transmission has a higher priority, it is allocated resources. This shows an overriding mechanism that might be beneficial to ensure tasks with high priority are still able to be executed, even when resources have been allocated.
With regard to claim 19, Shibaike further teaches:
wherein the FHA override setting comprises a gating condition for a resource request, wherein the resource request comprises a first level of coherency, wherein the first level of coherency is greater than a gating threshold for the resource request, and wherein the FHA controller overrides the active FHA mechanisms to allow the resource request to pass to the resource ([0108] Pre-emption means that a transmission for which resources have already been allocated is stopped, and the already allocated resources are used for another transmission that has been requested later, but has lower latency/higher priority requirements; Examiner’s Note: The resources allocated to other transmissions are given to transmissions that have higher priority. FHA mechanism of suspension based on a threshold is overridden for a task of higher priority. Even though resources had already been allocated (similarly to how the threshold has been reached), any new requests should be temporarily suspended, but since this transmission has a higher priority, it is allocated resources. The threshold is the priority).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sato and Okamura with the teachings of Shibaike wherein determining active FHA mechanisms for the resource request comprises: determining, from FHA settings at the FHA controller and the resource request, an FHA override setting, wherein the FHA controller processes the resource request without implementing FHA mechanisms when the FHA override setting indicates an FHA override for the resource request. Okamura shows that hangs can be caused by deadlocks, allowing one to equate deadlocks and hangs. Therefore, the deadlock components in Sato are analogous to the FHA elements mentioned throughout the claims (i.e. deadlock controller = FHA controller). In conclusion, it would be obvious to combine Sato and Okamura to teach of a hang avoidance system that determines activation of hang avoidance mechanisms. The determination is based on comparisons to thresholds and additional factors such as system scope, request state for resource request, and activation settings for the hang controller. Similarly, Shibaike teaches of resource allocation in order to enact congestion control or collision avoidance. Shibaike teaches that the resources allocated to other transmissions are given to transmissions that have higher priority. FHA mechanism of suspension based on a threshold is overridden for a task of higher priority. Even though resources had already been allocated (similarly to how the threshold has been reached), any new requests should be temporarily suspended, but since this transmission has a higher priority, it is allocated resources. This shows an overriding mechanism that might be beneficial to ensure tasks with high priority are still able to be executed, even when resources have been allocated.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AN-AN NGOC NGUYEN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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