Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- 5, 8, 9, 14, 15 and 16 are rejected under 35 U.S.C. 102a1 as being anticipated by Han (U.S. Patent Application Publication 2014/ 076619).
Regarding claim 1, Han discloses a method (figs. 4a-4e) comprising:
providing a substrate (Han, 201, fig. 2A);
forming a seed layer on the substrate (202);
forming a first metal layer (204) on selected portions of the seed layer (103) to form exposed portions of the seed layer (fig. 2d); and
scanning a laser beam across the substrate to remove the exposed portions of the seed layer to form exposed portions of the substrate (¶0015, fig. 2F).
Regarding claim 2, Han discloses all the limitations of claim 1, as above, and further discloses a method wherein scanning a laser beam comprises scanning a laser beam using an excimer laser (¶¶0009, 0047, “excimer”), a ultraviolet laser, an infrared laser, or a near-infrared laser.
Regarding claim 3, Han discloses all the limitations of claim 2, as above, and further discloses a method wherein scanning a laser beam comprises scanning a laser beam using an excimer laser (Han, ¶¶0009, 0047).
Regarding claim 4, Han discloses all the limitations of claim 3, as above, and further discloses a method wherein scanning a laser beam comprises scanning a laser beam using an excimer laser at 1 J/cm2 or less fluence (Han, ¶47, “650 mJ/cm2).
Regarding claim 5, Han discloses all the limitations of claim 4, as above, and further discloses a method wherein scanning a laser beam comprises scanning a laser beam using an excimer laser at 0.3 J/cm2 to 0.8 J/cm2 fluence. (Han, ¶47 “650 mJ/cm2).
Regarding claim 8, Han discloses all the limitations of claim 1, as above, and further discloses a method wherein the seed layer comprises palladium (Pd), titanium copper (TiCu), nickel chromium (NiCr), copper (Cu) (Han, ¶0014, “copper seed layer”), or chromium (Cr).
Regarding claim 9, Han discloses all the limitations of claim 1, as above, and further discloses a method wherein the first metal layer comprises copper (Cu) (Han, ¶0020, “plating layer may be a copper (CU) plating layer”).
Regarding claim 14, Han discloses an assembly (Han, figs. 1-3) comprising:
a substrate (201);
a seed layer (202) on the substrate;
a first metal layer (204) on selected portions of the seed layer to define exposed portions of the seed layer;
wherein the assembly comprises exposed portions of the substrate (figs. 2d-2f).
Regarding claim 15, Han discloses all the limitations of claim 14, as above, and further discloses an assembly wherein the seed layer comprises palladium (Pd), titanium copper (TiCu), nickel chromium (NiCr), copper (Cu) (Han, ¶0014, “copper seed layer”), or chromium (Cr).
Regarding claim 16, Han discloses all the limitations of claim 14, as above, and further discloses an assembly wherein the first metal layer comprises copper (Han, ¶0020, “plating layer may be a copper (CU) plating layer”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being obvious over Han (U.S. Patent Application Publication 2014/ 076619) in view of Nakao (U.S. Patent Application Publication 2011/ 0011632)
Regarding claim 6, Han discloses all the limitations of claim 3, as above, but does not further disclose a method wherein scanning a laser beam comprises scanning a laser beam using an excimer laser at 10 or less pulse per second. However, Nakao teaches an excimer laser for making conductors, uses a conventional (Nakao, ¶0162, “having a pulse frequency of from 1 to 10 Hz). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Han with the teachings of Nakao, and given that Han himself teaches a “pulsed laser” (Han ¶0047, laser irradiated in a “pulse mode”), just not at what regularity, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Han with the teachings of Nakao, to use a conventional method in a conventional way, pulsing a laser in a conventional way to achieve the expected result of laser processing these materials.
Regarding claim 7, Han in view of Nakao teaches all the limitations of claim 6, as above, but does not further disclose a method wherein scanning a laser beam comprises scanning a laser beam using an excimer laser at 1 to 4 pulse per second. Now, as noted above, Nakao teaches 1- 10 pulses per second. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Han in view of Nakao, already teaching 1-10 pulses per second, that through routine experimentation of the already taught limitations, would hit on the limitations of this claim (which is a subset of the entire taught range), to achieve the expected result of laser processing the material, the different routine experimentations adjusting for time and speed and efficiency, and thus pulsing within this range would have been obvious.
Claims 10,11, 17, 18 are rejected under 35 U.S.C. 103 as being obvious over Han (U.S. Patent Application Publication 2014/ 076619) in view of Noh (U.S. Patent Application Publication 2011/ 0297423).
Regarding claim 10, Han discloses all the limitations of claim 1, as above, but does not further disclose a method wherein the substrate comprises a dielectric Ajinomoto Build-up Film, a solder resist film, or any dielectric film. However, Noh teaches wherein the substrate comprises a dielectric Ajinomoto Build-up Film, a solder resist film (Noh, 16, 160, ¶0068), or any dielectric film. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Han with the teachings of Noh, to substitute Han’s “photo resist” (Han, Abstract, “photo resist layer”, 203) with the teaching of Noh, adding a solder resist layer, in order to prevent application of solder on unintended locations, and then, in the case of Han, having the seed layer removed, using a conventional material in a conventional way to achieve the expected result of preventing further material build-up where none is desired.
Regarding claim 11, Han discloses all the limitations of claim 1, as above, but does not further disclose a method comprising forming a solder resist layer (on selected regions of the exposed portions of the substrate. However, Noh teaches forming a solder resist layer (Noh, 16, 160, ¶0068) on selected regions of the exposed portions of the substrate Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Han with the teachings of Noh, to substitute Han’s “photo resist” (Han, Abstract, “photo resist layer”, 203) with the teaching of Noh, adding a solder resist layer, in order to prevent application of solder on unintended locations, and then, in the case of Han, having the seed layer removed, using a conventional material in a conventional way to achieve the expected result of preventing further material build-up where none is desired.
Regarding claim 17, Han discloses all the limitations of claim 14, as above, but does not further disclose an assembly wherein the substrate comprises a dielectric Ajinomoto Build-up Film, a solder resist film, or any dielectric film. However, Noh teaches wherein the substrate comprises a dielectric Ajinomoto Build-up Film, a solder resist film (Noh, 16, 160, ¶0068), or any dielectric film. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Han with the teachings of Noh, to substitute Han’s “photo resist” (Han, Abstract, “photo resist layer”, 203) with the teaching of Noh, adding a solder resist layer, in order to prevent application of solder on unintended locations, and then, in the case of Han, having the seed layer removed, using a conventional material in a conventional way to achieve the expected result of preventing further material build-up where none is desired.
Regarding claim 18, Han discloses all the limitations of claim 14, as above, but does not further disclose an assembly wherein comprising a solder resist layer on selected portions of the substrate. However, Noh teaches forming a solder resist layer (Noh, 16, 160 ¶0068) on selected regions of the exposed portions of the substrate Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Han with the teachings of Noh, to substitute Han’s “photo resist” (Han, Abstract, “photo resist layer”, 203) with the teaching of Noh, adding a solder resist layer, in order to prevent application of solder on unintended locations, and then, in the case of Han, having the seed layer removed, using a conventional material in a conventional way to achieve the expected result of preventing further material build-up where none is desired.
Claims 12, 13, 19, and 20 are rejected under 35 U.S.C. 103 as being obvious over Han (U.S. Patent Application Publication 2014/ 076619) in view of Tatsumi (U.S. Patent Application Publication 2021/ 0025069).
Regarding claim 12, Han discloses all the limitations of claim 11, as above, but does not further disclose a method comprising forming a second metal layer on the first metal layer. However, Tatsumi teaches forming a second metal layer on the first metal layer (Tatsumi, figs. 1, 2; tin layer 17a, 17b on first copper layer 6). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Han with the teachings of Tatsumi, to have a further second layer, of tin, applied to over the first layer, in order to coat the circuit with a further metal in order to protect the circuit from corrosion better while still maintaining enhanced electrical conductivity (as tin is a great conductor) and allows for better manipulation for shaping or forming or connecting to other joints.
Regarding claim 13, Han in view of Tatsumi teaches all the limitations of claim 12, as above, and further teaches a method wherein the second metal layer comprises nickel/palladium/gold (Ni/Pd/Au) or tin (Sn) (Tatsumi, figs. 1, 2; tin layer 17a, 17b on first copper layer 6; see combination in rejection of claim 12, above).
Regarding claim 19, Han discloses all the limitations of claim 18, as above, but does not further disclose an assembly wherein comprising a second metal layer on the first metal layer. However, Han teaches an assembly wherein comprising a second metal layer on the first metal layer. (Tatsumi, figs. 1, 2; tin layer 17a, 17b on first copper layer 6). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Han with the teachings of Tatsumi, to have a further second layer, of tin, applied to over the first layer, in order to coat the circuit with a further metal in order to protect the circuit from corrosion better while still maintaining enhanced electrical conductivity (as tin is a great conductor) and allows for better manipulation for shaping or forming or connecting to other joints.
Regarding claim 20, Han in view of Tatsumi teaches all the limitations of claim 19, as above, and further teaches an assembly wherein the second metal layer comprises nickel/palladium/gold (Ni/Pd/Au) or tin (Sn) (Tatsumi, figs. 1, 2; tin layer 17a, 17b on first copper layer 6; This was combined in the combination above in the rejection of claim 19).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see attached form PTO-892
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE H SAMUELS whose telephone number is (571)272-2683. The examiner can normally be reached 9AM-5PM M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ibrahime Abraham can be reached at 571-270-5569. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAWRENCE H SAMUELS/Examiner, Art Unit 3761
/IBRAHIME A ABRAHAM/Supervisory Patent Examiner, Art Unit 3761
Prosecution Insights