DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The Examiner acknowledges that the Applicant’s amendments to claims 5, 12 and 19 resolves the previous rejections of claims 5, 12 and 19 under 35 USC 112(d). Therefore, the previous rejection of claims 5, 12 and 19 under 35 USC 112(d) have been withdrawn.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15, claim 15 recites “wherein the vertical surface of the second gate is substantially flush with the vertical surface of the second gate”. The Examiner is unclear what structure this limitation is meant to claim as it is unclear how a vertical surface of a structure (the second gate) can be substantially flush with itself. As such, the language is unclear. Appropriate correction is required to clarify the language.
Claims 16-20 are also rejected under 35 USC 112(b) as they depend from and include all of the limitations of rejected claim 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 9, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 2021/0193527) hereinafter “Reznicek” in view of Cheng et al. (US 9755073) hereinafter “Cheng”.
Regarding claim 8, Fig. 25 of Reznicek teaches a semiconductor structure comprising: a vertical semiconductor channel region (Item 108); a bottom source drain region (Item 104) arranged on a substrate (Item 102) below the vertical semiconductor channel region (Item 108); and a metal gate (Item 132) disposed around the vertical semiconductor channel region (Item 108).
Reznicek does not teach where a vertical sidewall of the metal gate at a cell boundary is substantially flush with a vertical sidewall of the vertical semiconductor channel region.
Cheng teaches where a gate structure may wrap around three sides of the vertical fin (Column 15; Lines 45-48).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a gate structure wrap around only three sides of the vertical channel region of Reznicek such that a vertical sidewall of the metal gate at a cell boundary is substantially flush with a vertical sidewall of the vertical semiconductor channel region because having the metal gate on three sides of the vertical channel region is known to form an effective gate structure for a vertical field effect transistor(Cheng Column 15; Lines 47-48).
Regarding claim 9, Fig. 25 of Reznicek further teaches where a vertical sidewall of the metal gate (Item 132) is substantially flush with a vertical sidewall of the bottom source drain region (Item 104).
Regarding claim 13, Fig. 25 of Reznicek further teaches a top spacer (Item 140) separating the metal gate (Item 132) from a top source drain region (Item 144).
Regarding claim 14, Fig. 25 of Reznicek further teaches a bottom spacer (Item 114) separating the bottom source drain region (Item 104) from the metal gate (Item 132).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 2021/0193527) hereinafter “Reznicek” in view of Cheng et al. (US 9755073) hereinafter “Cheng” and in further view of Yeh et al. (US 2021/0210631) hereinafter “Yeh”.
Regarding claim 10, the combination of Reznicek and Cheng teaches all of the elements of the claimed invention as stated above except where a vertical sidewall of the vertical semiconductor channel region is substantially flush with a vertical sidewall of the bottom source drain region.
Fig.13 of Yeh teaches where a vertical sidewall of a vertical semiconductor channel region (Item 130) is substantially flush with a vertical sidewall of a bottom source drain region (Item 710).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a vertical sidewall of the vertical semiconductor channel region is substantially flush with a vertical sidewall of the bottom source drain region because it allows for a larger shallow trench isolation between fins of adjacent vertical transistors (Yeh Paragraph 0065).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 2021/0193527) hereinafter “Reznicek” in view of Kim et al. (US 2021/0193657) hereinafter “Kim” and in further view of Cheng et al. (US 9755073) hereinafter “Cheng”.
Regarding claim 11, the combination of Reznicek and Cheng teaches all of the elements of the claimed invention as stated above.
Fig. 25 of Reznicek further teaches a gate dielectric (Item 130) surrounding all sides of the vertical semiconductor channel region (Item 108).
Reznicek does not teach where the gate dielectric extends across a cell boundary.
Fig. 16B of Kim teaches where a gate dielectric (Item GI) extends across a cell boundary.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric layer extend across a cell boundary because the thickness of the gate insulating layer on a portion of a device isolation at a cell boundary adds to the thickness of the device isolation (Kim Paragraph 0085).
Reznicek does not teach where the metal gate surrounds only three sides of the gate dielectric.
Cheng teaches where a gate structure may wrap around three sides of the vertical fin (Column 15; Lines 45-48).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the metal gate surround only three sides of the gate dielectric because having the metal gate on three sides of the vertical channel region is known to form an effective gate structure for a vertical field effect transistor(Cheng Column 15; Lines 47-48).
Regarding claim 12, the combination of Reznicek, Kim and Cheng teaches all of the elements of the claimed invention as stated above.
Reznicek does not teach where the metal gate surrounds only three sides of the vertical semiconductor channel region.
Cheng teaches where a gate structure may wrap around three sides of the vertical fin (Column 15; Lines 45-48).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the metal gate surround only three sides of the vertical semiconductor channel region because having the metal gate on three sides of the vertical channel region is known to form an effective gate structure for a vertical field effect transistor(Cheng Column 15; Lines 47-48).
Allowable Subject Matter
Claims 1-7 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art does not teach, suggest or motivate one having skill in the art to have the third vertical surface of the first vertical channel is substantially flush with the third vertical surface of the second vertical channel, and wherein the second vertical surface of the first vertical channel and the first vertical surface of the second vertical channel abut a cell boundary; a first gate disposed only around the first vertical surface, the third vertical surface, and the fourth vertical surface of the first vertical channel; and a second gate disposed only around the second vertical surface, the third vertical surface, and the fourth vertical surface of the second vertical channel along with the other limitations of claim 1.
Response to Arguments
Applicant’s arguments, see Applicant’s REMARKS, filed 03/23/2026, with respect to claims 1-7 and 15-20 have been fully considered and are persuasive. Therefore, the rejections of claims 1-7 has been withdrawn. The basis of the indication of overcoming the previous rejection is a result of the limitations regarding the specific sides in which the gate surrounds the respective vertical channels along with the indication of the flushness and parallelness of the sides.
Applicant's arguments filed 03/23/2026, with respect to the rejection of claim 8, have been fully considered but they are not persuasive.
Specifically, the Applicant argues that the Examiner did not consider the limitation “a vertical sidewall of the metal gate at a cel boundary is substantially flush with a vertical sidewall of the vertical semiconductor channel region.”. The Examiner disagrees. In the previous, and current, rejection the Examiner stated that the limitation “a vertical sidewall of the metal gate at a cel boundary is substantially flush with a vertical sidewall of the vertical semiconductor channel region.” Is rendered obvious by the teaching in Cheng of a gate wrapping around three sides of a vertical channel fin. Whether or not the Applicant agrees with the Examiner’s rationale, the Examiner did consider and explicitly addressed the element in the rejection.
The Applicant further argues that that Cheng fails to inherently disclose “a vertical sidewall of the metal gate at a cell boundary is substantially flush with a vertical sidewall of the vertical semiconductor channel region.’. While the Examiner agrees that the Cheng reference does not explicitly teach “a vertical sidewall of the metal gate at a cell boundary is substantially flush with a vertical sidewall of the vertical semiconductor channel region.”, the Examiner does not agree that this does not render the limitation obvious in light of the teaching in Cheng. Column 15, Lines 45-48 of Cheng teach where a gate structure may wrap around three sides of the vertical fin. The Examiner avers based on this teaching that one having ordinary skill in the art would understand the wrapping of the gate on three sides of the vertical fin to result in a vertical sidewall of the metal gate at the cell boundary to be substantially flush with the vertical sidewall of the vertical semiconductor channel region. Further, the language in Cheng has no suggestion that the gate would be wrapped partially around on extend partially on the sides of the gate sidewalls such that one having ordinary skill in the art would reasonably understand that the gate would extend fully on three sides of the vertical fin. The Applicant further argues that because the gate, in Fig. 17 of Cheng, does not extend vertically on the entire surface of the gate that the statement of wrap around three sides of the vertical fin in Cheng would not be understood to have the gate extend horizontally around three sides of the gate such that a vertical sidewall of the gate at a cell boundary would be substantially flush with a vertical sidewall of the channel region. The Examiner disagrees. In Cheng, as with all other prior art that utilizes a vertical channel, a gate’s vertical coverage of a fin is dictated by an inventor’s desired coverage of an active area (channel) of the fin. The amount of vertical coverage of the fin varies from reference to refence and would not necessarily inherent or obvious to one having ordinary skill in the art. However, when considering the horizontal extension of a gate over a fin the prior art mainly covers and is generally understood by one having ordinary skill in the art to cover an entire side of a the fin such that when Cheng teaches that the gate may wrap around three sides of the fin, one having ordinary skill in the art would understand that to mean that it wraps completely around the three sides. Further, there is nothing to suggest in Cheng that the amount of coverage by the gate on a respective side would be limited in the horizontal direction. Therefore, the Examiner does not find the Applicant’s argument persuasive and maintains the rejection of claim 8 based on the combination of Reznicek and Cheng.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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