DETAILED ACTION
This Office Action is in response to the Remarks and Amendments filed on 21 January 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10, 13, 17-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected devices and methods, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02 September 2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. (US 2016/0155934 A1; hereinafter Hwang).
In regards to claim 1, Hwang teaches, e.g. figs. 1-2 and 25, a semiconductor structure (Title), the semiconductor structure comprising:
a magnetic tunnel junction (MTJ) pillar [0007] for a magnetoresistive random-access memory (MRAM) device (Title), the MTJ pillar including a reference laver (110) [0059], a tunnel barrier layer (122) [0073], and a free layer (130) [0063],
wherein a width of the tunnel barrier layer (W3) [0078] is greater than a width (W1) [0078] of the reference layer and is greater than a width (W2) [0062] of the free layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang as applied to claim 1 above, in view of Peng et al. (US 2020/0035907 A1; as cited in the Office Action dated 22 October 2025; hereinafter Peng).
In regards to claim 2, Hwang teaches the limitations discussed above in addressing claim 1. Hwang further teaches, e.g. in figs. 1-2 and 25, wherein the MTJ pillar further comprises:
a bottom electrode (248) [152]; the reference layer (110) [0059] on the bottom electrode;
the tunnel barrier layer (122) [0073] on the reference layer;
the free layer (130) [0063] on the tunnel barrier layer, wherein a width (W2) [0062] of the free layer is less than the width (W3) [0078] of the tunnel barrier layer; and a top electrode (140) [0057] on the free layer, wherein the top electrode has a tapered shape (fig. 2).
Hwang appears to be silent as to, but does not preclude, the limitations of a bottom electrode on a metal cap; and wherein the width of the reference layer is less than a width of the bottom electrode. Peng teaches the limitations of:
a bottom electrode (123/122a'/121a'/121a") [0040] on a metal cap (101) [0033];
a reference layer (pinned layer (1330)) [0029] on the bottom electrode, wherein the reference layer is less wide than the bottom electrode (fig. 2B: (123) is wider than the middle region of (130) in which reference layer (1330) resides); and
a top electrode (124) [0033] on the free layer, wherein the top electrode has a tapered shape (fig. 2).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hwang with the aforementioned limitations taught by Peng to have an MTJ cell with reduced thickness to lower risk of sputtering residue contamination at the side wall of the MTJ cell (Peng [0032]).
In regards to claim 3, the combination of Hwang and Peng teaches the limitations discussed above in addressing claim 2. Hwang further teaches, e.g. in figs. 1-2 and 25, the limitations further comprising: a sidewall encapsulation (160) [0070] formed around vertical sidewalls of the reference layer (110) [0059] and the free layer (130) [0063].
In regards to claim 4, the combination of Hwang and Peng teaches the limitations discussed above in addressing claim 3. Hwang further teaches, e.g. in figs. 1-2 and 25, the limitations wherein the reference layer (110) [0059] and the free layer (130) [0063] have the sidewall encapsulation (160) [0070] that is a same dielectric material (fig. 2).
In regards to claim 7, the combination of Hwang and Peng teaches the limitations discussed above in addressing claim 2. Hwang further teaches, e.g. in figs. 1-2 and 25, the limitations wherein a width of a bottom surface of the top electrode is greater than a width of a top surface of the top electrode (fig. 2: (160) is tapered shaped).
In regards to claim 8, the combination of Hwang and Peng teaches the limitations discussed above in addressing claim 2. Hwang further teaches, e.g. in figs. 1-2 and 25, the limitations wherein a width of a top surface of the top electrode is less than a width of a bottom surface of the top electrode (fig. 2: (160) is tapered shaped).
In regards to claim 9, the combination of Hwang and Peng teaches the limitations discussed above in addressing claim 2. Hwang further teaches, e.g. in figs. 1-2 and 25, the limitations wherein the top electrode (160) [0070] has a cone shape with a flat top surface and a flat bottom surface (fig. 2).
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hwang and Peng as applied to claim 3 above, in view of Yang et al. (US 10,770,654 B2; as cited in the Office Action dated 22 October 2025; hereinafter Yang).
In regards to claim 5, the combination of Hwang and Peng teaches the limitations discussed above in addressing claim 3. The combination of Hwang and Peng appears to be silent as to, but does not preclude, the limitations wherein a combined width of the reference layer and the sidewall encapsulation around the reference layer is approximately the same as the width of the tunnel barrier layer. Yang teaches the limitations wherein a combined width of the reference layer and the sidewall encapsulation around the reference layer is approximately the same as the width of the tunnel barrier layer (fig. 8: MTJ arrangement of a stack of layers, wherein each successive overlying layer overlying an adjacent underlying layer has a spacer making the successive overlying layer the same width as the adjacent underlying layer). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Hwang and Peng with the aforementioned limitations taught by Yang to have a process for forming an MTJ stack that prevents excessive damage (Yang col. 4/lns. 55-65).
In regards to claim 6, the combination of Hwang and Peng teaches the limitations discussed above in addressing claim 3. The combination of Hwang and Peng appears to be silent as to, but does not preclude, the limitations wherein a combined width of the free layer and the sidewall encapsulation around the free layer is approximately the same as a width of a bottom surface of the top electrode. Yang teaches the limitations wherein a combined width of the free layer and the sidewall encapsulation around the free layer is approximately the same as a width of a bottom surface of the top electrode (fig. 8: MTJ arrangement of a stack of layers, wherein each successive overlying layer overlying an adjacent underlying layer has a spacer making the successive overlying layer the same width as the adjacent underlying layer). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Hwang and Peng with the aforementioned limitations taught by Yang to have a process for forming an MTJ stack that prevents excessive damage (Yang col. 4/lns. 55-65).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hwang and Peng as applied to claim 2, in view of Hsu et al. (US 2021/0351348 A1; as cited in the Office Action dated 22 October 2025; hereinafter Hsu).
In regards to claim 11, the combination of Hwang and Peng teaches the limitations discussed above in addressing claim 2. The combination of Hwang and Peng appears to be silent as to, but does not preclude, the limitations further comprising a contact with a contact liner connecting to a top surface of the top electrode. Hsu teaches, e.g. in fig. 4, the limitations further comprising a contact (132) [0020] with a contact liner (131) [0025] connecting to a top surface of the top electrode (118) [0020]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Hwang and Peng with the aforementioned limitations taught by Hsu to prevent out-diffusion of electrode materials (Hsu [0024]).
Allowable Subject Matter
Claims 12 and 14-16 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 12, the closest prior art does not teach the combination of limitations of: a semiconductor structure of two adjacent magnetoresistive random-access memory devices, the semiconductor structure comprising: two bottom electrodes separated by a first layer of interlayer dielectric (ILD) material having a height corresponding to a height of the bottom electrodes; two reference layers with a first sidewall encapsulation separated by a second layer of interlayer dielectric material having a height corresponding to a height of the references layers; two tunnel barrier layers separated by a third layer of ILD material having a height corresponding to a height of the tunnel barrier layers; two free layers with a second sidewall encapsulation separated by a fourth layer of ILD material having a height corresponding to a height of the free layers; two top electrodes with a tapered sidewall separated by a fifth layer of ILD material having a height corresponding to a height of the top electrodes; and a contact on each of the two top electrodes in the fifth layer of ILD material.
The claims of the application at hand that depend from allowable claims are allowable because they respectively depend, directly or indirectly, from the allowable claims of the application at hand. Therefore, the dependent claims in question incorporate the allowable limitations of the claims from which they depend.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
Prosecution Insights