DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/02/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-12, 15-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo et. al. (US Patent Appl. Pub. No. 2021/0391275 A1).
[Re claim 1] Kuo discloses a semiconductor interconnect structure, comprising: a skip via, wherein the skip via includes a first skip via segment (42 or 58) vertically connected to a second skip via segment (44 or 60), wherein the first skip via segment has a first width and the second skip via segment has a second width (see figure 3 and 10 and paragraphs [0021], [0045]).
[Re claim 2] Kuo discloses the semiconductor interconnect structure further comprising: a first metal level (where 28 is located); a second metal level (metal where 42 is located); and a third metal level (metal where 44 is located), wherein: the second metal level is vertically located between the first metal level and the third metal level, and the skip via connects a first metal line (28) of the first metal level to a second metal line (56) of the third metal level (see figure 9-10 and paragraph [0045]-[0046]).
[Re claim 3] Kuo discloses the semiconductor interconnect structure wherein a centerline of the first metal line (28) of the first metal level is offset from a second centerline of the second metal line (56) of the third metal level (see figure 10).
[Re claim 4] Kuo discloses the semiconductor interconnect structure wherein the first skip via segment (58) and the second skip via segment (60) are made from a same conductive metal material (56) (see figure 9 and paragraph [0045]).
[Re claim 7] Kuo discloses the semiconductor interconnect structure wherein the first skip via segment and the second skip via segment have a first discontinuous taper angle of a first side (right side wall) and a second discontinuous taper angle of a second side (left side wall) (see figure 9).
[Re claim 8] Kuo discloses the semiconductor interconnect structure, comprising: a skip via (44 or 60); and a jumper (42 or 58), wherein the skip via is vertically connected to the jumper (see figure 3 and 10 and paragraphs [0021], [0045]).
[Re claim 9] Kuo discloses the semiconductor interconnect structure, further comprising: a first metal level (where 28 is located); a second metal level (where a metal is located at 42); and a third metal level (where a metal is located at 44), wherein: the second metal level is vertically located between the first metal level and the third metal level, the jumper (42) is connected to a first metal line and a second metal line of the first metal level, and the skip via connected to the jumper connects the first metal line and the second metal line of the first metal level to a third metal line of the third metal level (see figure 9-10 and paragraph [0045]-[0046]).
[Re claim 10] Kuo discloses the semiconductor interconnect structure wherein a first centerline of at least one of the first metal line or the second metal line of the first metal level is offset from a second centerline of the third metal line of the third metal level (see figure 9-10).
[Re claim 11] Kuo discloses the semiconductor interconnect structure wherein a first centerline of the jumper is offset from a second centerline of the third metal line of the third metal level (see figure 9-10).
[Re claim 12] Kuo discloses the semiconductor interconnect structure wherein the skip via (44) and the jumper (42) are made from a same conductive metal material (56) (see figure 9 and paragraph [0045]).
[Re claim 15] Kuo discloses the semiconductor interconnect structure wherein the skip via and the jumper have a first discontinuous taper angle of a first side (right side wall) and a second discontinuous taper angle of a second side (left side wall) (see figure 9).
[Re claim 16] Kuo discloses the method of forming a semiconductor interconnect structure, comprising: forming a first metal level (where 28 is located), wherein the first metal level includes one or more metal lines (28); forming a second metal level (a metal located at 42) above the first metal level, wherein the second metal level includes one or more metal lines (56); forming a third metal level (a metal located at 44) above the second metal level, wherein the third metal level includes one or more metal lines (56), and wherein a first metal line (28) of the first metal level has a first centerline that is offset from a second centerline of a second metal line (56) of the third metal level; and forming a skip via (42, 44), wherein the skip via includes a first skip via segment having a first width and a second skip via segment having a second width, wherein the skip via connects the first metal line of the first metal level to the second metal line of the third metal level (see figure 1-10 and paragraphs [0021]-[0023], [0045]-[0047]).
[Re claim 17] Kuo discloses the method wherein forming the skip via includes: forming a first line opening in a third dielectric layer of the third metal level; forming a first skip via segment opening in a portion of the third dielectric layer below the first line opening; forming a second via segment opening in a second dielectric layer of the second metal level below the first skip via segment opening; and depositing at least one conductive metal material into and filling the first line opening, the first skip via segment opening, and the second skip via segment opening to form the second metal line of the third metal level, the fist skip via segment, and the second skip via segment (see figure 2-3, 9-10 and paragraph [0021]-[0023], [0045]-[0047]).
[Re claim 18] Kuo discloses the method wherein depositing the at least one conductive metal material into and filling the first line opening, the first skip via segment opening, and the second skip via segment opening includes: depositing a first conductive metal material into and filling the second skip via segment; and depositing a second conductive metal material into and filling the second skip via segment located above the first skip via segment (see figure 2-3, 9-10 and paragraph [0021]-[0023], [0045]-[0047]).
[Re claim 20] Kuo discloses the method wherein forming the second via segment opening in the second dielectric layer of the second metal level below the first skip via segment opening includes: etching the second dielectric layer (34) of the second metal level such that the first the first skip via segment opening and the second skip via segment opening have a first discontinuous continuous taper angle of a first side (right side wall) and a second discontinuous taper angle of a second side (left side wall) (see figure 2-3 and 9-10).
Claim(s) 1, 5-6, 8 and 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KANAYA et. al. (US Patent Appl. Pub. No. 2020/0083288 A1).
[Re claim 1] KANAYA discloses a semiconductor interconnect structure, comprising: a skip via, wherein the skip via includes a first skip via segment (801) vertically connected to a second skip via segment (810), wherein the first skip via segment has a first width and the second skip via segment has a second width (see figure 7-12 and paragraphs [0113]-[0123]).
[Re claim 5] KANAYA discloses the semiconductor interconnect structure wherein the first skip via segment (801) and the second skip via segment (810) are made from different conductive metal materials (see figure 14 and paragraph [0092], [0115], [0123]).
[Re claim 6] KANAYA discloses the semiconductor interconnect structure wherein the first skip via segment (801) and the second skip via segment (810) have a continuous taper angle of a first side (right side wall) and a discontinuous taper angle of a second side (left side wall) (see figure 11).
[Re claim 8] KANAYA discloses a semiconductor interconnect structure, comprising: a skip via (810); and a jumper (801), wherein the skip via is vertically connected to the jumper (see figure 7-12 and paragraphs [0113]-[0123]).
[Re claim 13] KANAYA discloses the semiconductor interconnect structure wherein the skip via and the jumper are made from different conductive metal materials (see figure 14 and paragraph [0092], [0115], [0123]).
[Re claim 14] KANAYA discloses the semiconductor interconnect structure wherein the skip via and the jumper have a continuous taper angle of a first side (right side wall) and a discontinuous taper angle of a second side (left side wall) (see figure 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et. al. (US Patent Appl. Pub. No. 2021/0391275 A1) in view of KANAYA et. al. (US Patent Appl. Pub. No. 2020/0083288 A1).
[Re claim 19] Kuo discloses the method as claimed and rejected in claim 16, Kuo does not disclose the method wherein etching the second dielectric layer of the second metal level such that the first the first skip via segment opening and the second skip via segment opening have a continuous taper angle of a first side and a discontinuous taper angle of a second side. KANAYA discloses the method wherein forming the second via segment opening (801) in the second dielectric layer (80 and 81) of the second metal level below the first skip via segment opening includes: etching the second dielectric layer (80 and 81) of the second metal level such that the first the first skip via segment opening (810) and the second skip via segment opening have a continuous taper angle of a first side (right side wall) and a discontinuous taper angle of a second side (left side wall) (see figure 7-11). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to form a continuous taper angle of a first side and a discontinuous taper angle of a second side in the method of Kuo in order to form a better electrically interconnecting structure.
Conclusion
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/KYOUNG LEE/ Primary Examiner, Art Unit 2817