Prosecution Insights
Last updated: July 26, 2026
Application No. 18/061,368

CIRCUIT DESIGN UPDATES USING REINFORCED LEARNING LOOP

Non-Final OA §102
Filed
Dec 02, 2022
Examiner
ALAM, MOHAMMED
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
780 granted / 846 resolved
+24.2% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
13 currently pending
Career history
857
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
17.6%
-22.4% vs TC avg
§102
77.1%
+37.1% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 846 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Non-Final Office Action DETAILED ACTION Examiner’s Notes (a) Claim date: 12/02/22. Claim Rejections - 35 USC 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-20, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “Shroff” <US 20130305202 A1>. (As to claim 1, 8, 15 Shroff discloses):1. A method comprising: receiving a circuit design and a specification for the circuit design [028: “integrated circuit design complies with a specification”]; determining a first hypothesized change to the circuit design based at least in part on the circuit design and the specification [0028: “changes to the integrated circuit design”, “integrated circuit design complies with a specification”; Note: claim limitation “hypothesized change to the circuit design” is interpreted as any changes to the circuit design.], wherein making the first hypothesized change to the circuit design produces a first changed circuit design [0034: “first instantiation of a device of the integrated circuit design”]; determining a first counterexample input that causes the first changed circuit design to produce an output that departs from the specification [0043: “they may fail to have similar enough electrical performance for a particular application”; note: claim limitation “departs from the specification” is interpreted as: design fail with respect to the specification. Also, the claim limitation “counterexample input” is interpreted as any input to the circuit design]; determining a second hypothesized change to the circuit design based at least in part on the first hypothesized change [0021: second instantiation of a particular device type”], wherein making the second hypothesized change to the circuit design produces a second changed circuit design [Fig. 11, 560 is the second hypothesized change]; and PNG media_image1.png 256 562 media_image1.png Greyscale in response to determining that the second changed circuit design has no counterexample input that causes the second changed circuit design to produce an output that departs from the specification, making the second hypothesized change to the circuit design [0043: “matching of devices contrasts with a design rule in that the design rule can ensure that a particular feature on each device meets common criteria and therefore that the devices meet a particular performance level within a defined range”; note: claim limitation “no counterexample input …departs from the specification” is interpreted as: “meets the specification”]. (As to claim 2, 9, 16, Shroff discloses):2. The method of Claim 1, wherein determining the first hypothesized change comprises determining input values for the circuit design that cause the circuit design to produce an output that departs from the specification [0043: “they may fail to have similar enough electrical performance for a particular application”; note: claim limitation “departs from the specification” is interpreted as: design fail with respect to the specification]. (As to claim 3,10, 17, Shroff discloses):3. The method of Claim 2, wherein determining the first hypothesized change further comprises transforming the input values to a Boolean representation [0027: “Boolean combinations”][0036: “comparator performs a logical exclusive-OR (XOR)”]. (As to claim 4, 11, 18, Shroff discloses):4. The method of Claim 3, wherein the Boolean representation of the input values comprises a Boolean formula [0027: “Boolean combinations”][0036: “comparator performs a logical exclusive-OR (XOR)”; note: XOR logic is part of a Boolean formula]. (As to claim 5, 12, 19, Shroff discloses):5. The method of Claim 3, wherein determining the first counterexample input comprises generating a binary decision diagram based on the Boolean representation of the input values. [Fig. 13, along with Para 56, refer to “decision block”] (As to claim 6, 13, 20 Shroff discloses):6. The method of Claim 1, wherein making the second hypothesized change comprises changing a connection to an input port of the circuit design [0002: “CAD system simulates the behavior of the device based on input stimuli”]. (As to claim 7, 14, Shroff discloses):7. The method of Claim 6, wherein the input port is specified prior to determining the first hypothesized change [Fig. 2, refer to the input port of 212 and 214 are being specified before any design change]. PNG media_image2.png 156 364 media_image2.png Greyscale Conclusion The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Dec 02, 2022
Application Filed
Jun 13, 2024
Response after Non-Final Action
Jan 12, 2026
Non-Final Rejection mailed — §102
Jul 21, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
98%
With Interview (+6.1%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 846 resolved cases by this examiner. Grant probability derived from career allowance rate.

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