DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
This Office Action is in response to Applicant’s application 18/061,374 filed on December 02 2022 in which claims 1 to 19 are pending.
Drawings
The drawings submitted on December 02 2022 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS), filed on December 2, 2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of (C:L) where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of (¶ XXXX).
Election/Restrictions
Applicant’s election without traverse of claims 1-19 in the reply filed on December 22 2025 is acknowledged. Claims 20-27 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0052116 A1; hereinafter “Lee”) in view of Song et al. (US 2020/0395409 A1; hereinafter “Song”).
Regarding claim 1, Lee teaches in figures 1-10B and related text e.g. a semiconductor device comprising:
a substrate (102; Fig.10A; ¶0053) including a peripheral circuit region (region formed to the left of the MCA including AP; Fig.4; any region in the figures 2-4 can be peripheral circuit region, however, for the purpose of examining the officer interprets peripheral region as shown below in the annotate figure 4) and a cell region (MCA; Fig.4; ¶ 0053) having a first cell region ( “S1”; left region of MCA; Fig.4) and a second cell region (“S2”;right region of MCA: Fig.4), the second cell region being farther from the peripheral circuit region than the first cell region (the second region (S2; annotated in the figure 4 below) is farther from the peripheral circuit (P1; annotated in figure 4 below) than the first region (S1 annotate in figure 4 below);
a plurality of first conductive lines (110, Fig.10; ¶0053) disposed over the substrate (102; Fig.; 10A) and extending in a first direction (X-direction);
a plurality of second conductive lines (170; Fig.10; ¶ 0059) disposed over the first conductive lines (110) and extending in a second direction (Y-axis; Fig.10A) that intersects the first direction (Y-axis and X-axis intersects); and
a plurality of memory cells (MC3; Fig.10A; ¶ 0103) disposed at intersection regions between the first conductive lines (110) and the second conductive lines (170), respectively, the memory cells including a first memory cell disposed in the first cell region (MC3 disposed in the first memory region of Figure 4 and 10A) and a second memory cell disposed in the second cell region (MC3 disposed in the second memory region of Figure 4 and 10A),
wherein a first electrode layer (BE31; ¶ 0102) of the first memory cell (MC3 of S1; Fig.4 and 10A) and a second electrode layer (BE32; ¶ 0102) of the second memory cell include a conductive material (MC3 of S2; Fig.4 and 10A).
Lee does not explicitly teach wherein the first electrode layer further includes a first dopant that increases a resistivity of the conductive material.
However, Song in the same field of endeavor (memory devices; Fig.4) teaches the first electrode layer (EL1; Fig.4; ¶ 0058) further includes a first dopant that increases a resistivity of the conductive material (dopant; Fig.4; ¶ 0059).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have the first electrode layer further includes a first dopant that increases a resistivity of the conductive material in the memory device of the Lee as taught by Song for the memory layer to have different resistance levels based on the program current (¶0067).
Regarding claim 2, Lee does not teach wherein the second electrode layer further includes the first dopant, and a content of the first dopant in the first electrode layer is greater than a content of the first dopant in the second electrode layer.
However, Song teaches wherein the second electrode layer (EL2; Fig.4; ¶ 0060) further includes the first dopant (dopant; ¶ 0060), and a content of the first dopant in the first electrode layer 9dopant of EL1; Fig.4; ¶ 006) is greater than a content of the first dopant in the second electrode layer (¶ 0060).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have the second electrode layer further includes the first dopant, and a content of the first dopant in the first electrode layer is greater than a content of the first dopant in the second electrode layer in the device of Lee as taught by Song for the aforementioned reasons.
Regarding claims 3 and 4, Lee does not teach wherein the conductive material includes amorphous carbon, and the first dopant includes nitrogen.
However, Song teaches wherein the conductive material includes amorphous carbon (¶ 0060), and the first dopant includes nitrogen (¶ 0126).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have the conductive material includes amorphous carbon, and the first dopant includes nitrogen in the device of Lee as taught by Song for the aforementioned reasons.
Regarding claim 5, Lee teaches wherein the first electrode layer (BE31; Fig10B) and the second electrode layer (BE32; Fig.10B) are positioned at the same level in a direction perpendicular to a surface of the substrate and have the same volume (BE31 and BE32 can be the same layer as shown in BE1; Fig.5A-B).
Regarding claim 6, Lee teaches wherein the first memory cell includes a variable resistance layer (140; Fig.10B; ¶0070), wherein the first electrode layer (BE31; Fig. 10B) of the first memory cell is positioned over or under the variable resistance layer (140, Fig. 10B), and wherein the second electrode layer (BE32; Fig.10B) of the second memory cell is positioned at the same level as the first electrode layer (BE31 and BE32 can be the same layer for example BE1 Figures 5A-B) in a direction perpendicular to a surface of the substrate (102).
Regarding claim 7, Lee teaches wherein the first memory cell includes a selector layer (124; Fig.10B; ¶ 0064) and a variable resistance layer (140; Fig.10B; ¶0070) stacked in a vertical direction perpendicular to a surface of the substrate (perpendicular to the 102; Fig.10B),
wherein the first electrode layer (BE31; Fig. 10B) of the first memory cell is positioned over the variable resistance layer (140, Fig. 10B), or under the selector layer (BE31 is place under 124; Fig.10B), or between the variable resistance layer and the selector layer, and
wherein the second electrode layer (BE32; Fig.10B) of the second memory cell is positioned at the same level as the first electrode layer in vertical direction (BE31 and BE32 can be the same layer for example BE1 Figures 5A-B).
Regarding claim 8, Lee teaches wherein the first memory cell includes a selector layer (124; Fig.10B; ¶ 0064) and a variable resistance layer (140; Fig.10B; ¶0070) stacked in a vertical direction perpendicular to a surface of the substrate (perpendicular to the 102; Fig.10B),
wherein the first electrode layer (BE31; Fig. 10B) of the first memory cell is positioned under the variable resistance layer (BE31 is positioned under 140, Fig. 10B), and wherein the second electrode layer (BE32; Fig.10B) of the second memory cell is positioned at the same level as the first electrode layer (BE31 and BE32 can be the same layer for example BE1 Figures 5A-B) in a direction perpendicular to a surface of the substrate (102).
Regarding claim 9, Lee teaches a resistance layer (140; Fig.10A) disposed between the first conductive line and one or more of the memory cells corresponding to the first conductive line, or between the second conductive line (110; Fig.10A) and one or more of the memory cells corresponding to the second conductive line (170; Fig.10A).
Regarding claim 10, Lee teaches the resistance layer includes a first resistance layer (140; Fig.10A) in the first cell region (MCA of S1) and a second resistance layer in the second cell region (140; Fig.10A; formed in MCA of S2), wherein the first resistance layer (140; Fig.10A) and the second resistance layer (140; Fig.10A) include a resistance material (¶ 0070), and wherein the first resistance layer (140; Fig.10A) further includes a second dopant (resistive layer 140 can include addition elements (dopants) B, C, N…: ¶ 0071).
that increases a resistivity of the resistance material
Lee does not explicitly state that the second dopant increasing a resistive of the resistance material.
However, Song in the same field of endeavor (memory devices; Fig.4) teaches the first electrode layer (EL1; Fig.4; ¶ 0058) further includes a first dopant that increases a resistivity of the conductive material (dopant; Fig.4; ¶ 0059).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to recognize that the dopants in the resistance material can increase resistivity of the resistance material in the memory device of the Lee as taught by Song since doing the memory layer reduces charger carrier mobility which can increase resistivity of the layer.
Regarding claim 11, Lee does not explicitly teach wherein the resistance material has the resistivity higher than a resistivity of a material for forming the first conductive line or the second conductive line.
However, Lee as modified by Song teaches the first and second resistance layer (140; Fig.10A) can have a dopant) with a doped layer can have increased resistance (¶ 0060).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have the resistance material has the resistivity higher than a resistivity of a material for forming the first conductive line or the second conductive line in the device of Lee as taught by Song since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice MPEP § 2144.07.
Regarding claim 12, Lee teaches wherein the resistance material includes tungsten silicon nitride, and wherein the second dopant includes one or both of silicon and nitrogen (¶ 0070-0071).
(Furthermore, the following reference Lim et al. (US 2007/0166870 A1) teaches a chalcogenide layer that can formed from tungsten silicon nitride; ¶ 0096).
Regarding claim 13, Lee teaches wherein the resistance layer (140 in MC1; Fig.4) has a line shape overlapping the first conductive line (110; Fig.4) and disposed between the first conductive line (110) and the corresponding memory cells (MC1).
Regarding claim 14, Lee wherein the resistance layer (140 formed in MC1; Fig.4) has a line shape overlapping the second conductive line (170) and disposed between the second conductive line (170) and the corresponding memory cells (MC1).
Regarding claim 15, Lee teaches in figures 1-10B and related text e.g. a semiconductor device comprising:
a substrate (102; Fig.10A; ¶0053) including a peripheral circuit region (region formed to the left of the MCA including AP; Fig.4; any region in the figures 2-4 can be peripheral circuit region, however, for the purpose of examining the officer interprets peripheral region as shown below in the annotate figure 4) and a cell region (MCA; Fig.4; ¶ 0053) having a first cell region ( “S1”; left region of MCA; Fig.4) and a second cell region (“S2”;right region of MCA: Fig.4), the second cell region being farther from the peripheral circuit region than the first cell region (the second region (S2; annotated in the figure 4 below) is farther from the peripheral circuit (P1; annotated in figure 4 below) than the first region (S1 annotate in figure 4 below);
a plurality of first conductive lines (110, Fig.10; ¶0053) disposed over the substrate (102; Fig.; 10A) and extending in a first direction (X-direction);
a plurality of second conductive lines (170; Fig.10; ¶ 0059) disposed over the first conductive lines (110) and extending in a second direction (Y-axis; Fig.10A) that intersects the first direction (Y-axis and X-axis intersects); and
a plurality of memory cells (MC3; Fig.10A; ¶ 0103) disposed at intersection regions between the first conductive lines (110) and the second conductive lines (170), respectively, the memory cells including a first memory cell disposed in the first cell region (MC3 disposed in the first memory region of Figure 4 and 10A) and a second memory cell disposed in the second cell region (MC3 disposed in the second memory region of Figure 4 and 10A), and
a resistance layer (140; Fig.10A; ¶ 0063) disposed between the first conductive line and one or more of the memory cells corresponding to the first conductive line, or between the second conductive line (110; Fig.10A) and one or more of the memory cells corresponding to the second conductive line (170; Fig.10A),
wherein the resistance layer includes a first resistance layer (140; Fig.10A) disposed in the first cell region (MCA of S1) and a second resistance layer in the second cell region (140; Fig.10A; formed in MCA of S2), wherein the first resistance layer (140; Fig.10A) and the second resistance layer (140; Fig.10A) include a resistance material (¶ 0070), and wherein the first resistance layer (140; Fig.10A) further includes a second dopant (resistive layer 140 can include addition elements (dopants) B, C, N…: ¶ 0071).
Lee does not explicitly state that the second dopant increasing a resistive of the resistance material.
However, Song in the same field of endeavor (memory devices; Fig.4) teaches the first electrode layer (EL1; Fig.4; ¶ 0058) further includes a first dopant that increases a resistivity of the conductive material (dopant; Fig.4; ¶ 0059).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to recognize that the dopants in the resistance material can increase resistivity of the resistance material in the memory device of the Lee as taught by Song since doing the memory layer reduces charger carrier mobility which can increase resistivity of the layer.
Regarding claim 16, Lee does not explicitly teach wherein the resistance material has the resistivity higher than a resistivity of a material for forming the first conductive line or the second conductive line.
However, Lee as modified by Song teaches the first and second resistance layer (140; Fig.10A) can have a dopant) with a doped layer can have increased resistance (¶ 0060).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have the resistance material has the resistivity higher than a resistivity of a material for forming the first conductive line or the second conductive line in the device of Lee as taught by Song since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice MPEP § 2144.07.
Regarding claim 17, Lee teaches wherein the resistance material includes tungsten silicon nitride, and wherein the second dopant includes one or both of silicon and nitrogen (¶ 0070-0071).
(Furthermore, the following reference Lim et al. (US 2007/0166870 A1) teaches a chalcogenide layer that can formed from tungsten silicon nitride; ¶ 0096).
Regarding claim 18, Lee teaches wherein the resistance layer (140 in MC1; Fig.4) has a line shape overlapping the first conductive line (110; Fig.4) and disposed between the first conductive line (110) and the corresponding memory cells (MC1).
Regarding claim 19, Lee wherein the resistance layer (140 formed in MC1; Fig.4) has a line shape overlapping the second conductive line (170) and disposed between the second conductive line (170) and the corresponding memory cells (MC1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mounir S Amer whose telephone number is (571)270-3683. The examiner can normally be reached Monday-Friday 9:00-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mounir S Amer/ Primary Examiner, Art Unit 2818