DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 26, 2026 has been entered.
Response to Amendment
The amendment filed January 26, 2026 has been entered. Claims 1-30 remain pending in the application.
Response to Arguments
Applicant's arguments filed January 26, 2026 have been fully considered but they are not persuasive. Applicant argues, see pages 11-12, that previously presented prior art reference Behzad et al. (Patent Number US 8,093,952 B2), hereafter referred to as Behzad, fails to disclose a diode-connected transistors. Examiner respectfully disagrees.
First, applicant argues that the Final Office Action inappropriately maps the claimed first and second transistors to the circuit of Behzad, with transistor 504 of Behzad, Fig. 5 inappropriately being mapped to the claimed second transistor, and that therefore the lack of a diode-connection of transistor 520 of Behzad, Fig. 5 results in the invalidity of the previous rejection. Examiner respectfully disagrees.
Applicant states that “the second transistor having a gate electrode connected to the gate electrode of the first transistor via the low-pass filter circuit” requires the claimed second transistor to correspond to transistor 520 of Behzad, Fig. 5. However, the connection of the two transistors via the low-pass filter circuit does not confer any differences between the two transistors. If the second transistor is connected to the first transistor via the low-pass filter circuit, then the first transistor is also connected to the second transistor via the low-pass filter circuit. There is no specific directionality regarding the two transistors that this limitation requires. In other words, this limitation does not distinguish between the first transistor and the second transistor, and therefore cannot be used to determine which one is mapped to in Behzad. Therefore, the mapping of the claimed first transistor to transistor 520 of Behzad, Fig. 5, and the mapping of the claimed second transistor to transistor 504 of Behzad, Fig. 5 is appropriate.
Second, applicant argues that claim 3 further requires the claimed first transistor to be diode-connected, and that therefore the lack of a diode-connection of transistor 520 of Behzad, Fig. 5, regardless of the interpretation of Behzad results in the invalidity of the previous rejection.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the first transistor having a diode-connection) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Similar to the discussion above, the limitations of claim 3 do not distinguish between the first transistor and the second transistor. Claim 3 recites “a capacitor connected between the gate electrode of the second transistor”. This limitation does not require the capacitor to be directly connected to the gate electrode of the second transistor, and therefore, the indirect connection of capacitor 516 to transistor 504 in Behzad, Fig. 5 does provide this limitation in the prior art. Therefore, all of applicant’s arguments are unconvincing and the rejections of claims 1-14 and 22-30 are maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-24, 26, and 28-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "a diode-connected transistor" in lines 8 and 21. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “a first diode-connected transistor” (on line 8) and “a second diode-connected transistor” (on line 21) is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 12-24, 26, and 28-30 are likewise rejected under this logic by virtue of their dependencies on claim 11.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Behzad in view of Kudo (Patent Publication Number US 2009/0160420 A1), hereafter referred to as Kudo.
Regarding claim 1, Behzad discloses:
An amplifier circuit (Behzad, Fig. 5) including: a first circuit (Fig. 5, 504) including a first transistor (Fig. 5, 520) connected between an input node (Fig. 5, Vdd) through which an input current flows (Fig. 5, I1) and a reference potential node (Fig. 5, see connection between 520 and ground), the first transistor having a gate electrode connected to the input node (Fig. 5, see connection between gate of 520 and Vdd via 514 and 502); a second circuit (Fig. 5, 504, 514, and 516) including a low-pass filter circuit (Fig. 5, 514 and 516) and a second transistor (Fig. 5, 504) connected in parallel to the first transistor between the input node and the reference potential node (Fig. 5, see connection between Vdd and ground via 504), the second transistor having a gate electrode connected to the gate electrode of the first transistor via the low- pass filter circuit (Fig. 5, see connection between gate of 504 and gate of 520 via resistor 514) and being a diode-connected transistor such that the gate electrode is connected to a drain electrode of the second transistor (Fig. 5, see connection between gate and drain of 504); and a third circuit (Fig. 5, 524) including a third transistor (Fig. 5, 524) connected between an output node (Fig. 5, 522) through which an output current flows (Fig. 5, I2) and the reference potential node (Fig. 5, see connection between 524 and ground), the third circuit having a gate electrode connected to the gate electrode of the first transistor (Fig. 5, see connection between gate of 524 and gate of 520), but fails to disclose the input current being an alternating current signal, a current value of the alternating current signal varying on a periodic basis at a determined frequency.
However, Kudo teaches the input current being an alternating current signal (Kudo, Paragraph 49, lines 1-3, consider that the input current at node 1 in Fig. 2 has a frequency that determines the gain of the current mirror amplifier of Fig. 2, as shown in Figs. 3-4), a current value of the alternating current signal varying on a periodic basis at a determined frequency (Paragraph 49, lines 1-3, consider that the input current at node 1 in Fig. 2 has a frequency that determines the gain of the current mirror amplifier of Fig. 2, as shown in Figs. 3-4).
Behzad and Kudo are both considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Behzad to incorporate the teachings of Kudo to include an AC input current in the amplifier of Behzad, which would have the effect of enabling the amplifier of Behzad to amplify an AC signal (Paragraph 49, lines 1-3).
Regarding claim 2, Behzad further discloses:
wherein the first circuit and the second circuit constitute a current mirror circuit with the third circuit (Behzad, Col. 8, lines 40-47).
Regarding claim 3, Behzad further discloses:
wherein the low-pass filter circuit includes: a capacitor (Behzad, Fig. 5, 516) connected between the gate electrode of the second transistor (Fig. 5, see connection between 516 and gate of 504) and the reference potential node (Fig. 5, see connection between 516 and ground); and a resistor (Fig. 5, 514) connected between the gate electrode of the second transistor (Fig. 5, see connection between 514 and gate of 504) and the gate electrode of the first transistor (Fig. 5, see connection between 514 and gate of 520).
Regarding claim 7, Behzad further discloses:
comprising a current source (Behzad, Fig. 5, 528) connected in parallel to the first transistor and the second transistor between the input node and the reference potential node (Fig. 5, see connection between Vdd and ground via 528).
Regarding claim 8, Behzad further discloses:
wherein a gain of the amplifier circuit in a case where a frequency of the input current is lower than a cutoff frequency of the low-pass filter circuit is determined according to a size of the current source (Behzad, Col. 8, lines 35-39 [size of current source 528 determines bias voltage for amplifier 512, which improves performance of amplifier system]).
Regarding claim 9, Behzad further discloses:
wherein a gain of the amplifier circuit in a case where a frequency of the input current is higher than a cutoff frequency of the low-pass filter circuit is larger than a gain of the amplifier circuit in a case where the frequency of the input current is lower than the cutoff frequency of the low-pass filter circuit (Behzad, Col. 8, lines 48-51 [low-pass filter improves signal quality by removing noise]).
Regarding claim 10, Behzad further discloses:
wherein a difference in gain of the amplifier circuit between a case where the frequency of the input current is higher than the cutoff frequency of the low-pass filter circuit and a case where the frequency of the input current is lower than the cutoff frequency of the low-pass filter circuit is determined according to a size of the second transistor (Behzad, Col. 8, lines 22-39 [transistor 504 helps to improve signal quality, so size will influence improvement in signal quality]).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Behzad in view of Kudo as applied to claim 1 above, and further in view of Van Acht et al. (Patent Publication Number CN 1,947,200 A), hereafter referred to as Van Acht.
Regarding claim 4, Behzad fails to disclose:
wherein a size of the third transistor is equal to a sum of a size of the first transistor and a size of the second transistor.
However, Van Acht teaches wherein a size of the third transistor is equal to a sum of a size of the first transistor and a size of the second transistor (Van Acht, Page 5, Paragraph 4, lines 1-7, consider Fig. 3, where transistor 30 is the third transistor, and transistors 32 are the first and second transistors).
Behzad, Kudo, and Van Acht are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Behzad to incorporate the teachings of Van Acht to make the output transistor of Behzad have size equivalent to the combined sizes of the input transistors of Behzad, which would have the effect of combining the input currents of Behzad (Van Acht, Page 5, Paragraph 4, lines 1-10).
Regarding claim 5, Behzad further discloses:
wherein each of the first transistor, the second transistor, and the third transistor is a planar transistor (Behzad, Fig. 5, see that 520, 504, and 524 are all MOSFET transistors), and the sizes correspond to gate widths of the planar transistors (Col. 7, lines 48-49).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Behzad in view of Kudo and Van Acht as applied to claim 4 above, and further in view of Zhang et al. (Patent Publication Number CN 106,505,995 A), hereafter referred to as Zhang.
Regarding claim 6, Behzad and Van Acht fail to disclose:
wherein each of the first transistor, the second transistor, and the third transistor is a FinFET, and the sizes correspond to the numbers of fins of the FinFETs.
However, Zhang teaches wherein each of the first transistor, the second transistor, and the third transistor is a FinFET (Zhang, Fig. 3A, see amplifier comprised of FinFET transistors), and the sizes correspond to the numbers of fins of the FinFETs (Page 2, Paragraph 1, lines 4-7).
Behzad, Kudo, Van Acht, and Zhang are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Behzad to incorporate the teachings of Zhang to use FinFET transistors to implement the transistors of Behzad, which would have the effect of reducing non-linear distortions in the amplifier of Behzad (Zhang, Page 2, Paragraph 1, lines 7-11).
Claims 11-13, 22-24, 26, 28, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Nagamatsu et al. (Patent Number US 5,764,086 A), as cited by applicant, hereafter referred to as Nagamatsu, in view of Behzad.
Regarding claim 11, Nagamatsu discloses:
A differential amplifier circuit (Nagamatsu, Fig. 1) including: a first circuit (Fig. 1, N1) including a first transistor (Fig. 1, N1) connected between a first input node (Fig. 1, S1) through which a first input current flows (Fig. 1, see connection between N1 and S1) and a reference potential node (Fig. 1, see connection between N1 and ground), the first transistor having a gate electrode connected to the first input node (Fig. 4, see connection between gate of N1 and S1); a third circuit (Fig. 1, N5) including a third transistor (Fig. 1, N5) connected between a first output node (Fig. 1, see node at P4) through which a first output current flows (Fig. 1, see connection between N5 and P4) and the reference potential node (Fig. 1, see connection between N5 and ground), the third transistor having a gate electrode connected to the gate electrode of the first transistor (Fig. 1, see connection between gate of N5 and gate of N1); a fourth circuit (Fig. 1, N4) including a fourth transistor (Fig. 1, N4) connected between a second input node (Fig. 1, S2) through which a second input current flows (Fig. 1, see connection between N4 and S2) and the reference potential node (Fig. 1, see connection between N4 and ground), the fourth transistor having a gate electrode connected to the second input node (Fig. 1, see connection between gate of N4 and S2); a sixth circuit (Fig. 1, N6) including a sixth transistor (Fig. 1, N6) connected between a second output node (Fig. 1, S5) through which a second output current flows (Fig. 1, see connection between N6 and S5) and the reference potential node (Fig. 1, see connection between N6 and ground), the sixth transistor having a gate electrode connected to the gate electrode of the fourth transistor (Fig. 1, see connection between N6 and N4); a seventh circuit (Fig. 1, N2) including a seventh transistor (Fig. 1, N2) connected between the second input node (Fig. 1, see connection between N2 and S2) and the reference potential node (Fig. 1, see connection between N2 and ground), the seventh transistor having a gate electrode connected to the gate electrode of the first transistor (Fig. 1, see connection between gate of N2 and gate of N1); and an eighth circuit (Fig. 1, N3) including an eighth transistor (Fig. 1, N3) connected between the first input node (Fig. 1, see connection between N3 and S1) and the reference potential node (Fig. 1, see connection between N3 and ground), the eighth transistor having a gate electrode connected to the gate electrode of the fourth transistor (Fig. 1, see connection between gate of N3 and gate of N4), but fails to disclose a second circuit including a first low-pass filter circuit and a second transistor connected in parallel to the first transistor between the first input node and the reference potential node, the second transistor having a gate electrode connected to the gate electrode of the first transistor via the first low-pass filter circuit and being a diode-connected transistor such that the gate electrode is connected to a drain electrode of the second transistor, the first input current being an alternating current signal, a current value of the alternating current signal of the first input current varying on a periodic basis at a determined frequency; a fifth circuit including a second low-pass filter circuit and a fifth transistor connected in parallel to the fourth transistor between the second input node and the reference potential node, the fifth transistor having a gate electrode connected to the gate electrode of the fourth transistor via the second low-pass filter circuit and being a diode-connected transistor such that the gate electrode is connected to a drain electrode of the fifth transistor, the second input current being an alternating current signal, a current value of the alternating current signal of the second input current varying on a periodic basis at a determined frequency.
However, Behzad teaches a second circuit (Behzad, Fig. 5, Elements 504, 514, and 516) including a first low-pass filter circuit (Fig. 5, 514 and 516) and a second transistor (Fig. 5, 504) connected in parallel to the first transistor between the first input node and the reference potential node (Fig. 5, see that 504 and 520 are both in parallel between Vdd and ground), the second transistor having a gate electrode connected to the gate electrode of the first transistor via the first low-pass filter circuit (Fig. 5, see connection between gate of 504 and gate of 520 via 514/516) and being a diode-connected transistor such that the gate electrode is connected to a drain electrode of the second transistor (Fig. 5, see connection between gate and drain of 504), a fifth circuit (Fig. 5, Elements 504, 514, and 516) including a second low-pass filter circuit (Fig. 5, 514 and 516) and a fifth transistor (Fig. 5, 504) connected in parallel to the fourth transistor between the second input node and the reference potential node (Fig. 5, see that 504 and 520 are both in parallel between Vdd and ground), the fifth transistor having a gate electrode connected to the gate electrode of the fourth transistor via the second low-pass filter circuit (Fig. 5, see connection between gate of 504 and gate of 520 via 514/516) and being a diode-connected transistor such that the gate electrode is connected to a drain electrode of the fifth transistor (Fig. 5, see connection between gate and drain of 504), but fails to teach the first input current being an alternating current signal, a current value of the alternating current signal of the first input current varying on a periodic basis at a determined frequency; the second input current being an alternating current signal, a current value of the alternating current signal of the second input current varying on a periodic basis at a determined frequency.
However, Kudo teaches the first input current being an alternating current signal (Kudo, Paragraph 49, lines 1-3, consider that the input current at node 1 in Fig. 2 has a frequency that determines the gain of the current mirror amplifier of Fig. 2, as shown in Figs. 3-4), a current value of the alternating current signal of the first input current varying on a periodic basis at a determined frequency (Paragraph 49, lines 1-3, consider that the input current at node 1 in Fig. 2 has a frequency that determines the gain of the current mirror amplifier of Fig. 2, as shown in Figs. 3-4); the second input current being an alternating current signal (Paragraph 49, lines 1-3, consider that the input current at node 1 in Fig. 2 has a frequency that determines the gain of the current mirror amplifier of Fig. 2, as shown in Figs. 3-4), a current value of the alternating current signal of the second input current varying on a periodic basis at a determined frequency (Paragraph 49, lines 1-3, consider that the input current at node 1 in Fig. 2 has a frequency that determines the gain of the current mirror amplifier of Fig. 2, as shown in Figs. 3-4).
Nagamatsu, Behzad, and Kudo are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Nagamatsu to incorporate the teachings of Behzad and Kudo to include the transistor and low-pass filter circuit of Behzad in the amplifier of Nagamatsu, which would have the effect of reducing unwanted signal noise (Behzad, Col. 2, lines 24-27) and to include an AC input current in the amplifier of Nagamatsu, which would have the effect of enabling the amplifier of Nagamatsu to amplify an AC signal (Paragraph 49, lines 1-3).
Regarding claim 12, Nagamatsu in view of Behzad and Nagamatsu further discloses:
wherein the first circuit, the second circuit, and the seventh circuit constitute a first current mirror circuit with the third circuit (Nagamatsu, Fig. 1, see current mirror formed by gate coupled transistors N1, N2, and N5 [with transistor 504 of Fig. 5 of Behzad added]), and the fourth circuit, the fifth circuit, and the eighth circuit constitute a second current mirror circuit with the sixth circuit (Fig. 1, see current mirror formed by gate coupled transistors N3, N4, and N6 [with transistor 504 of Fig. 5 of Behzad added]).
Regarding claim 13, Nagamatsu fails to disclose:
wherein the first low-pass filter circuit includes: a first capacitor connected between the gate electrode of the second transistor and the reference potential node; and a first resistor connected between the gate electrode of the second transistor and the gate electrode of the first transistor, and the second low-pass filter circuit includes: a second capacitor connected between the gate electrode of the fifth transistor and the reference potential node; and a second resistor connected between the gate electrode of the fifth transistor and the gate electrode of the fourth transistor.
However, Behzad further teaches wherein the first low-pass filter circuit includes: a first capacitor (Behzad, Fig. 5, 516) connected between the gate electrode of the second transistor (Fig. 5, see connection between 516 and gate of 504) and the reference potential node (Fig. 5, see connection between 516 and ground); and a first resistor (Fig. 5, 514) connected between the gate electrode of the second transistor and the gate electrode of the first transistor (Fig. 5, see connection between gate of 504 and gate of 520 via resistor 514), and the second low-pass filter circuit includes: a second capacitor (Fig. 5, 516) connected between the gate electrode of the fifth transistor (Fig. 5, see connection between 516 and gate of 504) and the reference potential node (Fig. 5, see connection between 516 and ground); and a second resistor (Fig. 5, 514) connected between the gate electrode of the fifth transistor and the gate electrode of the fourth transistor (Fig. 5, see connection between gate of 504 and gate of 520 via resistor 514).
Nagamatsu, Behzad, and Kudo are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Nagamatsu to incorporate the teachings of Behzad to include the transistor and low-pass filter circuit of Behzad in the amplifier of Nagamatsu, which would have the effect of reducing unwanted signal noise (Behzad, Col. 2, lines 24-27).
Regarding claim 22, Nagamatsu fails to disclose:
wherein a gain of the differential amplifier circuit in a case where frequencies of the first input current and the second input current are higher than cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit is larger than a gain of the differential amplifier circuit in a case where the frequencies of the first input current and the second input current are lower than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit.
However, Behzad further teaches wherein a gain of the differential amplifier circuit in a case where frequencies of the first input current and the second input current are higher than cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit is larger than a gain of the differential amplifier circuit in a case where the frequencies of the first input current and the second input current are lower than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit (Behzad, Col. 8, lines 48-51 [low-pass filter improves signal quality by removing noise]).
Nagamatsu, Behzad, and Kudo are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Nagamatsu to incorporate the teachings of Behzad to include the transistor and low-pass filter circuit of Behzad in the amplifier of Nagamatsu, which would have the effect of reducing unwanted signal noise (Behzad, Col. 2, lines 24-27).
Regarding claim 23, Nagamatsu fails to disclose:
further including: a first current source connected in parallel to the first transistor and the second transistor between the first input node and the reference potential node; and a second current source connected in parallel to the fourth transistor and the fifth transistor between the second input node and the reference potential node.
However, Behzad further teaches further including: a first current source (Behzad, Fig. 5, 528) connected in parallel to the first transistor and the second transistor between the first input node and the reference potential node (Fig. 5, see connection between Vdd and ground via 528); and a second current source (Fig. 5, 528) connected in parallel to the fourth transistor and the fifth transistor between the second input node and the reference potential node (Fig. 5, see connection between Vdd and ground via 528).
Nagamatsu, Behzad, and Kudo are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Nagamatsu to incorporate the teachings of Behzad to include the current source of Behzad in the amplifier of Nagamatsu, which would have the effect of improving stability of the amplifier of Nagamatsu (Behzad, Col. 8, lines 35-39).
Regarding claim 24, Nagamatsu fails to disclose:
wherein a gain of the differential amplifier circuit in a case where a frequency of the first input current is lower than a cutoff frequency of the first low-pass filter and a frequency of the second input current is lower than a cutoff frequency of the second low-pass filter
However, Behzad further teaches wherein a gain of the differential amplifier circuit in a case where a frequency of the first input current is lower than a cutoff frequency of the first low-pass filter (Behzad, Col. 8, lines 35-39 [size of current source 528 determines bias voltage for amplifier 512, which improves performance of amplifier system]) and a frequency of the second input current is lower than a cutoff frequency of the second low-pass filter (Col. 8, lines 35-39 [size of current source 528 determines bias voltage for amplifier 512, which improves performance of amplifier system]).
Nagamatsu, Behzad, and Kudo are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Nagamatsu to incorporate the teachings of Behzad to include the current source of Behzad in the amplifier of Nagamatsu, which would have the effect of improving stability of the amplifier of Nagamatsu (Behzad, Col. 8, lines 35-39).
Regarding claim 26, Nagamatsu further discloses:
A differential amplifier circuit (Nagamatsu, Fig. 1) obtained by connecting the differential amplifier circuits according to claim 11 in multiple stages (Fig. 1, see that C1 forms a first amplifier stage, and that C2 forms a second amplifier stage in parallel with C1).
Regarding claim 28, Nagamatsu further discloses:
A reception circuit (Nagamatsu, Fig. 1) including: an input circuit (Fig. 1, C1 and C2) that receives an input signal (Fig. 1, IN+ and IN-) and performs equalization processing on the input signal (Col. 9, line 61-Col. 10, line 5), the input circuit including the differential amplifier circuit according to claim 11 (see above); and a conversion circuit (Fig. 1, 4-7) that performs predetermined conversion processing on an output signal of the input circuit (Col. 10, lines 6-15).
Regarding claim 30, Nagamatsu further discloses:
A semiconductor integrated circuit (Nagamatsu, Fig. 1) including: the reception circuit according to claim 28 (see above); and a processing circuit (Fig. 1, 4-7) that performs predetermined signal processing on an output signal of the reception circuit (Col. 10, lines 6-15).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nagamatsu in view of Behzad and Kudo as applied to claim 11 above, and further in view of Van Acht.
Regarding claim 14, Nagamatsu, Behzad, and Kudo fail to disclose:
wherein a size of the third transistor is equal to a sum of a size of the first transistor, a size of the second transistor, and a size of the seventh transistor, and a size of the sixth transistor is equal to a sum of a size of the fourth transistor, a size of the fifth transistor, and a size of the eighth transistor.
However, Van Acht teaches wherein a size of the third transistor is equal to a sum of a size of the first transistor, a size of the second transistor, and a size of the seventh transistor (Van Acht, Page 5, Paragraph 4, lines 1-7, consider Fig. 3, where transistor 30 is the third transistor, and transistors 32 are the first, second, and seventh transistors), and a size of the sixth transistor is equal to a sum of a size of the fourth transistor, a size of the fifth transistor, and a size of the eighth transistor (Van Acht, Page 5, Paragraph 4, lines 1-7, consider Fig. 3, where transistor 30 is the sixth transistor, and transistors 32 are the fourth, fifth, and eighth transistors).
Nagamatsu, Behzad, Kudo, and Van Acht are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Nagamatsu to incorporate the teachings of Van Acht to make the output transistors of Nagamatsu have size equivalent to the combined sizes of the input transistors of Nagamatsu, which would have the effect of combining the input currents of Nagamatsu (Van Acht, Page 5, Paragraph 4, lines 1-10).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Behzad in view of Kudo as applied to claim 1 above, and further in view of Chen (Patent Number US 6,995,612 B1), hereafter referred to as Chen.
Regarding claim 25, Behzad fails to disclose:
An amplifier circuit obtained by connecting the amplifier circuits according to claim 1 in multiple stages.
However, Chen teaches an amplifier circuit obtained by connecting the amplifier circuits according to claim 1 in multiple stages (Chen, Fig. 2, see M1-M3 forming a first stage amplifier, and M4-M6 forming a second stage amplifier).
Behzad, Kudo, and Chen are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Behzad to incorporate the teachings of Chen to include multiple stages of the amplifier of Behzad, which would have the effect of reducing leakage current (Chen, Col. 3, lines 25-32).
Claims 27 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Behzad in view of Kudo as applied to claim 1 above, and further in view of Nagamatsu.
Regarding claim 27, Behzad further discloses:
A reception circuit (Behzad, Fig. 5) including: the input circuit including the amplifier circuit according to claim 1 (see above); but fails to disclose an input circuit that receives an input signal and performs equalization processing on the input signal, and a conversion circuit that performs predetermined conversion processing on an output signal of the input circuit.
However, Nagamatsu teaches an input circuit that receives an input signal (Nagamatsu, Fig. 1) and performs equalization processing on the input signal (Col. 9, line 61-Col. 10, line 5), and a conversion circuit (Fig. 1, 4-7) that performs predetermined conversion processing on an output signal of the input circuit (Col. 10, lines 6-15).
Behzad, Kudo, and Nagamatsu are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Behzad to incorporate the teachings of Nagamatsu to include the equalization and conversion processing components of Nagamatsu in the amplifier of Behzad, which would have the effect of processing the output signal of the amplifier of Behzad for outside use.
Regarding claim 29, Behzad fails to disclose:
A semiconductor integrated circuit including: the reception circuit according to claim 27; and a processing circuit that performs predetermined signal processing on an output signal of the reception circuit.
However, Nagamatsu further teaches a semiconductor integrated circuit (Nagamatsu, Fig. 1) including: the reception circuit according to claim 27 (see above); and a processing circuit (Fig. 1, 4-7) that performs predetermined signal processing on an output signal of the reception circuit (Col. 10, lines 6-15).
Behzad, Kudo, and Nagamatsu are all considered to be analogous to the claimed invention because they are in the same field of improving current mirror based amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Behzad to incorporate the teachings of Nagamatsu to include the processing components of Nagamatsu in the amplifier of Behzad, which would have the effect of processing the output signal of the amplifier of Behzad for outside use.
Allowable Subject Matter
Claims 15-21 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art, when taken alone, or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the Applicant.
The closest prior arts are Nagamatsu, Behzad, and Kudo (see rejection of claim 11 above). However, Nagamatsu, Behzad, and Kudo fail to disclose the limitations of claim 15, which describe an implementation of individual transistor activation control for the differential amplifier of claim 11, the limitations which are given in the claim as follows: “ wherein the second circuit includes a tenth transistor connected between the second transistor and the reference potential node, an eleventh transistor connected in parallel to the second transistor between the first input node and the reference potential node, the eleventh transistor having a gate electrode connected to the gate electrode of the first transistor without via the first low-pass filter circuit, a twelfth transistor connected between the eleventh transistor and the reference potential node, and a first inverter in which one of an input side thereof and an output side thereof is connected to a gate electrode of the tenth transistor and in which the other of the input side and the output side is connected to a gate electrode of the twelfth transistor, the first inverter being configured to selectively turn on one of the tenth transistor and the twelfth transistor according to a first control signal to be input thereto, the seventh circuit includes a thirteenth transistor connected between the seventh transistor and the reference potential node, a fourteenth transistor connected in parallel to the seventh transistor between the first input node and the reference potential node, the fourteenth transistor having a gate electrode connected to the gate of the first transistor, a fifteenth transistor connected between the fourteenth transistor and the reference potential node, and a second inverter in which one of an input side thereof and an output side thereof is connected to a gate electrode of the fifteenth transistor and in which the other of the input side and the output side is connected to a gate electrode of the thirteenth transistor, the second inverter being configured to selectively turn on one of the thirteenth transistor and the fifteenth transistor according to a second control signal to be input thereto, the fifth circuit includes an eighteenth transistor connected between the fifth transistor and the reference potential node, a nineteenth transistor connected in parallel to the fifth transistor between the second input node and the reference potential node, the nineteenth transistor having a gate electrode connected to the gate of the fourth transistor without via the second low-pass filter circuit, a twentieth transistor connected between the nineteenth transistor and the reference potential node, and a third inverter in which one of an input side thereof and an output side thereof is connected to a gate electrode of the eighteenth transistor and in which the other of the input side and the output side is connected to a gate electrode of the twentieth transistor, the third inverter being configured to selectively turn on one of the eighteenth transistor and the twentieth transistor according to a third input control signal, and the eighth circuit includes a twenty-first transistor connected between the eighth transistor and the reference potential node, a twenty-second transistor connected in parallel to the eighth transistor between the second input node and the reference potential node, the twenty-second transistor having a gate electrode connected to the gate of the fourth transistor, a twenty-third transistor connected between the twenty-second transistor and the reference potential node, and a fourth inverter in which one of an input side thereof and an output side thereof is connected to a gate electrode of the twenty-third transistor and in which the other of the input side and the output side is connected to a gate electrode of the twenty-first transistor, the fourth inverter being configured to selectively turn on one of the twenty-first transistor and the twenty-third transistor according to a fourth control signal to be input thereto.” Therefore, Nagamatsu, Behzad, and Kudo are not suitable for the application as claimed in claims 15-21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ma et al. (Patent Number CN 201,042,006 Y) discloses controlling amplifier gain by varying transistor sizes.
Quan et al. (Patent Number US 7,724,092 B2) discloses (Fig. 5) a current mirror amplifier with an AC input signal.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843