DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 2-6, 17-18, and 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 11, 16, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Horst (US 5317726) (hereinafter Horst) in view of Schoenfeldt et al (US 2013/0304958) (hereinafter Schoenfeldt) further in view of Tsirkin (US 2021/0342260) (hereinafter Tsirkin).
As per claim 1, Horst teaches:
One or more machine readable media including instructions stored therein, wherein the instructions, when executed by a first processor, cause the first processor to:
assign a first tag to a plurality of granules in a first portion of memory allocated for a function (Horst, col 17, ll 21-23— under BRI, a 1st potion of mem can be i-cache) ;
wherein the function is an offloaded function invoked by a module running on a second processor (Hors, col 7, ll17-19— under BRI, an offloaded function can be access to disk memory);
Horst does not expressly teach:
subsequent to an exception being raised for a tag check failure of a memory access operation in the first portion of the memory, update a modified address list to include information associated with a first memory address; and
synchronize, based on the modified address list, a second portion of the memory allocated to the module with the first portion of the memory;
However, Schoenfeldt discloses:
subsequent to an exception being raised for an error, update a modified address list to include information associated with a first memory address (Schoenfeldt, [0078]—under BRI, update a modified address list to include information associated with a first memory address can be he configurable bus 310 may change the memory map of the system 100 so as to disable access to protected address ranges of the system) ; and
wherein the error is for a tag check failure of a memory access operation in the first portion of the memory (Schoenfeldt, [0050]—under BRI, a tag check failure of a memory access operation in the first portion of the memory can be a bus error generated because of access to an address range requiring privileged access)
Both Schoenfeldt and Horst pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Schoenfeldt’s method to update address list because it is well-known in the art that cache coherence protocols use updated tag to manage shared data, ensuring that when another processor requests data, a "dirty" copy is updated in memory or transferred, preventing stale data reads.
Horst/Schoenfeldt does not expressly teach:
synchronize, based on the modified address list, a second portion of the memory allocated to the module with the first portion of the memory.
However, Tsirkin discloses:
synchronize, based on the modified address list, a second portion of the memory allocated to the module with the first portion of the memory (Tsirkin, [0025]—under BRI, synchronizing memory can be merging the contents of the memory page with the duplicate page).
Both Tsirkin and Horst/Schoenfeldt pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Tsirkin’s method to merge memory because it is well-known in the art that when memory is modified, cache coherence requires memory be synchronized.
As per claim 7, Horst/Schoenfeldt/Tsirkin teaches:
The one or more machine readable media of Claim 1 (See rejection on claim 1), wherein the first processor is to execute the instructions further to:
detect the exception for the tag check failure, wherein the modified address list is to be updated with the information in response to, at least in part, detecting the exception for the tag check failure (Schoenfeldt, [0050], [0078]).
As per claim 11, Horst/Schoenfeldt/Tsirkin teaches:
The one or more machine readable media of Claim 1 (See rejection on claim 1), wherein the information represents the first memory address or an interval of memory addresses that includes the first memory address (Horst, col 6, ll 10).
As per claim 16, see rejection on claim 1.
As per claim 21, see rejection on claim 1.
As per claim 23, see rejection on claim 1.
Claims 8. 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Horst/Schoenfeldt/Tsirkin as applied above, and further in view of Loison et al (US 2023/0100746) (hereinafter Loison).
As per claim 8, Horst/Schoenfeldt/Tsirkin teaches:
The one or more machine readable media of Claim 7 (see rejection on claim 7).
Horst/Schoenfeldt/Tsirkin does not expressly teach:
wherein the modified address list is to be updated with the information in response to, in part, a determination that the memory access operation modified data stored at the first memory address.
However, Loison discloses:
wherein the modified address list is to be updated with the information in response to, in part, a determination that the memory access operation modified data stored at the first memory address (Loison, [0031]).
Both Loison and Horst/Schoenfeldt/Tsirkin pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Loison’s method to mark an address list dirty after modification because it is well-known in the art that dirty bit improves cache performance and coherence by identifying modified cache blocks, allowing write-back caching to minimize costly main memory writes.
As per claim 19, Horst/Schoenfeldt/Tsirkin teaches:
The apparatus of Claim 16 (See rejection on claim 16).
Horst/Schoenfeldt/Tsirkin does not expressly teach:
wherein the modified address list is to be updated with the information in response to detecting the exception for the tag check failure and a determination that the memory access operation modified data stored at the first memory address.
However, Loison discloses:
wherein the modified address list is to be updated with the information in response to detecting the exception for the tag check failure and a determination that the memory access operation modified data stored at the first memory address (Loison, [0031]) .
Both Loison and Horst/Schoenfeldt/Tsirkin pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Loison’s method to mark an address list dirty after modification because it is well-known in the art that dirty bit improves cache performance and coherence by identifying modified cache blocks, allowing write-back caching to minimize costly main memory writes.
As per claim 22, see rejection on claim 19.
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Horst/Schoenfeldt/Tsirkin as applied above, and further in view of Kurita et al (US 2023/0297514) (hereinafter Kurita).
As per claim 9, Horst/Schoenfeldt/Tsirkin teaches:
The one or more machine readable media of Claim 1 (see rejection on claim 1).
Horst/Schoenfeldt/Tsirkin does not expressly teach:
wherein the first portion of the memory is a first continuous range of memory addresses in the memory, wherein the second portion of the memory is a second continuous range of memory addresses in the memory.
However, Kurita discloses:
wherein the first portion of the memory is a first continuous range of memory addresses in the memory, wherein the second portion of the memory is a second continuous range of memory addresses in the memory (Kurita, claim 7).
Both Kurita and Horst/Schoenfeldt/Tsirkin pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Kurita’s method to use a first and second continuous range of memory addresses in the memory because it is well-known in the art that contiguous memory allocation offers significant performance advantages, primarily due to faster data access, improved CPU caching, and reduced management overhead.
As per claim 20, Horst/Schoenfeldt/Tsirkin teaches:
The apparatus of Claim 16 (See rejection on claim 16).
Horst/Schoenfeldt/Tsirkin does not expressly teach:
wherein the memory includes a first memory and a second memory that is separate from the first memory, wherein the first memory includes the first portion of the memory and the second memory includes the second portion of the memory.
However, However, Kurita discloses:
wherein the memory includes a first memory and a second memory that is separate from the first memory, wherein the first memory includes the first portion of the memory and the second memory includes the second portion of the memory (Kurita, Fig 11 Bank 0-3).
Both Kurita and Horst/Schoenfeldt/Tsirkin pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Kurita’s method to use a first and second memory because it is well-known in the art that arranging memory in banks offers several benefits, including improved throughput and latency compared to non-banked devices of identical capacity
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Horst/Schoenfeldt/Tsirkin as applied above, and further in view of Torola et al (US 2023/0315602) (hereinafter Torola).
As per claim 10, Horst/Schoenfeldt/Tsirkin teaches:
The one or more machine readable media of Claim 1 (see rejection on claim 1).
Horst/Schoenfeldt/Tsirkin does not expressly teach:
wherein to synchronize the second portion of the memory with the first portion of the memory is to:
copy data stored at one or more memory addresses specified in the modified address list for the first portion of the memory to one or more corresponding memory addresses in the second portion of the memory.
However, Torola discloses:
wherein to synchronize the second portion of the memory with the first portion of the memory is to:
copy data stored at one or more memory addresses specified in the modified address list for the first portion of the memory to one or more corresponding memory addresses in the second portion of the memory (Torola, [0042]).
Both Torola and Horst/Schoenfeldt/Tsirkin pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Torola’s method to copy data in the memory because it is well-known in the art that copying data within memory (RAM) is a critical operation in computing that, while using CPU cycles, offers significant performance benefits over accessing slower, non-volatile storage (like SSDs or HDDs).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Horst/Schoenfeldt/Tsirkin as applied above, and further in view of Scrivano et al (US 2024/0103882) (hereinafter Scrivano).
As per claim 12, Horst/Schoenfeldt/Tsirkin teaches:
The one or more machine readable media of Claim 1 (See rejection on claim 1).
Horst/Schoenfeldt/Tsirkin does not expressly teach:
wherein the module includes WebAssembly binary code compiled from a first software language.
However, Scrivano discloses:
wherein the module includes WebAssembly binary code compiled from a first software language (Scrivano, [0020]).
Both Scrivano and Horst/Schoenfeldt/Tsirkin pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Scrivano’s method to use WebAssembly because it is well-known in the art that WebAssembly is a binary instruction format that brings near-native execution speed to web browsers, enabling high-performance applications like video editing, gaming, and complex simulations. It enhances security via sandboxing, supports multiple languages, and facilitates code portability across web and serverless environments.
As per claim 13, Horst/Schoenfeldt/Tsirkin teaches:
The one or more machine readable media of Claim 1 (See rejection on claim ).
Horst/Schoenfeldt/Tsirkin does not expressly teach:
wherein the instructions are included in a WebAssembly runtime.
However, Scrivano discloses:
wherein the instructions are included in a WebAssembly runtime (Scrivano, [0020]).
Both Scrivano and Horst/Schoenfeldt/Tsirkin pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Scrivano’s method to use WebAssembly runtime because it is well-known in the art that WebAssembly is a binary instruction format that brings near-native execution speed to web browsers, enabling high-performance applications like video editing, gaming, and complex simulations. It enhances security via sandboxing, supports multiple languages, and facilitates code portability across web and serverless environments.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Horst/Schoenfeldt/Tsirkin as applied to claim 1 above, and further in view of Raju et al (US 2015/0281047) (hereinafter Raju) .
As per claim 14, Horst/Schoenfeldt/Tsirkin teaches:
The one or more machine readable media of Claim 1 (See rejection on claim 1).
Horst/Schoenfeldt/Tsirkin does not expressly teach:
wherein the first processor is a first stack-based virtual processor that runs on a first physical processor, and wherein the second processor is a second stack-based virtual processor that runs on a second physical processor.
However, Raju discloses:
wherein the first processor is a first stack-based virtual processor that runs on a first physical processor, and wherein the second processor is a second stack-based virtual processor that runs on a second physical processor (Raju, Abstract).
Both Raju and Horst/Schoenfeldt/Tsirkin pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Raju’s method to use stack virtual processors because it is well-known in the art that stack processors offer significant advantages in computer architecture, including smaller program sizes (higher code density), lower hardware complexity, and faster, more efficient subroutine calls and recursion management compared to register-based machines.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Horst/Schoenfeldt/Tsirkin as applied to claim 1above, and further in view of Jacob et al (US 2016/0253123) (hereinafter Jacob).
As per claim 15, Horst/Schoenfeldt/Tsirkin teaches:
The one or more machine readable media of Claim 1 (See rejection on claim 1).
Horst/Schoenfeldt/Tsirkin does not expressly teach:
wherein the memory is to be mapped to a unified main memory.
However, Jacob discloses:
wherein the memory is to be mapped to a unified main memory (Jacob, [0005]).
Both Jacob and Horst/Schoenfeldt/Tsirkin pertain to the art of memory systems.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Jacob’s method to use unified main memory because it is well-known in the art that unified memory offers several benefits including reduced latency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2016/0034300 teaches a method of updating memory table in response to a memory access exception.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
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/CHARLIE SUN/Primary Examiner, Art Unit 2198