DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 11 recites the limitation “wherein forming at least one exposed area in the film comprises: laminating the film onto the metal layer”. However, the step of forming at least one exposed areas in the film is part of the step of patterning the film, discussed in claim 10, whereas claim 1 line 6 already recites a step of providing the film on the metal layer by lamination. Therefore it is not sufficiently clear from the claim language if the lamination of the film on the metal layer is performed during one or both of the recited steps of “providing a film on the metal layer by lamination” and “patterning the film by forming a cavity to expose an area of the metal layer” as recited in claim 1 lines 6-7, and/or how the same film would be laminated to the metal layer in both of these steps as recited in light of the disclosure of the invention, thereby rendering the claim indefinite because the metes and bounds of the claim are not sufficiently clear. For the purpose of examination, the examiner interprets this limitation to read as “wherein the forming the at least one exposed areas in the film is performed after laminating the film onto the metal layer” so as to be supported by the disclosure of the invention.
Claim 12 recites the limitation “wherein forming at least one exposed area in the film comprises: providing the film with a thickness of 12 µm or more”. This limitations shares a similar problem as claim 11 above, as it is not sufficiently clear from the claim language if the lamination/providing of the film on the metal layer is performed during one or both of the recited steps of “providing a film on the metal layer by lamination” and “patterning the film by forming a cavity to expose an area of the metal layer” as recited in claim 1 lines 6-7, and/or how the same film would be laminated/provided to the metal layer in both of these steps as recited in light of the disclosure of the invention, thereby rendering the claim indefinite because the metes and bounds of the claim are not sufficiently clear. For the purpose of examination, the examiner interprets this limitation to read as “wherein the providing the film on the metal layer comprises: providing the film with a thickness of 12 µm or more”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7, 9-11, and 14-18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over US 2005/0245087 to Sasagawa in view of US 2020/0350178 to Ren, TW 201218886 to Bai (translation previously provided by examiner), and US 2005/0124091 to Fukase.
As per claim 1, Sasagawa discloses a method of manufacturing a component carrier, the method comprising:
providing a substrate (see substrate 100 in Fig 5A) with opposed surfaces, the substrate comprising an organic material (Para 0052 indicates that the substrate 100 can be a polycarbonate, polyethylene sulfone, polyethylene terephthalate, or polyethylene naphthalate which are organic compounds).
providing a metal layer (see conductive layer 102 in Fig 5A and step S101 in Fig 1-2) on at least one of the opposed surfaces;
providing a film (see first mask pattern 103 in Fig 5A) on the metal layer;
patterning the film by forming a cavity in order to expose an area of the metal layer (see cavities provided to the left and right of the mask pattern 103 in Fig 5A that expose the conductive layer 102; Para 0055 and 0105 indicate that the mask pattern 103 can be formed by a photolithography method including coating a resist over the conductive layer and developing and removing the portions of the mask associated with the cavities to form the mask pattern 103);
carrying out a first etch (see conductive layer 302 in Fig 5B and step S102 in Fig 1-2), thereby removing a part of the exposed metal layer and reducing a thickness and part of the film (see Fig 5B that shows that the mask pattern 103 is etched by the first etch resulting in mask pattern 312 with reduced thickness and reduced width; Para 0080), and enlarging the exposed area of the metal layer (see Fig 5B wherein the reduced width of mask pattern 312 increases the exposed area of the conductive layer 302; also the partial etching through the conductive layer as shown in Fig 5B would also increase the exposed area of the conductive layer 302); and thereafter
carrying out a second etch (see conductive layers 311 and 321 in Fig 5D-E and step S103 in Fig 1-2), thereby forming at least one metal trace that is spatially separated from the metal layer (see Fig 5D-E that shows that the conductive layers 311/321 are spatially separated from the rest of the metal layer, i.e. the rest of the conductive layer 102).
As per claim 1, Sasagawa discloses the elements of the current invention as detailed above with respect to claim 1, but Sasagawa discloses that the second etch reduces the thickness of the film and therefore does not disclose that the second etch does not affect the film as claimed. However, it is understood by the examiner that determining the extent to which a step of etching affects a film, i.e. a mask, for an etching process would be within the skill of one of ordinary skill in the art and it would have been an obvious choice to choose to have an etching step not affect a film during an etching process as this would prevent the film/mask from becoming too degraded which could negatively affect the accuracy of the etching process.
Ren discloses a similar method of manufacturing a component carrier wherein a metal layer (see conductive material 10 in Fig 4A) is provided on a component carrier (see substrate 405 in Fig 4A), a patterned film (see mask material 415 in Fig 4A) is provided on the metal layer, a first etch is carried out to remove a part of an exposed portion of the metal layer under the patterned film (see Fig 4B; see step 315 in Fig 3), and a second etch is carried out to further remove an exposed portion of the metal layer and finalize a metal trace (see Fig 4C; see step 325 in Fig 3; Para 0044-0053), wherein the first etch reduces a thickness of the patterned film, but the second etch does not affect the patterned film, thereby reducing contamination of the metal trace in the second etching step while simultaneously preventing oxidation of the metal trace in the first etching step (Para 0052-0053).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the second etch of Sasagawa to not affect the film as taught by Ren. One of ordinary skill in the art would have realized that determining the extent to which a step of etching affects a film, i.e. a mask, for an etching process would be within the skill of one of ordinary skill in the art and it would have been an obvious choice to choose to have an etching step not affect a film during an etching process especially in view of Ren; the obvious advantage of the second etch not affecting the film being that this would reduce contamination of the metal trace in the second etching step and also allow for the prevention of oxidation of the metal trace in the first etching step (Para 0052-0053).
As per claim 1, Sasagawa and Ren disclose the elements of the current invention as detailed above with respect to claim 1, but Sasagawa discloses that the etching techniques used for the first and second etching are dry etching techniques such as ICP, ECR, RIE, CCP, SWP, etc. (Para 0060), and Ren discloses that both wet and dry etching processes are known, but specifically uses dry etching methods such as RIE, and therefore do not specifically teach that the second etch specifically comprises wet etching. However, wet etching is well-known in the art and it would have been an obvious substitution for one of ordinary skill in the art to substitute dry etching for wet etching as both dry etching and wet etching have drawbacks as discussed in Ren (see Para 0004), and it would have been within the skill of one of ordinary skill in the art to choose between wet etching and dry etching depending on the specific application. Further, the current application discloses that the second etch can be performed using dry etching or wet etching (see Para 0011, 0024, 0074 of the Specification as originally filed) and does not provide any criticality to specifically using wet etching over dry etching; therefore there is no reason to expect that it would not be an obvious choice for one of ordinary skill in the art to choose wet etching over dry etching.
Bai discloses a similar multiple etching process for forming a component carrier with plural circuit traces (see finished circuit board 100 Fig 13) including a step of providing a metal layer (see copper foil layer 12 in Fig 1), a step of forming a film over the metal layer (see photoresist layer 21 in Fig 2), patterning the film (see Fig 3) and etching exposed portions of the metal layer using the patterned film (see openings 141-143 in Fig 4), followed by further etchings steps using films as masks (see Fig 7-8 and 11-12) to form separated traces (see first line 15 and second line 16 in Fig 13), wherein the etching steps are performed using wet etching methods using an isotropic etchant so as to reduce the isotropic etching of the metal layer to allow for the production of thick copper circuit boards with high production yield while still using the isotropic etchants and etchings processes known in the art therefore not increasing the cost or efficiency of the process (see Translation Page 2-3).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the above combination of Sasagawa and Ren as to use a wet etching method for the second etch as taught by Bai. One of ordinary skill in the art would recognize both wet etching and dry etching methods are known in the art and wet etching would be an obvious substitution for dry etching, and it would have been within the skill of one of ordinary skill in the art to choose between wet etching and dry etching depending on the specific application, especially since the current application does not provide any criticality to specifically using wet etching rather than dry etching; the obvious advantages of using a wet etching method for the second etch being that the use of an isotropic etchant that would allow for thick copper circuit boards to be produced with high yield without increasing the cost or efficiency of the process (Bai: see Translation Page 2-3).
As per claim 1, Sasagawa, Ren, and Bai disclose the elements of the current invention as detailed above with respect to claim 1, but Sasagawa discloses that the film is coated and dried on the metal layer and therefore does not explicitly disclose that the film is provided on the metal layer by lamination. However, both coating and lamination are very well-known methods for providing films, especially to be used as etching masks, and therefore it would have been an obvious choice for one of ordinary skill in the art to choose between coating and laminating the film on the metal layer.
Fukase discloses a similar multiple step etching process wherein a dry film resist (see masking 4 in Fig 2b), that would inherently and/or obviously be solvent-free, is laminated over a metal layer (see copper foil 2 in Fig 1-2) for a multiple step etching process (see Fig 2a-f)(Para 0017 and 0040).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the film of Sasagawa to specifically be a dry film that is laminated on the metal layer as taught by Fukase. One of ordinary skill in the art would have realized that both coating and laminating are very well-known methods for providing films, and that it would be within the skill of one of ordinary skill in the art to determine an appropriate method for supplying a film to a metal layer based on the particular circumstances of the application; the obvious advantage of laminating a dry solvent-less film would be to avoid the application of a wet material to the metal layer which would require a drying time and/or the application of heat to dry the wet material that would lengthen the manufacturing process and/or add additional heating steps to the process that could damage/delaminate components due to thermal expansion as would be generally understood by one of ordinary skill in the art.
As per claim 2, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 1. Sasagawa further discloses that the forming of the at least one metal trace comprises forming a first cavity and a further cavity in the metal layer by the first etch and the second etch such that the metal trace is located between the cavities (see Fig 5B and 5D that show the first and second etching steps forming a cavity within the conductive layer on either side of the metal trace to be formed, these cavities representing the first and further cavities with the metal trace, i.e. the conductive layer 311 located between the cavities)
As per claim 3, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 1. Sasagawa further discloses that the area of the metal layer where the first etch and the second etch are carried out further comprises at least two adjacent sub-areas on one of the first surface and the opposed surface, wherein said at least two sub-areas are provided at a distance from each other to form the metal trace (see Fig 5A and 5D that show the first and second etching steps are performed on adjacent sub-areas on either side of the metal trace to be formed, these areas being spaced from each other by a distance represented by the width of the metal trace, i.e. the conductive layer 311).
As per claim 4, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 1. Sasagawa further discloses that the first etch comprises a wet etch or a dry etch (Para 0060, 0080, and 0106).
As per claim 6, Sasagawa, Ren, Bai, and Fukase discloses the elements of the current invention as detailed above with respect to claim 1. Sasagawa further discloses that the film is not resistant to the first etch (see Para 0080 that indicates that the mask 103 in Fig 5A is etched to reduce the width and the thickness by the first etch to form mask 312 in Fig 5B and therefore the mask 103 can be considered to be not resistant to the first etch).
As per claims 7 and 14, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 1. Sasagawa further discloses that the film (see mask pattern 103 in Fig 5A) can be coated over the first conductive layer and pre-baked and developed (see Para 0105) and therefore can be considered a “dry film” that would inherently or obviously be “solvent-free” as claimed; and Fukase discloses that the film laminated over the metal layer (see 2 in Fig 1-2) for the multiple step etching process (see Fig 2a-f) is a dry film resist (see masking 4 in Fig 2b), that would inherently and/or obviously be solvent-free (Para 0017 and 0040).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the film of Sasagawa to specifically be a dry film that is solvent-less as taught by Fukase. One of ordinary skill in the art would have realized that determining an appropriate type of film used as a mask for an etching process would have merely involved routine skill in the art as both wet and dry films are well-known in the art for such etching processes; the obvious advantage of choosing a dry solvent-less film would be that the dry film can by laminated over the top of the metal layer rather than coated with a wet material so as to avoid a drying time that would lengthen the manufacturing process as would be generally understood by one of ordinary skill in the art.
As per claim 9, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 1. Sasagawa further discloses that first etch can be an anisotropic etching, i.e. in one direction, such as shown in Fig 4B (Para 0071); and Bai that an isotropic etchant is used for the multiple etching steps so as to reduce the isotropic etching of the metal layer to allow for the production of thick copper circuit boards with high production yield while still using the isotropic etchants and etchings processes known in the art therefore not increasing the cost or efficiency of the process (see Translation Page 2-3).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the etchant used for the for the first etch and/or second etch in Sasagawa to be an isotropic etchant as taught by Bai. One of ordinary skill in the art would recognize that isotropic etchants are very well-known in the art and therefore it would be a routine matter to choose to use an isotropic etchant as these etchants are readily available and the processes of using such etchants are well-known; the obvious advantages being that the use of the isotropic etchants used for multiple etching steps as disclosed in Bai would reduce the isotropic etching of the metal layer to allow for the production of thick copper circuit boards with high production yield while still using the isotropic etchants and etchings processes known in the art therefore not increasing the cost or efficiency of the process (Bai: see Translation Page 2-3).
As per claim 10, Sasagawa, Ren, Bai, and Fukase discloses the elements of the current invention as detailed above with respect to claim 1. Sasagawa further discloses that the film is patterned by a photolithography process (Para 0055 and 0105) which is known in the art to include exposing areas of the film using light followed by a development process to form the film into a pattern such as disclosed in Bai (see Fig 2-3 in which the photoresist layer 21 is laminated on the copper foil layer 12 and patterned by lithography; see Translation page 4).
As per claim 11, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 10. Sasagawa further discloses that the forming the at least one exposed areas in the film is performed after laminating the film onto the metal layer (Para 0105).
As per claim 15, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 1. Sasagawa further discloses that the film (103/312/313 in Fig 5) is removed after the second etch (see Fig 5E-F)
As per claim 16, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 1, but Sasagawa does not explicitly disclose that the metal layer has a thickness of 30 µm or more, but Bai discloses that the metal layer can be a thick metal layer with a thickness of 12 to 210 µm (see Translation Page 4; see abstract and Page 7 Translation that indicates the metal layer can be 100 µm or more) to result in thick circuit traces with high current, integrated power, good heat dissipation, and control characteristic impedance (see Translation Page 2).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the thickness of the metal layer of Sasagawa to have a thickness of 30 µm or more as taught by Bai. One of ordinary skill in the art would have realized that determining an appropriate thickness of a metal layer for forming traces would have merely involved routine skill in the art as it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges of dimensions involves only ordinary skill in the art; the obvious advantage of choosing a thickness of at least 30 µm being that this would allow for the creation of thick circuit traces with high current, integrated power, good heat dissipation, and control characteristic impedance (Bai: see Translation Page 2).
As per claim 17, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 1. Sasagawa discloses other embodiments of the invention in which plural metal traces are present (see conductive layers 2006, 2007, and 2008 in Fig 14A; Para 0154); and Bai discloses the forming of plural separated traces (see first line 15 and second line 16 in Fig 13) that are arranged side-by-side with a bottom sided spacing in between (see seventh opening 147 in Fig 13).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the method of Sasagawa as to form first and second traces that are arranged side-by-side with a bottom-sided spacing in between as taught by Bai. One of ordinary skill in the art would have realized that having multiple traces arranged side-by-side with a bottom side spacing in between would only represent a mere duplication of parts which would have been well-within the skill of one of ordinary skill in the art as it has been held that mere duplication of essential working parts of a device involves only routine skill in the art; the obvious advantage of forming multiple metal traces side-by-side would be that more complicated devices can be made with more metal traces as would be generally understood by one of ordinary skill in the art.
As per claim 18, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 17. Bai further discloses that the area of the metal trace where the first etch and the second etch are carried out comprises more than two adjacent sub-areas on one of the component carrier main surfaces (see Fig 1 that shows the sub-areas to be etched represented by the first etch region 123, the second etch region 124, and the third etch region 125 that are provided on one surface of the circuit board 10; also see Fig 2-13 that show that the first etch region 123, the second etch region 124, and the third etch region 125 are etched to form the first line 15 and the second line 16), wherein said more than two sub-areas are provided at a distance from each other (see distance between the first etch region 123, the second etch region 124, and the third etch region 125 represented by the size of the first line region 121 and the second line region 122 respectively), so that, after the first and the second etch, at least two adjacent metal traces between the sub-areas are formed side-by-side (see first line 15 and the second line 16 in Fig 13), wherein the sub-areas are arranged with a bottom-sided spacing in between (see Fig 1-13 wherein a bottom side spacing is provided between the first etch region 123, the second etch region 124, and the third etch region 125 represented by the first line region 121 and the second line region 122 respectively), wherein, after the second etch, at least two adjacent metal traces are spaced by the bottom-sided spacing of less than 45 µm (see translation Page 7 that indicates that a line distance between the first line 15 and the second line 16 is above 10 microns), wherein, after the second etch, each of the adjacent metal traces has a thickness of at least 30 µm (see Translation Page 7 that indicates that the lines 15 and 16 have a thickness of 100 µm or more), wherein the metal layer can be a thick metal layer with a thickness of 12 to 210 µm (see Translation Page 4) to result in thick circuit traces with high current, integrated power, good heat dissipation, and control characteristic impedance (see Translation Page 2).
Claim 12 is rejected under AIA 35 U.S.C. 103 as being unpatentable over US 2005/0245087 to Sasagawa, US 2020/0350178 to Ren, TW 201218886 to Bai (translation previously provided by examiner), and US 2005/0124091 to Fukase in further view of US 2006/0127690 to Ueda.
As per claim 12, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 10. Sasagawa, Ren, and Bai are silent regarding the thickness of the film and therefore do not explicitly disclose that the film has a thickness of 12 µm or more as claimed. However, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges of dimensions involves only ordinary skill in the art, and therefore it would have been an obvious design choice for one of ordinary skill in the art to choose the thickness of the film to be 12 µm or more as claimed.
Ueda discloses a similar multiple etching process for etching through a metal base (see 1 in Fig 1A) including forming a patterned photoresist (see resist layer 2 in Fig 1A) and performing multiple etches using the patterned photoresist to etch through the metal base (see Fig 1B-E), wherein the photoresist can have a thickness from 3-30 µm (Para 0127).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the thickness of the film of Sasagawa to have a thickness of 12 µm or more as taught by Ueda. One of ordinary skill in the art would have realized that determining an appropriate thickness of a masking film would have merely involved routine skill in the art as it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges of dimensions involves only ordinary skill in the art; the obvious advantage of choosing a thickness of at least 12 µm being that this would allow for appropriate etching resistance and resolution (Ueda: Para 0127).
Claim 13 is rejected under AIA 35 U.S.C. 103 as being unpatentable over US 2005/0245087 to Sasagawa, US 2020/0350178 to Ren, TW 201218886 to Bai (translation previously provided by examiner), and US 2005/0124091 to Fukase in further view of JP 2005-285946 to Shomura (translation previously provided by examiner).
As per claim 13, Sasagawa, Ren, Bai, and Fukase disclose the elements of the current invention as detailed above with respect to claim 1. Sasagawa further discloses that the reducing the thickness of the film during the first etch includes reducing the thickness of the film (see Fig 5B that shows that the first etch reduced the thickness of the mask 103 to form the mask 312; Para 0080), but does not explicitly disclose that the thinning is to a thickness of 90% or lower of an initial thickness of the film. However, the thinning of the film to a thickness of 90% or lower of an initial thickness of the film provides no criticality insofar as the record is concerned to the claimed method. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges of dimensions involves only ordinary skill in the art, and therefore it would have been an obvious design choice for one of ordinary skill in the art to choose the thinning of the film to be to a thickness of 90% or lower of the initial thickness with the reasonable expectation that this would leave enough of the thickness of the film to be effective for future etching steps as taught by Sasagawa (see Fig 3B Fig 5B-D that show that the thinned mask 312 is used for the second etch) while also allowing some leeway for the etchant to remove some of the thickness of the film so as to avoid using less powerful etchants which can extend the length of the etching process as would be generally understood by one of ordinary skill in the art.
Shomura discloses a similar etching process wherein a film is used as a mask in an etching process (see photoresists 3a and 4a in Fig 1c) of a metal layer (see metal foil in Fig 1c), wherein it is disclosed that it is known that an increased thickness of the film is desirable because this increases the strength of the film, but increasing the thickness of the resist results in decreasing resolution of the etching as the flow of etching liquid between resist is hindered by the narrow gaps (see Translation page 3).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the amount of thinning of the film in Sasagawa to be to a thickness of 90% or lower of the initial thickness in light of Shomura in order to allow for the initial thickness of the film for the first etch to be increased so that the strength of the film for the first etch can be increased, such as to allow for more etchings steps, while allowing for the second etch to have an increased resolution due to the decrease of thickness of the film as taught by Shomura. One of ordinary skill in the art would have realized that determining an appropriate thinning amount of the film would have merely involved routine skill in the art as it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges of dimensions involves only ordinary skill in the art; an obvious advantage of choosing to reduce the thickness of the film to be to a thickness of 90% or lower of the initial thickness being that this would leave enough of the thickness of the film to be effective for future etching steps as taught by Sasagawa while also allowing some leeway for the etchant to remove some of the thickness of the film so as to avoid using less powerful etchants which can extend the length of the etching process as would be generally understood by one of ordinary skill in the art; and also that this would allow for the strength of the initial film to be increased for the first etch while allowing for an increased etching resolution for the second etch due to the decrease of thickness of the film as taught by Shomura (Shomura: see Translation Page 3).
Claims 21-22 are rejected under AIA 35 U.S.C. 103 as being unpatentable over US 2005/0245087 to Sasagawa in view of TW 201218886 to Bai (translation previously provided by examiner) and US 2005/0124091 to Fukase.
As per claim 21, Sasagawa discloses a method of manufacturing an organic component carrier, the organic component carrier in the form of a printed circuit board or an integrated circuit substrate, the method comprising:
providing a substrate (see substrate 100 in Fig 5A) with opposed surfaces, the substrate comprising an organic material (Para 0052 indicates that the substrate 100 can be a polycarbonate, polyethylene sulfone, polyethylene terephthalate, or polyethylene naphthalate which are organic compounds).
providing a metal layer (see conductive layer 102 in Fig 5A and step S101 in Fig 1-2) on at least one of the opposed surfaces;
providing a film (see first mask pattern 103 in Fig 5A) on the metal layer;
patterning the film by forming a cavity in order to expose an area of the metal layer (see cavities provided to the left and right of the mask pattern 103 in Fig 5A that expose the conductive layer 102; Para 0055 indicates that the mask pattern 103 can be patterned by a photolithography method which is known to include providing a blanket mask and removing the portions of the mask associated with the cavities to form the mask pattern 103);
carrying out a first etch (see conductive layer 302 in Fig 5B and step S102 in Fig 1-2), thereby removing a part of the exposed metal layer and reducing a thickness and part of the film (see Fig 5B that shows that the mask pattern 103 is etched by the first etch resulting in mask pattern 312 with reduced thickness and reduced width; Para 0080), and enlarging the exposed area of the metal layer (see Fig 5B wherein the reduced width of mask pattern 312 increases the exposed area of the conductive layer 302; also the partial etching through the conductive layer as shown in Fig 5B would also increase the exposed area of the conductive layer 302); and thereafter
carrying out a second etch (see conductive layers 311 and 321 in Fig 5D-E and step S103 in Fig 1-2), thereby forming at least one metal trace that is spatially separated from the metal layer (see Fig 5D-E that shows that the conductive layers 311/321 are spatially separated from the rest of the metal layer, i.e. the rest of the conductive layer 102).
As per claim 21, Sasagawa disclose the elements of the current invention as detailed above with respect to claim 1, but Sasagawa discloses that the etching techniques used for the first and second etching are dry etching techniques such as ICP, ECR, RIE, CCP, SWP, etc. (Para 0060), therefore does not specifically teach that the second etch specifically comprises wet etching. However, wet etching is well-known in the art and it would have been an obvious substitution for one of ordinary skill in the art to substitute dry etching for wet etching as both dry etching and wet etching have drawbacks (for example as discussed in Para 0004 of Ren as discussed above), and it would have been within the skill of one of ordinary skill in the art to choose between wet etching and dry etching depending on the specific application. Further, the current application discloses that the second etch can be performed using dry etching or wet etching (see Para 0011, 0024, 0074 of the Specification as originally filed) and does not provide any criticality to specifically using wet etching over dry etching; therefore there is no reason to expect that it would not be an obvious choice for one of ordinary skill in the art to choose wet etching over dry etching.
Bai discloses a similar multiple etching process for forming a component carrier with plural circuit traces (see finished circuit board 100 Fig 13) including a step of providing a metal layer (see copper foil layer 12 in Fig 1), a step of forming a film over the metal layer (see photoresist layer 21 in Fig 2), patterning the film (see Fig 3) and etching exposed portions of the metal layer using the patterned film (see openings 141-143 in Fig 4), followed by further etchings steps using films as masks (see Fig 7-8 and 11-12) to form separated traces (see first line 15 and second line 16 in Fig 13), wherein the etching steps are performed using wet etching methods using an isotropic etchant so as to reduce the isotropic etching of the metal layer to allow for the production of thick copper circuit boards with high production yield while still using the isotropic etchants and etchings processes known in the art therefore not increasing the cost or efficiency of the process (see Translation Page 2-3).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the above combination of Sasagawa and Ren as to use a wet etching method for the second etch as taught by Bai. One of ordinary skill in the art would recognize both wet etching and dry etching methods are known in the art and wet etching would be an obvious substitution for dry etching, and it would have been within the skill of one of ordinary skill in the art to choose between wet etching and dry etching depending on the specific application, especially since the current application does not provide any criticality to specifically using wet etching rather than dry etching; the obvious advantages of using a wet etching method for the second etch being that the use of an isotropic etchant that would allow for thick copper circuit boards to be produced with high yield without increasing the cost or efficiency of the process (Bai: see Translation Page 2-3).
As per claim 21, Sasagawa and Bai disclose the elements of the current invention as detailed above with respect to claim 1, but Sasagawa discloses that the film is coated and dried on the metal layer and therefore does not explicitly disclose that the film is provided on the metal layer by lamination. However, both coating and lamination are very well-known methods for providing films, especially to be used as etching masks, and therefore it would have been an obvious choice for one of ordinary skill in the art to choose between coating and laminating the film on the metal layer.
Fukase discloses a similar multiple step etching process wherein a dry film resist (see masking 4 in Fig 2b), that would inherently and/or obviously be solvent-free, is laminated over a metal layer (see copper foil 2 in Fig 1-2) for a multiple step etching process (see Fig 2a-f)(Para 0017 and 0040).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the film of Sasagawa to specifically be a dry film that is laminated on the metal layer as taught by Fukase. One of ordinary skill in the art would have realized that both coating and laminating are very well-known methods for providing films, and that it would be within the skill of one of ordinary skill in the art to determine an appropriate method for supplying a film to a metal layer based on the particular circumstances of the application; the obvious advantage of laminating a dry solvent-less film would be to avoid the application of a wet material to the metal layer which would require a drying time and/or the application of heat to dry the wet material that would lengthen the manufacturing process and/or add additional heating steps to the process that could damage/delaminate components due to thermal expansion as would be generally understood by one of ordinary skill in the art.
As per claim 22, Sasagawa, Bai, and Fukase discloses the elements of the current invention as detailed above with respect to claim 21. Sasagawa discloses other embodiments of the invention in which plural metal traces are present (see conductive layers 2006, 2007, and 2008 in Fig 14A; Para 0154); and Bai discloses forming plural separated traces (see first line 15 and second line 16 in Fig 13) that are arranged side-by-side with a bottom sided spacing in between (see seventh opening 147 in Fig 13).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the method of Sasagawa as to form plural traces that are arranged side-by-side as taught by Bai. One of ordinary skill in the art would have realized that having multiple traces arranged side-by-side with a bottom side spacing in between would only represent a mere duplication of parts which would have been well-within the skill of one of ordinary skill in the art as it has been held that mere duplication of essential working parts of a device involves only routine skill in the art; the obvious advantage of forming multiple metal traces side-by-side would be that more complicated devices can be made with more metal traces as would be generally understood by one of ordinary skill in the art.
As per claim 22, Sasagawa further discloses that the traces are formed with a top-side line width less than that of a bottom-side line width of the traces (see conductive layers 2006, 2007, and 2008 in Fig 14A as well as conductive layer 131 in Fig 3D, conductive layer 231 in Fig 4D, and conductive layer 321 in Fig 5F), but does not explicitly disclose that the traces have a top-sided line width of at least 80% of its respective bottom-sided line width, and the first trace and/or the second trace comprises an etching factor of at least 3 (the disclosure of the invention defines the etching factor as EF=(2*thickness)/(BW-TW) as shown in Fig 4); and Bai further discloses that the two traces have a top-side line width of at least 80% of its respective bottom-side line width (see Fig 13 that shows that the two lines 15 and 16 have a wider bottom surface 151/161 compared with the top surface 152/162; see translation page 6-7 that indicates that the bottom side width is greater than or equal to 100 µm, and the difference between the bottom side width and the top side width is less than 50 µm; therefore the top side line width can be chosen to be 90 µm compared with the bottom side line width that is 100 µm or more, therefore the traces would have a top-side line width that is at least 90% of its respective bottom-side line width); Bai also discloses that the first trace and/or the second trace can comprise an etching factor of at least 3 (the disclosure of the invention defines the etching factor as EF=(2*thickness)/(BW-TW) as shown in Fig 4; see translation page 6-7 that indicates that the bottom side width is greater than or equal to 100 µm, the difference between the bottom side width and the top side width is less than 50 µm, and the thickness of the lines 15 and 16 is at least 100 µm; therefore the top side line width can be chosen to be 90 µm, the thickness can be chosen to be 100 µm, and the bottom side line width can be chosen to be 100 µm, therefore the etching factor is EF=(2*100)/(100-90)=20).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the dimensions of the traces of Sasagawa such that the top-sided line width of at least 80% of its respective bottom-sided line width, and the first trace and/or the second trace comprises an etching factor of at least 3 as taught by Bai. One of ordinary skill in the art would have realized that changing the relative dimensions of traces would only represent a mere change in the shape or size of parts which would have been well-within the skill of one of ordinary skill in the art as it has been held that discovering the optimum or workable ranges of dimensions involves only ordinary skill in the art, and therefore it would have been an obvious design choice for one of ordinary skill in the art to choose the relative widths and thicknesses of the traces such that a top-sided line width of at least 80% of its respective bottom-sided line width and the first trace and/or the second trace comprises an etching factor of at least 3 in view of the Bai reference; the obvious advantage being that this would result in thick circuit traces with high current, integrated power, good heat dissipation, and control characteristic impedance (Bai: see Translation Page 2).
Response to Arguments
Applicant’s arguments, see Applicant’s response, filed 01/08/2025, with respect to the rejection(s) of claim 21 under 35 U.S.C. 102(a)(1) as being anticipated by US 2005/0245087 to Sasagawa and the rejection(s) of claim 1 under 35 U.S.C. 103 as being unpatentable over US 2005/0245087 to Sasagawa in view of US 2020/0350178 to Ren have been fully considered and are persuasive in light of the claim amendments filed 11/24/2025, specifically regarding the film being provided by lamination and the second etch being carried out by wet etching. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of TW 201218886 to Bai and US 2005/0124091 to Fukase (see above 103 rejections of claims 1 and 21).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSHUA D ANDERSON/
Examiner, Art Unit 3729
/THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729