DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-9 and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung (US 2021/0358935).
[claim 1] A semiconductor device (fig. 2, figs. 3A-3E), comprising: a gate stack (EL, IL1, fig. 3A-3E) including insulating patterns (IL1, fig. 3A-3E, [0044]) and conductive patterns (EL, fig. 3A-3E, [0044]), which are alternately stacked; first block channel structures (VS in ST1, fig. 2, 3A-3E), wherein the first block channel structures are in a first memory block (block of ST1, fig. 2, 3A-3E), in penetrating the gate stack; second block channel structures (VS in ST2, fig. 2, 3A-3E) penetrating the gate stack, wherein the second block channel structures are in a second memory block (block of ST2, fig. 2, 3A-3E); and an isolation structure (MO, ISP, fig. 2, 3C) penetrating the gate stack, wherein the isolation structure comprises a block isolation structure (MO, ISP, bottom SPS, top SPS in fig. 2, see also fig. 3C) between the first block channel structures in the first memory block and the second block channel structures (fig. 2), a first word line isolation structure (one SPS in ST1 in the center of fig. 2, see also fig. 3E) extending in a first direction and between the first block channel structures (fig. 3E) , and a second word line isolation structure (next adjacent SPS in the center of fig. 2, see also fig. 3E) between the first block channel structures and adjacent to the first word line isolation structure (fig. 3E), wherein the second word line isolation structure extends parallel to the first word line isolation structure (fig. 2), the block isolation structure comprises a first side surface connected to a side surface of the first word line isolation structure (as can be seen in fig. 2, ISPs of the block isolation structure surrounds side surfaces of the word line isolations SPS, for example the side surface can be either in the D1 or D2 direction in fig. 2), and a second side surface connected to a side surface of the second word line isolation structure (as can be seen in fig. 2, ISPs of the block isolation structure surrounds side surfaces of the word line isolations SPS, for example the side surface can be either in the D1 or D2 direction in fig. 2), wherein the block isolation structure comprises a plurality of isolation portions, wherein a first isolation portion (an arbitrary rectangular portion of the block isolation structure between the first and third word line isolation that extends laterally along its major axis, fig. 2) of the plurality of isolation portions extends in a different direction than a second isolation portion (an arbitrary rectangular portion of the block isolation structure between the second and third word line isolation that extends vertically along its major axis, fig. 2) of the plurality of isolation portions, and the first block channel structures comprise an intervening channel structure between the first and second side surfaces of the block isolation structure (since the block isolation structure comprises the bottom SPS and top SPS in fig. 2, there would be an intervening block channel structure between the two SPSs at the top and bottom, see also fig. 3E).
[claim 2] The semiconductor device of claim 1, wherein the first and second side surfaces of the block isolation structure are connected to each other (side surfaces are connected through the block isolation structure, fig. 2).
[claim 3] The semiconductor device of claim 2, wherein a first angle between the first and second side surfaces of the block isolation structure (if the side surfaces of the block isolation structure are both in the D2 direction, the angle would be 0 degrees) is less than a second angle between the first side surface of the block isolation structure and the side surface of the first word line isolation structure (if the side of surface of the first word line isolation structure is in the D1 direction it would have a 90 degree angle with the D2 direction of the block isolation structure, fig. 2).
[claim 4] The semiconductor device of claim 1, wherein the block isolation structure comprises a third side surface (mirror side surface of mirror ISP of the first side surface of the ISP, fig. 2) opposite to the first side surface of the block isolation structure, and a fourth side surface (mirror side surface of mirror ISP of the second side surface of the adjacent ISP, fig. 2) opposite to the second side surface of the block isolation structure, and the isolation structure further comprises a third word line isolation structure (mirror ISP in ST2, fig. 2) connected to the third and fourth side surfaces of the block isolation structure and arranged between the second block channel structures, wherein the first isolation portion of the plurality of isolation portions extends between the first word line isolation structure and the third word line isolation structure (see above), and wherein the second isolation portion of the plurality of isolation portions extends between the third word line isolation structure and the second word line isolation structure (see above).
[claim 5] The semiconductor device of claim 1, further comprising: a share bit line (segments of BL, fig. 3C overlaps MO and ISP) overlapping the block isolation structure, wherein the first block channel structures comprise a first sharing channel structure (VS in ST1, fig. 2, 3A-E) electrically connected to the share bit line, and the second block channel structures comprise a second sharing channel structure (VS in ST2, fig. 2, 3A-E) electrically connected to the share bit line.
[claim 6] The semiconductor device of claim 1, further comprising: bit lines (segments of BL, fig. 3C overlaps MO and ISP) which extending in a second direction crossing the first direction, wherein the intervening channel structure is at least partially overlapped with the first and second side surfaces of the block isolation structure in the first direction (fig. 3C).
[claim 8] The semiconductor device of claim 1, further comprising: a dummy channel structure (DS, fig. 3B, [0060]) penetrating the gate stack, wherein, the dummy channel structure is enclosed by the block isolation structure (Fig. 3B).
[claim 9] The semiconductor device of claim 1, further comprising: an overlap bit line (segments of BL, fig. 3C overlaps MO and ISP), which at least partially overlaps the first and second side surfaces of the block isolation structure, wherein the intervening channel structure is at least partially overlapped by the overlap bit line (fig. 3B).
[claim 15] A semiconductor device (fig. 2, figs. 3A-3E), comprising: a gate stack (EL, IL1, fig. 3A-3E) including insulating patterns (IL1, fig. 3A-3E, [0044]) and conductive patterns (EL, fig. 3A-3E, [0044]), which are alternately stacked; bit lines (segments of BL, fig. 3A-3E) on the gate stack; first block channel structures (VS in ST1, fig. 2, 3A-3E) penetrating the gate stack wherein the first block channel structures are in a first memory block (block of ST1, fig. 2, 3A-3E); second block channel structures (VS in ST2, fig. 2, 3A-3E) penetrating the gate stack, wherein the second block channel structures are in a second memory block (block of ST2, fig. 2, 3A-3E); and an isolation structure (MO, ISP, fig. 2, 3C) penetrating the gate stack, wherein the isolation structure comprises a block isolation structure (MO, ISP, fig. 2, 3C) between the first block channel structures in the first memory block and the second block channel structures in the second memory block (fig. 2), a first word line isolation structure (one SPS in ST1 in the center of fig. 2, see also fig. 3E) extending in a first direction and between the first block channel structures (fig. 3E) , and a second word line isolation structure (next adjacent SPS in the center of fig. 2, see also fig. 3E) between the first block channel structures and adjacent to the first word line isolation structure (fig. 3E), wherein the second word line, wherein the second word line isolation structure extends parallel to the first word line isolation structure (fig. 2), the block isolation structure comprises a first side surface connected to a side surface of the first word line isolation structure (as can be seen in fig. 2, ISPs of the block isolation structure surrounds side surfaces of the word line isolations SPS, for example the side surface can be either in the D1 or D2 direction in fig. 2), and a second side surface connected to a side surface of the second word line isolation structure (as can be seen in fig. 2, ISPs of the block isolation structure surrounds side surfaces of the word line isolations SPS, for example the side surface can be either in the D1 or D2 direction in fig. 2), wherein the block isolation structure comprises a plurality of isolation portions, wherein a first isolation portion (an arbitrary rectangular portion of the block isolation structure between the first and third word line isolation that extends laterally along its major axis, fig. 2) of the plurality of isolation portions extends in a different direction than a second isolation portion (an arbitrary rectangular portion of the block isolation structure between the second and third word line isolation that extends vertically along its major axis, fig. 2) of the plurality of isolation portions, wherein the bit lines a first overlap a bit line ate at least partially overlapping the first and second side surfaces of the block isolation structure (fig. 2) and the first block channel structures comprise an intervening channel structure between the first and second side surfaces of the block isolation structure (since the block isolation structure comprises the bottom SPS and top SPS in fig. 2, there would be an intervening block channel structure between the two SPSs at the top and bottom, see also fig. 3E).
[claim 16] The semiconductor device of claim 15, wherein the isolation structure further comprises a third word line isolation (one SPS in the center of ST2 of fig. 2, see also fig. 3E) structure between the second block channel structures, wherein the first isolation portion of the plurality of isolation portions extends between the first word line isolation structure and the third word line isolation structure (see above), and wherein the second isolation portion of the plurality of isolation portions extends between the third word line isolation structure and the second word line isolation structure (see above), the block isolation structure comprises a third side surface and a fourth side surface respectively connected to side surfaces of the third word line isolation structure (as can be seen in fig. 2, ISPs of the block isolation structure surrounds side surfaces of the word line isolations SPS, for example the side surface can be either in the D1 or D2 direction in fig. 2), the bit lines comprise a second overlap bit line, which at least partially overlapping the third and fourth side surfaces of the block isolation structure (segments of BL, fig. 3C overlaps MO and ISP), an overlap bit line (segments of BL, fig. 3C overlaps MO and ISP), which at least partially overlaps the first and second side surfaces of the block isolation structure and the second block channel structures comprise a second intervening channel structure, at least partially overlapped by the second overlap bit line (fig. 3B).
[claim 17] The semiconductor device of claim 16, wherein the bit lines further comprise a share bit line (BL bit lines are connected to the control circuitry via TSV in fig. 3B, the share line bit line can be this center BL connected to the other bit lines, [0070]) between the first overlap bit line and the second overlap bit line, the first block channel structures comprise a first sharing channel structure (centermost VS in ST1, fig. 2, 3B) electrically connected to the share bit line, and the second block channel structures comprise a second sharing channel structure (centermost VS in ST2, fig. 2, 3B) electrically connected to the share bit line.
[claim 18] The semiconductor device of claim 17, wherein an angle between the first side surface of the block isolation structure and the side surface of the first word line isolation structure is greater than 90 degrees (angle may be 180 degrees between side surfaces in opposite directions, fig. 2).
[claim 19] An electronic system (fig. 2, 3A-3E), comprising: a main substrate (SUB, fig. 3A-3E); a semiconductor device (CS, fig. 3A-3E) on the main substrate; and a controller (PS, fig. 3A-3E, PS controls the cell array above) on the main substrate and electrically connected to the semiconductor device, wherein the semiconductor device comprises, a gate stack (EL, IL1, fig. 3A-3E) including insulating patterns (IL1, fig. 3A-3E, [0044]) and conductive patterns (EL, fig. 3A-3E, [0044]), which are alternately stacked; bit lines (segments of BL, fig. 3A-3E) on the gate stack; first block channel structures (VS in ST1, fig. 2, 3A-3E) penetrating the gate stack, wherein the first block channel structures are in a first memory block (block of ST1, fig. 2, 3A-3E); second block channel structures (VS in ST2, fig. 2, 3A-3E) penetrating the gate stack, wherein the second block channel structures are in a second memory block (block of ST2, fig. 2, 3A-3E); and an isolation structure (MO, ISP, fig. 2, 3C) penetrating the gate stack, wherein the isolation structure comprises a block isolation structure (MO, ISP, fig. 2, 3C) between the first block channel structures in the first memory block and the second block channel structures (fig. 2),in the second memory block, a first word line isolation structure (one SPS in ST1 in the center of fig. 2, see also fig. 3E) extending in a first direction and between the first block channel structures (fig. 3E) , and a second word line isolation structure (next adjacent SPS in the center of fig. 2, see also fig. 3E) between the first block channel structures and adjacent to the first word line isolation structure (fig. 3E), wherein the second word line isolation structure extends parallel to the first word line isolation structure, wherein the block isolation structure comprises a plurality of isolation portions, wherein a first isolation portion (an arbitrary rectangular portion of the block isolation structure between the first and third word line isolation that extends laterally along its major axis, fig. 2) of the plurality of isolation portions extends in a different direction than a second isolation portion (an arbitrary rectangular portion of the block isolation structure between the second and third word line isolation that extends vertically along its major axis, fig. 2) of the plurality of isolation portions, the bit lines comprise a first overlap bit line at least partially overlapping the block isolation structure (left BL in SER, fig. 3C overlaps MO and ISP), a second overlap bit line (right BL in SER, fig. 3C overlaps MO and ISP) at least partially overlapping the block isolation structure, and a share bit line (center BL in SER, fig. 3C overlaps MO and ISP) arranged between the first overlap bit line and the second overlap bit line, the first block channel structures comprise a first intervening channel structure electrically connected to the first overlap bit line (since the block isolation structure comprises the bottom SPS and top SPS in fig. 2, there would be an intervening block channel structure between the two SPSs at the top and bottom in ST1, see also fig. 3E), and a first sharing channel structure (centermost VS in ST1, fig. 3E) electrically connected to the share bit line, and the second block channel structures comprise a second intervening channel structure (since the block isolation structure comprises the bottom SPS and top SPS in fig. 2, there would be an intervening block channel structure between the two SPSs at the top and bottom in ST2, see also fig. 3E) electrically connected to the second overlap bit line, and a second sharing channel structure (centermost VS in ST2, fig. 3E) electrically connected to the share bit line.
[claim 20] The electronic system of claim 19, and each of the first and second intervening channel structures and the first and second sharing channel structures is between the plurality of isolation portions of the block isolation structure (fig. 2).
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Applicant argues that requiring that the block isolation structure have an first isolation and second isolation portion that extend in different directions would overcome the prior art Jung. However, the term portion refers to any arbitrary portion of the block isolation structure. For example, in fig. 2 of Jung, the first isolation portion could be an arbitrary rectangular portion of the block isolation structure that extends laterally along its major while the second isolation portion could be an arbitrary rectangular portion of the block isolation structure between the second and third word line isolation that extends vertically along its major axis.
The examiner suggests that applicant include limitations that focus on the heart of the invention by requiring the block isolation structure to have a zigzag shape (see fig. 2A of applicant’s drawings).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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