Office Action Predictor
Application No. 18/062,706

ELECTRICAL CONTACT BETWEEN SEPARATED SEMICONDUCTOR LAYERS

Non-Final OA §102§103
Filed
Dec 07, 2022
Examiner
CHOU, JIMMY
Art Unit
3761
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Melexis Technologies NV
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
93%
With Interview

Examiner Intelligence

71%
Career Allow Rate
592 granted / 833 resolved
Without
With
+22.0%
Interview Lift
avg trend
3y 4m
Avg Prosecution
43 pending
876
Total Applications
career history

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
44.0%
+4.0% vs TC avg
§102
16.2%
-23.8% vs TC avg
§112
34.4%
-5.6% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 11-14 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 11/25/2025. Applicant's election with traverse of Group II in the reply filed on 11/25/2025 is acknowledged. The traversal is on the ground(s) that the election is made with traverse, as the current record does not establish that examination of all claimed inventions would present a serious search or examination burden. In particular, it has not been shown that the claimed inventions are independent or distinct … a different analysis than that applicable to a process and its product … It also has not been shown how the apparatus as claimed by Invention II could be used to cut layered vehicle parts. The apparatus as claimed in Invention II is a "semiconductor device" that comprises "a layered stack," and it is not clear how such a device could perform such cutting operations. This is not found persuasive because laser cutting device is capable of materially different process such as a cutting process for cutting a stack vehicle panels for manufacturing purpose. The requirement is still deemed proper and is therefore made FINAL. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the Claim 6 recites “adjacent laser grooves are lasered in the stack” (claim 6). However, claim 1 recites “laser grooving at least one laser groove” (claim 1). Examiner noted that “adjacent laser grooves” directed to fig.3, 240. However, at least one laser groove can be only one groove which directed to fig.2, 240. Both claims 1 and 6 now require adjacent laser grooves and at least one laser groove (hence, i.e., totally at least three grooves) that is not shown in any of the figures or embodiments. must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3 and 6-7 is/are rejected under 35 U.S.C. 102 a1 as being anticipated by Harikai (JP 2019110272 A). Regarding claim 1, Harikai discloses “a method for creating an electrical contact between semiconductor layers which are separated by an isolating connection layer” (fig.4A shows semiconductor layers 11 and 13 are separated by an isolating connection layer 12. Examine noted that creating groove in a semiconductor is to facilitate electrical contacts and it is a well-known process), the method comprising: -providing “a layered stack” (10 includes 11, 12 and 13) comprising “at least a first semiconductor layer” (13), “an isolating connection layer” (12), and “a second semiconductor layer” (11), wherein “the isolating connection layer is between the first semiconductor layer and the second semiconductor layer” (12 is between 13 and 11), -“laser grooving at least one laser groove in the layered stack through the first semiconductor layer and the isolating connection layer and partly in the second semiconductor layer” (fig.4A shows laser grooving (i.e., L1, L2) in the layered stack (i.e., Fig.4B, the groove at 11, 12 and 13) through the first semiconductor layer and the isolating connection layer and partly in the second semiconductor layer), “thereby obtaining a recrystallized conductive layer at an edge of the layered stack, which connects the first semiconductor layer and the second semiconductor layer” (fig.4B shows the first semiconductor layer and the second semiconductor layer. Examiner noted that “producing molten material is an inherent and expected phenomenon during standard laser cutting of a semiconductor layer”. Examiner noted that “recrystallized conductive layer” refers to the molten semiconductor material of first layer may trickle over the connection layer due to gravity before recrystallizing during solidification. On page 5, i.e., The semiconductor layer is made of, for example, silicon (Si), gallium arsenide (GaAs), galliumnitride (GaN), silicon carbide (SiC) or the like. Examiner noted that semiconductor layer can be gallium arsenide (GaAs) which is conductive), wherein “the recrystallized conductive layer is at least obtained from molten material of the first semiconductor layer” (As noted above, during laser grooving, the molten material may trickle over connection layer from the first semiconductor layer due to gravity), and wherein “after the laser grooving a remainder of the second semiconductor layer is still present” (fig.4B shows safter the laser grooving a reminader (the top portion of 11 has a recess) of the second semiconductor layer 11), -“cutting the remainder of the second semiconductor layer” (fig.4C shows cutting remainder of the second semiconductor layer 11 so that the middle portion of 11 is being completely cut off). Regarding claim 2, Harikai discloses “during the laser grooving the focal point of the laser is controlled such that laser grooving is done up to substantially a same depth as the depth of the isolating connection layer” (fig.4B shows during the laser grooving the focal point of the laser is controlled such that laser grooving is done up to substantially a same depth as the depth of the isolating connection layer in order to create a groove at substantially a same depth as the connection layer 12). Regarding claim 3, Harikai discloses “the first and second semiconductor layer of the provided layered stack are silicon layers, GaAs layers, SiC layers, GaN layers” (On page 5, i.e., The semiconductor layer is made of, for example, silicon (Si), gallium arsenide (GaAs), galliumnitride (GaN), silicon carbide (SiC) or the like) or a combination thereof. Regarding claim 6, Harikai discloses “adjacent laser grooves are lasered in the stack and wherein cutting the remainder of the second semiconductor layer is done between the adjacent laser grooves” (fig.6 shows laser grooves Ro (hence, i.e., each cutting line is a groove). Examiner noted that one of grooves is in between adjacent grooves. Fig.4B and fig.4C shows the cutting process for cutting the remainder of the second semiconductor layer). Regarding claim 7, Harikai discloses “the laser grooving of the adjacent laser grooves is done such that in a pair of adjacent laser grooves the adjacent laser grooves are parallel” (fig.6 shows laser grooves Ro (hence, i.e., each cutting line is a groove), the adjacent laser grooves is the cutting lines which are parallel). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harikai (JP 2019110272 A) in view of Ryu et al. (US 8,993,924). Regarding claim 4, Harikai is silent regarding doping the bonding surface of the first and/or the second semiconductor layer with an n-type or p-type dopant. Ryu et al. teaches “doping the bonding surface of the first and/or the second semiconductor layer with an n-type or p-type dopant” (col.4 at lines 60-67, i.e., N-GaN 221 … and a P-GaN layer 223. Examiner noted that n-type GaN semiconductor layer must include n-type dopant includes the surface intended for bonding to ensure proper electrical conductivity and device functionality). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Harikai with Ryu et al., by replacing Harikai’s semiconductor material according to Ryu et al.’s semiconductor material, to provide a functional device. One skilled in the art would have found it obvious to substitute Harikai semiconductor material with Ryu et al.’s semiconductor material are both recognized by the art for the same purpose of providing semiconductor material. MPEP 2144.06. Claim(s) 5 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harikai (JP 2019110272 A) in view of Murai (WO 2015140849). Regarding claim 5, Harikai teaches a thickness of the isolation layer of the provided layer stack. Harikai is silent regarding the thickness of the layer is between 3 and 6 nm. Murai teaches “the thickness of the layer is between 3 and 6 nm” (on page 4, The thickness of the well layer is preferably about 1 nm to 5 nm. As set forth in MPEP 2144.05, in the case where the claimed range “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Harikai with Murai, by modifying Harikai’s thickness of layer according to Murai’s thickness of layer, to provide a desired thickness of layer based on design specification (on page 5) as taught by Murai. Regarding claim 8, Harikai teaches the laser grooving of the adjacent laser grooves is done such that in a pair of adjacent grooves a distance between the adjacent laser grooves ranges between a distance. Harikai is silent regarding “a distance ranges between 0 and 60 µm”. Murai teaches “a distance ranges between 0 and 60 µm” (on page 8, i.e., the widthL2b of the first groove 31b and the width L2a of the second groove 31a are set to 10 μm). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Harikai with Murai, by setting a desired distance based on the chip size (on page 8) as taught by Murai. Regarding claim 9, Harikai discloses “the laser grooving is done in at least two passes” (Harikai, fig.4B-4C shows laser grooving is done at least two passes to cut through layer 11). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harikai (JP 2019110272 A) in view of Design Choice. Regarding claim 10, Harikai discloses “the laser grooving and the cutting is done in a direction fig.4B-4C and fig.6). Harikai is silent regarding the laser grooving and the cutting is done in two different directions. However, the applicant has not disclosed that the laser grooving and the cutting is done in two different directions solves any stated problem or provides any unexpected results. The examiner notes that the laser grooving and the cutting is done in two different directions just to cut workpiece. As such, the examiner considers this limitation to be a design choice. Therefore, it would have been obvious as a matter of design choice to modify Harikai to perform the laser grooving and the cutting is done in two different directions as proposed by the applicant, since the applicant has not disclosed that the laser grooving and the cutting is done in two different directions solves any stated problem or provides any unexpected results and it appears that Harikai’s the laser grooving and the cutting is done i would perform equally well, since the laser grooving and the cutting is done in two different directions merely to cut workpiece. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIMMY CHOU whose telephone number is (571)270-7107. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helena Kosanovic can be reached at (571) 272-9059. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JIMMY CHOU/Primary Examiner, Art Unit 3761
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Prosecution Timeline

Dec 07, 2022
Application Filed
Jan 07, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
93%
With Interview (+22.0%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 833 resolved cases by this examiner