DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2013/0126964).
[claim 1] A semiconductor device (figs. 1, 3p), comprising: a bit line (27, fig. 1, 3p, [0023]) extending in a first direction; a semiconductor pattern (12, fig. 1, 3p, [0029]) on the bit line, the semiconductor pattern comprising first and second vertical portions (portions of 12 on the opposite sides of 34/40, fig. 1,3p), which are opposite to each other in the first direction, the semiconductor pattern including a horizontal portion (horizontal portion of 12 below 34/40 connecting the two vertical portions, fig. 1, 3p) connecting the first and second vertical portions; first and second word lines (multiple 40s, fig. 1, 3p, [0023]) on the horizontal portion adjacent to the first and second vertical portions, respectively; and a gate insulating pattern (34, fig. 1, 3p, [0023]) between the first vertical portion and the first word line and between the second vertical portion and the second word line, wherein a bottom surface of the horizontal portion is located at a height that is lower than to an uppermost surface of the bit line (fig. 3p (a)(b) shows a side and orthographic view of the device in fig. 1, as can be seen a portion of the horizontal portion below 34/40 is below the top surface of the bit line 27).
[claim 3] The semiconductor device of claim 1, wherein at least a portion of the horizontal portion is received in an upper portion of the bit line (fig. 1,3p).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2013/0126964) in view of Chan (US 2006/0175609).
Lee discloses the transistor semiconductor device of claims 1 and 3 and a passivating insulation film (28, fig. 1) between the semiconductor patterns (12, fig. 1) may be made of a nitride film [0036][0031]. Lee, however, does not expressly disclose that the passivating insulation film 28 may be made of a hydrogenated amorphous silicon nitride (a-SiN.sub.x:H).
Chan discloses a transistor semiconductor device wherein the passivating insulation film may be made of a hydrogenated amorphous silicon nitride (a-SiN.sub.x:H)[0060].
It would have been obvious to one of ordinary skill in the art before the time of filing to have made Lee’s passivation insulation out of a hydrogenated amorphous silicon nitride (a-SiN.sub.x:H) in order to provide a means to form the nitride film. Moreover, hydrogenated amorphous silicon nitride (a-SiN.sub.x:H) can passivate dangling bonds and reduce defects.
With this modification Lee discloses:
[claim 2] The semiconductor device of claim 1, wherein the semiconductor pattern comprises a first semiconductor pattern (12, fig. 1,3p) and a second semiconductor pattern (adjacent 12 to first 12, fig. 1,3p) adjacent to each other in the first direction, the semiconductor device further comprises a lower pattern (28, fig. 1) between the first and second semiconductor patterns, and the lower pattern contains at least one of hydrogen and deuterium (upon modification the nitride layer is hydrogenated).
[claim 4] The semiconductor device of claim 3, wherein the semiconductor pattern comprises a first semiconductor pattern (12, fig. 1,3p) and a second semiconductor pattern (adjacent 12 to first 12, fig. 1,3p) adjacent to each other in the first direction, the semiconductor device further comprises an auxiliary pattern (28,fig. 1) between the first and second semiconductor patterns, the auxiliary pattern comprises at least one of a blocking pattern (upper portion of 28, fig. 1) and a lower pattern (lower portion of 28, fig. 1), the blocking pattern comprises at least one of insulating (28 is an insulating film) and conductive materials, and the lower pattern contains at least one of hydrogen and deuterium (upon modification the nitride layer is hydrogenated).
[claim 5] The semiconductor device of claim 4, wherein a bottom surface of the horizontal portion is located at a height that is lower than or equal to a lowermost surface of the auxiliary pattern (bottom of 28 in fig. 1 is at the same height as the bottom of the horizontal portion of 12 in fig. 1).
[claim 6] The semiconductor device of claim 4, wherein the auxiliary pattern comprises both of the blocking pattern and the lower pattern (fig. 1), and the lower pattern is between the bit line and the blocking pattern (fig. 1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAR MOVVA whose telephone number is (571)272-9009. The examiner can normally be reached Monday-Friday 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMAR MOVVA/Primary Examiner, Art Unit 2898
Prosecution Insights