Prosecution Insights
Last updated: July 17, 2026
Application No. 18/062,931

DISPLAY APPARATUS AND MULTI SCREEN DISPLAY APPARATUS INCLUDING THE SAME

Final Rejection §103
Filed
Dec 07, 2022
Priority
Dec 09, 2021 — RE 10-2021-0175903
Examiner
AUTORE JR, MARIO ANDRES
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
2 (Final)
58%
Grant Probability
Moderate
3-4
OA Rounds
2m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allowance Rate
25 granted / 43 resolved
-9.9% vs TC avg
Strong +32% interview lift
Without
With
+31.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 10m
Avg Prosecution
21 currently pending
Career history
82
Total Applications
across all art units

Statute-Specific Performance

§103
95.0%
+55.0% vs TC avg
§102
4.3%
-35.7% vs TC avg
§112
0.7%
-39.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 43 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on April 27th, 2026 has been received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Response to Amendments Acknowledgment is made of the amendment filed April 3rd, 2026 (“A...”), in which: claims 1 and 15 are amended; no new claims are added; no claims are canceled; and the rejection of the claims are traversed. Claims 1 – 23 are currently pending an Office Action on the merits as follows, wherein claims 2 – 10 and 19 – 23 are withdrawn from consideration. Response to Arguments Applicant’s arguments with respect to claims 1 and 11 – 18 have been fully considered but are moot in view of the new grounds of rejection. Rejections Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20080062264 A), and further in view of Dong et al. (US 20260068498 A1). Regarding independent claim 1, Kim teaches a display apparatus comprising: a substrate (Fig. 1; substrate 12) having a display portion (Fig. 5; active area AA); a plurality of pixels (Fig. 5; plurality of pixels in active area AA) disposed in the display portion (Fig. 5); pad portions (Fig. 5; circuit blocks 148) spaced apart from the plurality of pixels (Fig. 5) and disposed at an edge portion of one side of the substrate (Fig. 5); a dummy portion (Fig. 5; dummy unit DA) adjacent to the display portion (Fig. 5) and disposed between the pad portion (Fig. 5) and the plurality of pixels (Fig. 5); a pad connection line (Fig. 5; gate wiring 113) crossing the dummy portion (Fig. 5; gate wiring 113) and electrically connected to each of the pad portions (Fig. 5); a connection portion (Fig. 5; dummy transistor T1) electrically connecting the dummy portion with the pad connection line (see p. 7; par. 8 of provided translation); and ... wherein the dummy portion includes a first dummy line (Fig. 5; second dummy wire 162) ... and a second dummy line (Fig. 5; second dummy wire 162) ... However, Kim remains silent regarding the display device including: ... a dam disposed at the edge portion of the substrate to surround the display portion, wherein the dummy portion includes a first dummy line disposed between the pad portion and the dam and a second dummy line disposed between the first dummy line and the dam. However, in the same field of endeavor, Dong (US 20260068498 A1) teaches a display device including a dam (Figs. 4 – 6; at least second block portion 111b2 of the block structure 111) and a pad portion (Fig. 2; examiner is interpreting The first signal line 103, second signal line 109, and electrode structure 105 to be/include a pad portion. See [0060] – [0061] and [0103] – [0104]). Further, Dong teaches a dam disposed at the edge portion of the substrate to surround the display portion (Fig. 6). Including Dong’s dam structure to the display device of Kim yields the structure wherein the dummy portion includes a first dummy line disposed between the pad portion and the dam and a second dummy line disposed between the first dummy line and the dam. Dong teaches the benefit of moisture protection (see at least abstract of Dong as well as [0087] – [0090]), which would be motivation for including such a dam structure into the display substrate of Kim. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the display substrate of Kim to include Dong’s edge of substrate dam, such that the dummy portion includes a first dummy line disposed between the pad portion and the dam and a second dummy line disposed between the first dummy line and the dam, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Dong’s substrate is comparable to Kim’s substrate because they are substrates for display apparatus. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the display substrate of Kim to include Dong’s edge of substrate dam, such that the dummy portion includes a first dummy line disposed between the pad portion and the dam and a second dummy line disposed between the first dummy line and the dam with the predictable result of providing protection to device circuitry. Claims 11 and 15 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20080062264 A), and further in view of Dong et al. (US 20260068498 A1), Sasaki et al. (US 6671134 B1). Regarding dependent claim 11, Kim, further in view of Dong, teach the display apparatus of claim 1, further comprising: a cross area where the dummy portion and the pad connection line cross each other (Fig. 5; see area where the dummy lines and gate wiring 113 overlap); and a non-cross area (Fig. 5; area covered by transistor T1) adjacent to the cross area (Fig. 5), in which the dummy portion and the pad connection line do not cross each other (Fig. 5; dummy lines are connected to the source of transistor T1, and gate wiring 113 is connected to the drain of transistor T1), … However, Kim remains silent regarding the display apparatus: … wherein the pad connection line includes a protruded line protruded toward the non-cross area, and wherein the connection portion electrically connects the dummy portion with the protruded line on the protruded line. However, within the art of semiconductors, Sasaki teaches a structure for forming electrical connections between elements of a semiconductor device; wherein upper conductors 506 (Fig. 50A), i.e., a pad connection line, includes conductive patches 508, i.e., a protruded line protruded toward the non-cross area (Fig. 50B), wherein the connection portion electrically connects the dummy portion (Fig. 50B; lower conductors 501) with the protruded line on the protruded line (Figs. 50A – 50B). Examiner asserts that such a wiring connection may be adopted into/ used to modify other semiconductor devices as a means of forming connective conductive pathways; i.e., as Kim discloses that the transistor T1 connects the dummy wirings to the gate wiring 113 (p. 7; par. 8 of provided translation), Sasaki’s connective via may be used to alter/replace the dummy transistor T1 that forms the connection between dummy wirings and gate wiring 113. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kim’s display apparatus, further in view of Dong, to include a connection between the conductive wires via a non-cross area, as disclosed by Sasaki, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Sasaki’s non-cross area connection is comparable to Kim’s dummy transistor T1 because dummy transistor T1 does not serve a function other than connecting the dummy wiring to the gate wiring 113. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Kim’s display apparatus to include a connection between the conductive wires via a non-cross area, as disclosed by Sasaki, with the predictable result of connecting a dummy wire to a pad connection line. Regarding dependent claim 15, Kim, further in view of Dong and Sasaki, teach the display apparatus of claim 11, wherein the pad portion includes a first pad member (Fig. 5; the first circuit block 148) and a second pad member (Fig. 5; the second circuit block 148 under the first), which are disposed to be spaced apart from each other at an edge portion of the substrate (Fig. 5), wherein the pad connection line includes a first pad connection line (Fig. 5; see the gate wiring 113 associated with the first pad member) electrically connected to the first pad member and a second pad connection line (Fig. 5; see the gate wiring 113 associated with the second pad member) electrically connected to the second pad member, wherein the first pad connection line includes a first protruded line protruded toward the non-cross area (Yielded through the combination of Kim, further in view of Sasaki), wherein the second pad connection line includes a second protruded line protruded toward the non-cross area (Yielded through the combination of Kim, further in view of Sasaki), wherein the first dummy line includes a first dummy electrode electrically connected to the first protruded line on the first protruded line (Surface of the dummy line in contact with first protruded line yielded through the combination of Kim, further in view of Sasaki), and wherein the second dummy line includes a second dummy electrode electrically connected to the second protruded line on the second protruded line (Surface of the dummy line 162 in contact with second protruded line yielded through the combination of Kim, further in view of Sasaki). Regarding dependent claim 16, Kim, further in view of Dong and Sasaki, teach the display apparatus of claim 15, wherein the pad portion further includes a third pad member (Kim: Fig. 5; the third circuit block 148 under the second) spaced apart from the second pad member at the edge portion of the substrate (Kim: Fig. 5), wherein the pad connection line further includes a third pad connection line (Fig. 5; see the gate wiring 113 associated with the third pad member) electrically connected to the third pad member, wherein the first protruded line is disposed between the first pad connection line and the second pad connection line (Yielded through the combination of Kim, further in view of Sasaki), and wherein the second protruded line is disposed between the second pad connection line and the third pad connection line (Yielded through the combination of Kim, further in view of Sasaki). Claims 12 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20080062264 A), and further in view of Dong et al. (US 20260068498 A1), Sasaki et al. (US 6671134 B1) and Eom et al (US 20200251658 A1). Regarding dependent claim 12, Kim, further in view of Dong and Sasaki, teach the display apparatus of claim 11, further comprising: … a second middle insulating layer (Sasaki: Fig. 50A; insulating film 502) disposed between the dummy portion and the connection portion (Sasaki: Fig. 50A), … wherein the second middle insulating layer includes a second contact hole (Sasaki: Fig. 50A; hole accommodating coupling plug 507) for electrically connecting the dummy portion with the connection portion (Sasaki: Fig. 50A), and However, Kim remains silent regarding the display apparatus further comprising: a first middle insulating layer disposed between the connection portion and the protruded line; and … wherein the first middle insulating layer includes a first contact hole for electrically connecting the connection portion with the protruded line, … wherein the first contact hole is disposed to be spaced apart from the second contact hole on the protruded line. However, within the art of semiconductors, Eom discloses an image sensor, which is a device with many similarities to a display apparatus, in the way that there are transistor structures, dummy features, pixels, and pad regions which are connected through wires. Referring to Figs. 8 – 10B, Eom teaches a peripheral region PR with pads, e.g., first pad 330 and second pad 340, wherein the pads are connected to connection lines, e.g., first connection line CL1 and second connection line CL2 (Figs. 9A – 9B), such that connections lines CL1 and CL2 may be considered as pad connection lines. Further, these connection lines extend into a dummy region DR and connect to a plurality of third connection lines CL3 (Figs. 9A – 9B), which further connect to lower electrodes 230; thus, examiner is asserting that the connection line CL3 serves a similar function as the protruded line of Kim and Sasaki. Further the lower electrodes 230 serve a function of testing alignment of device layers during a formation process ([0049] – [0054]); thus, examiner is interpreting the lower electrodes 230 in the dummy region DR to be dummy portions. Thus, Eom’s structure allows for a pad connection lines to cross a dummy portion (Fig. 9), such that (in view of the protruded line yielded from Kim and Sasaki) the protruded line may be separated from the pad connection lines by an insulating layer, e.g., first interlayered insulating layer 140 (Fig. 9A). Thus, Eom’s disclosure may be used to modify the display apparatus of Kim, further in view of Sasaki, to such that the layers on which the pad connection lines, dummy portions, and protruded lines may be changed to yield the display apparatus wherein a first middle insulating layer (Eom: Fig. 9A; first interlayered insulating layer 140) disposed between the connection portion and the protruded line (Yielded from the combination of Kim and Sasaki, further in view of Eom’s Fig. 9A); and wherein the first middle insulating layer includes a first contact hole (Eom: Fig. 9A; contact hole accommodating lower contact plug BCP3) for electrically connecting the connection portion with the protruded line (Yielded from the combination of Kim and Sasaki, further in view of Eom’s Fig. 9A). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the display apparatus of Kim, further in view of Dong and Sasaki, to include insulating layers between conductive features, as disclosed by Eom, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Eom’s insulating layers are comparable to the insulating layers separating conductive structures in the disclosures of Kim and Sasaki because providing insulating layers between conductive structures is known in the art to prevent undesirable effects and prevent loss of device function. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the display apparatus of Kim, further in view of Sasaki, to include insulating layers between conductive features, as disclosed by Eom, with the predictable result of insulating the connection portion and the protruded line. Regarding dependent claim 13, Kim, further in view of Dong, Sasaki, and Eom, teach the display apparatus of claim 12; however, Kim remains silent wherein the connection portion includes: a first connection line that is in contact with the protruded line and extended from the first contact hole to a space between the first contact hole and the second contact hole; and a second connection line electrically connected to the first connection line and extended to the second contact hole to be in contact with the dummy portion, and wherein the first connection line is in contact with the second connection line between the first contact hole and the second contact hole. However, within the art of semiconductors, Eom discloses an image sensor, which is a device with many similarities to a display apparatus, in the way that there are transistor structures, dummy features, pixels, and pad regions which are connected through wires. Referring to Fig. 9A, Eom teaches contact holes that are spaced apart in the third direction (Fig. 9A; contact holes accommodating lower contact plug BCP3, i.e., a first contact hole, and upper contact plugs TCP, i.e., a second contact hole). Eom teaches connection portions extending through these contact holes to connect the pad connection line with the lower electrodes 230, i.e., dummy electrodes; such that Eom’s disclosure may be used to modify the disclosure of Kim, further in view of Sasaki, to yield a display apparatus wherein: a first connection line (Eom: Fig. 9A; penetration electrode 120) that is in contact with the protruded line (yield from the combination of Kim, further in view of Sasaki and Eom) and extended from the first contact hole to a space between the first contact hole and the second contact hole (Eom: Fig. 9A); and a second connection line (Eom: Fig. 9A; upper contact plug TCP) electrically connected to the first connection line and extended to the second contact hole to be in contact with the dummy portion (Eom: Fig. 9A), and wherein the first connection line is in contact with the second connection line between the first contact hole and the second contact hole (Eom: Fig. 9A). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the display apparatus of Kim, further in view of Dong, Sasaki, and Eom, to include Eom’s first and second connection lines extending between contact holes in the insulating layers, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Eom’s conductive layers are comparable to the conductive layers of Kim and Sasaki because both disclosures teach conductive layers formed on different layers within the display apparatus which are then connected through contact holes and conductive pathways filling the holes. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the display apparatus of Kim, further in view of Sasaki and Eom, to include Eom’s first and second connection lines extending between contact holes in the insulating layers, with the predictable result of connecting conductive layers that are separated vertically by insulating layers. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20080062264 A), and further in view of Dong et al. (US 20260068498 A1), Sasaki et al. (US 6671134 B1), Eom et al (US 20200251658 A1), and Sun et al. (US 20150311232 A1). Regarding dependent claim 14, Kim, further in view of Dong, Sasaki, and Eom, teach the display apparatus of claim 12; however, Kim remains silent wherein the first middle insulating layer includes a buffer layer disposed on the protruded line and an interlayer insulating layer disposed on the buffer layer, wherein the second middle insulating layer includes a passivation layer disposed on the interlayer insulating layer, wherein the first contact hole includes a first via hole passing through the buffer layer and a second via hole passing through the interlayer insulating layer disposed on the first via hole, wherein the second contact hole includes a third via hole passing through the passivation layer disposed on the second via hole, wherein the first via hole overlaps the second via hole, and wherein the third via hole does not overlap the second via hole. However, in the same field of endeavor, Sun teaches an array substrate that includes a buffer layer 102, gate insulating layer 111, an intermediate dielectric layer 112, and a passivation layer 114 (Fig. 12); such that Sun teaches a display apparatus including: the first middle insulating layer (Fig. 12; gate insulating layer 111 + buffer layer 102) includes a buffer layer (Fig. 12; buffer layer 102) … and an interlayer insulating layer (Fig. 12; gate insulating layer 111) disposed on the buffer layer, wherein the second middle insulating layer (Fig. 12; intermediate dielectric layer 112 + a passivation layer 114) includes a passivation layer (Fig. 12; passivation layer 114) disposed on the interlayer insulating layer, wherein the first contact hole includes a first via hole passing through the buffer layer and a second via hole passing through the interlayer insulating layer disposed on the first via hole (Fig. 12), wherein the second contact hole includes a third via hole passing through the passivation layer disposed on the second via hole (Fig. 12), wherein the first via hole overlaps the second via hole (Fig. 12), and wherein the third via hole does not overlap the second via hole (Fig. 12). Thus, examiner asserts that Sun’s distinct insulating layers are in the same order as claimed by the instant invention, and can be used to modify the display apparatus of Kim, further in view of Dong, Sasaki, and Eom, to yield the display apparatus wherein the first middle insulating layer includes a buffer layer disposed on the protruded line and an interlayer insulating layer disposed on the buffer layer, wherein the second middle insulating layer includes a passivation layer disposed on the interlayer insulating layer, wherein the first contact hole includes a first via hole passing through the buffer layer and a second via hole passing through the interlayer insulating layer disposed on the first via hole, wherein the second contact hole includes a third via hole passing through the passivation layer disposed on the second via hole, wherein the first via hole overlaps the second via hole, and wherein the third via hole does not overlap the second via hole. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the display apparatus of Kim, further in view of Dong, Sasaki, and Eom, to include Sun’s insulating layers including a buffer layer and a passivation layer, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, the display apparatus of Kim, further in view of Dong, Sasaki, and Eom, as modified by Sun’s insulating layers including a buffer layer and a passivation layer can yield a predictable result of protecting the fragile device components disposed between the buffer layer and passivation layer since the buffer layer and passivation layers are formed of materials resistant to materials and energy that may damage the device. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20080062264 A), and further in view of Dong et al. (US 20260068498 A1), Sasaki et al. (US 6671134 B1), and Hao (US 20190257875 A1). Regarding dependent claim 17, Kim, further in view of Dong and Sasaki, teach the display apparatus of claim 15; however, Kim remains silent wherein a width of the first dummy electrode overlapped with the first protruded line is wider than that of the first dummy electrode overlapped with the cross area. However, in the same field of endeavor, Hao teaches forming dummy (dummy line 4) and signal lines (signal line 5) that overlap (Figs. 3 and 5), wherein a width of the first dummy electrode not overlapped with the cross area is wider than that of the first dummy electrode overlapped with the cross area (Figs. 3 and 5). Hao’s teaching may be used for the modification of the display apparatus of Kim and Sasaki to yield the display apparatus wherein a width of the first dummy electrode overlapped with the first protruded line is wider than that of the first dummy electrode overlapped with the cross area. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kim’s dummy electrode to include varying widths, as disclosed by Hao, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Hao’s dummy electrodes of varying width are comparable to Kim’s dummy line because they are both disclosed to be dummy lines. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Kim’s dummy electrode to include varying widths, as disclosed by Hao, with the predictable result of forming a display apparatus wherein a width of the first dummy electrode overlapped with the first protruded line is wider than that of the first dummy electrode overlapped with the cross area. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20080062264 A), and further in view of Dong et al. (US 20260068498 A1), Sasaki et al. (US 6671134 B1), Hao (US 20190257875 A1), and Yen (US 20160103509 A1). Regarding dependent claim 18, Kim, further in view of Dong, Sasaki, and Hao, teach the display apparatus of claim 17; however, Kim remains silent wherein the second dummy electrode includes a first sub-dummy electrode disposed to face the first protruded line and a second sub-dummy electrode electrically connected to the first sub-dummy electrode, and wherein a width of the first sub-dummy electrode is narrower than that of the second sub-dummy electrode. However, in the art of semiconductors, Yen teaches a structure for dummy electrodes (Fig. 5; dummy electrode 152a). Considering two dummy electrode 152 that extend in parallel, it is seen in Yen’s Fig. 5 that the dummy electrodes have a zig zag shape such that as one dummy electrode extends away from the other dummy electrode, the other dummy electrode extends towards the one dummy electrode. This relative shape/feature is what the examiner best understands the phrase “disposed to face” in relationship to the instant Fig. 7. Yen’s zig zag shape also corresponds to a change in width, such that the shortest widths of Yen’s dummy electrodes are along the crease of the dummy electrodes where there is a corresponding direction change in the X-direction (Yen: Fig. 5). Therefore, Yen’s zig zag pattern may be used to modify the display apparatus of Kim, further in view of Dong, Sasaki, and Hao, to yield the display apparatus wherein the second dummy electrode includes a first sub-dummy electrode (Yen: Fig. 5; portion of dummy electrode 152a about a crease that extends away from another dummy electrode152a immediately to the left of it) disposed to face the first protruded line (Yielded through the combination of Kim, Dong, Sasaki, and Hao) and a second sub-dummy electrode (Yen: Fig. 5; portion of dummy electrode 152a about a crease, connected to the first sub-dummy electrode, and extends away from another dummy electrode152a immediately to the left of it) electrically connected to the first sub-dummy electrode, and wherein a width of the first sub-dummy electrode is narrower than that of the second sub-dummy electrode (Fig. 5 of Yen and Hao’s Fig. 5). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kim’s dummy electrode, further in view of Hao, to include varying widths, as disclosed by Yen, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Yen’s dummy electrodes of varying widths are comparable to Kim’s dummy line because they are both disclosed to be dummy lines. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Kim’s dummy electrode to include varying widths, as disclosed by Yen, with the predictable result of forming a display apparatus wherein the second dummy electrode includes a first sub-dummy electrode disposed to face the first protruded line and a second sub-dummy electrode electrically connected to the first sub-dummy electrode, and wherein a width of the first sub-dummy electrode is narrower than that of the second sub-dummy electrode. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 20210217841 A1 previously relied on. US 20090021166 A1 considered for layout shown in at least Fig. 5. US 20220406978 A1 considered for teachings of areas where dummy lines and pad connections lines are disposed, e.g., Fig. 16. US 20160285044 A1 for similar order of features from the edge of the display substrate to the display area DA. US 20190250746 A1 considered for various electrode shapes. US 11522038 B2 considered for at least Figs. 3, 5, and 8 – 13. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARIO A. AUTORE JR. Examiner Art Unit 2897 /MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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Prosecution Timeline

Dec 07, 2022
Application Filed
Jan 28, 2026
Non-Final Rejection mailed — §103
Apr 03, 2026
Response Filed
Jun 30, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
58%
Grant Probability
90%
With Interview (+31.8%)
3y 10m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 43 resolved cases by this examiner. Grant probability derived from career allowance rate.

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