DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Currently, claims 1-20 are pending in the application. Claims 1,5,7, 12 & 16 are amended.
Response to Arguments / Amendments
Applicant’s arguments have been fully considered, but they are not persuasive, see discussion below.
Rejections under 35 U.S.C. § 103:
Applicants respectfully note that the cited portion of Lou is silent regarding "a bit line ... [comprising] sub-bit lines respectively connected to the ferroelectric memories included in corresponding ones of the plurality of memory cells connected to the bit line ... and is configured such that each of the sub-bit lines of the bit line receives the same applied input."
As to the above argument, Boybat discloses a neural network device with phase change memory devices, develop a comprehensive model and demonstrate via simulations the effectiveness of the concept for both spiking and non-spiking neural network (Abstract) and plurality of bit lines extending in a second direction intersecting the first direction; and a plurality of memory cells at points where the plurality of word lines and the plurality of bit lines intersect implemented as "In the non-differential architecture, by placing the devices that constitute a single synapse along the bit lines of a crossbar, it is possible to sum up the currents using Kirchhoff's law and obtain the total synaptic current without the need for any additional circuitry (Page 3, Fig. 1).
LUO teaches at least two ferroelectric memories connected in parallel along a corresponding word line of the plurality of word lines, in the dielectric layer 320 made of a material having a ferroelectric property and the bit lines 501 of the plurality of symmetrical memory cells 100 in the memory cell array group 110a of the neural network layer 110 are input to the input end In of the interface module 200 at another end of the memory cell array group 110a, the positive output terminal Out of the interface module 200 is input to the positive word line 301 of the symmetrical memory cell 100 at one end of the memory cell array group at a corresponding position of the next level neural network layer 120 ([0061], FIG. 3B [0074], FIG. 4).
LUO also teaches sub-bit lines respectively connected to the ferroelectric memories included in corresponding ones of the plurality of memory cells connected to the bit line with the memory cell array group 110a, a plurality of symmetric memory cells 100 are arranged in the first direction. Each symmetric memory unit 100 is connected to the interface module 200 through the bit line BL501 for controlling an input of each symmetric memory cell 100 to the interface module 200 ([0048], FIG. 1A-FIG. 2B;[0069], FIG. 1A, FIG. 1B and FIG. 4 with each of the sub-bit lines of the bit line receives the same applied input ([0071]).
It should be further noted that Applicant has not presented any specific arguments with regards to the rejections of the dependent claims.
Accordingly, Examiner maintains the rejection with regards to above arguments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Boybat et al. ("Neuromorphic Computing with Multi- Memristive Synapses", NATURE COMMUNICATIONS, vol. 9, no. 1, 28 June 2018, hereinafter Boybat) in view of LUO et al. (US 20230267990, hereinafter LUO).
Regarding Claim 1, Boybat discloses a neural network device (Abstract, phase change memory devices, develop a comprehensive model and demonstrate via simulations the effectiveness of the concept for both spiking and non-spiking neural network; Introduction, hardware implementations of deep neural networks) comprising:
a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction intersecting the first direction; and a plurality of memory cells at points where the plurality of word lines and the plurality of bit lines intersect (Page 3, Fig. 1, "In the non-differential architecture, by placing the devices that constitute a single synapse along the bit lines of a crossbar, it is possible to sum up the currents using Kirchhoff's law and obtain the total synaptic current without the need for any additional circuitry):
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Boybat does not explicitly disclose wherein each of the plurality of memory cells comprises at least two ferroelectric memories connected in parallel along a corresponding word line of the plurality of word lines.
LUO teaches wherein each of the plurality of memory cells comprises at least two ferroelectric memories connected in parallel along a corresponding word line of the plurality of word lines ([0061], FIG. 3B, in the dielectric layer 320 made of a material having a ferroelectric property; [0074], FIG. 4, the bit lines 501 of the plurality of symmetrical memory cells 100 in the memory cell array group 110a of the neural network layer 110 are input to the input end In of the interface module 200 at another end of the memory cell array group 110a, the positive output terminal Out of the interface module 200 is input to the positive word line 301 of the symmetrical memory cell 100 at one end of the memory cell array group at a corresponding position of the next level neural network layer 120),a bit line, of the plurality of bit lines, comprises sub-bit lines respectively connected to the ferroelectric memories included in corresponding ones of the plurality of memory cells connected to the bit line ([0017], one end of the second inverter is connected to the working voltage VDD, another end of the second inverter is grounded to the VGND, and the output end of the second inverter is connected to a positive word line of a next level neural network layer adjacent to the each level of the neural network layer; [0048], FIG. 1A-FIG. 2B;[0069], FIG. 1A, FIG. 1B and FIG. 4, memory cell array group 110a, a plurality of symmetric memory cells 100 are arranged in the first direction. Each symmetric memory unit 100 is connected to the interface module 200 through the bit line BL501 for controlling an input of each symmetric memory cell 100 to the interface module 200) and is configured such that each of the sub-bit lines of the bit line receives the same applied input ([0071]When the weight value stored in the symmetric memory cell 100 is the same as the input, the bit line BL501 is charged, and when the weight value stored in the symmetric memory cell 100 is different from the input, the bit line 501 is discharged. When there are more symmetric memory cells 100 on the bit line 501 that are the same as the input, an output of the bit line is 1).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of memory cells comprises at least two ferroelectric memories as taught by LUO ([0061]) into the neural network device of Boybat in order to provide systems for using first control transistor for connecting with the latter complementary structure, and thus enables to ensure fast data growth and ensures the data processing timeliness (LUO, [0004]).
Regarding Claim 2, Boybat in view of LUO discloses the neural network device of claim 1,
Boybat discloses wherein the plurality of memory cells is configured such that synthesis conductance of the ferroelectric memories, included in each of the plurality of memory cells, corresponds to a weight stored in a corresponding one of the plurality of memory cells, and the weight stored in each of the plurality of memory cells is linearly updatable (FIG. 1, N memory devices could be used, with each device programmed to the maximum (fully potentiated) or minimum (fully depressed) conductance states to represent a number in binary format and each device needs to be read independently, accomplished by reading each of the N bits one by one, or alternatively, N amplifiers could be used to read the N bits in parallel and then the desired weight update should be done with prior knowledge of the stored weight).
Regarding Claim 3, Boybat in view of LUO discloses the neural network device of claim 1,
Boybat discloses wherein the neural network device is configured to train a neural network implemented by the neural network device by applying different voltages to the ferroelectric memories included in each of the plurality of memory cells, in a process of updating a weight stored in each of the plurality of memory cells (Fig. 1b, synapse synaptic plasticity "The synaptic update is induced by altering the conductance of the selected device as dictated by a learning algorithm. This is achieved by applying a suitable programming pulse to the selected device".
Regarding Claim 4, Boybat in view of LUO discloses the neural network device of claim 3, LUO discloses wherein the different voltages applied to the ferroelectric memories included in each of the plurality of memory cells are determined so that nonlinear state-change characteristics of each ferroelectric memory are offset in a process of synthesizing conductances by parallel connection ([0061], FIG. 3B, in the dielectric layer 320 made of a material having a ferroelectric property, before the ferroelectric thin film of the dielectric layer 320 is polarized. The polarized electric field causes directional movement of electron).
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.
The same reason or rational of obviousness motivation applied as used above in claim 1.
Regarding Claim 5, Boybat in view of LUO discloses the neural network device of claim 3,
LUO discloses wherein the neural network device is configured to update the weights by applying direct current (DC) voltages, having a constant voltage interval, to output terminals of the sub-bit lines ([0017], one end of the second inverter is connected to the working voltage VDD, another end of the second inverter is grounded to the VGND, and the output end of the second inverter is connected to a positive word line of a next level neural network layer adjacent to the each level of the neural network layer; [0048], FIG. 1A-FIG. 2B).
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The same reason or rational of obviousness motivation applied as used above in claim 1.
Regarding Claim 6, Boybat in view of LUO discloses the neural network device of claim 5,
LUO discloses wherein a difference between DC voltages applied to output terminals of adjacent sub-bit lines, among the sub-bit lines, corresponds to a standard deviation of a Gaussian distribution when a voltage-current characteristic curve of a ferroelectric memory is approximated to the Gaussian distribution ([0069], FIG. 1A, FIG. 1B and FIG. 4, Connection setting of each symmetric memory cell 100 and the interface module 200 in the BNN circuit are achieved through a word line WL301, a complementary word line 401 and a bit line BL501. Each symmetric memory unit 100 is connected to the interface module 200 through the bit line BL501 for controlling an input of each symmetric memory cell 100 to the interface module 200. That is, a connection end of the bit line BL501 of the interface module 200 is an input end in).
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The same reason or rational of obviousness motivation applied as used above in claim 1.
Regarding Claim 7, Boybat in view of LUO discloses the neural network device of claim 3,
Boybat discloses wherein output terminals of the sub-bit lines are connected such that, for at least one of the plurality of bit lines, currents flowing through each of the sub-bit lines are summed and output when inference is performed using the trained neural network (Fig. 1a, the resulting current flowing through each device is summed up to generate the synaptic output in which sub-bit lines are connected to sum outputs per synapse).
Regarding Claim 8, Boybat in view of LUO discloses the neural network device of claim 7,
Boybat discloses further comprising: a switching circuit configured to control whether the output terminals of the sub-bit lines are connected to each other or are connected to DC voltages ( Page 9, Fig. 1b & Fig. 1c, a thin oxide n-type field-effect transistor (FET) enables access to each PCM device’ Fig. 1a, the resulting current flowing through each device is summed up to generate the synaptic output in which sub-bit lines are connected to sum outputs per synapse).
Regarding Claim 9, Boybat in view of LUO discloses the neural network device of claim 1,
Boybat discloses wherein each of the plurality of memory cells further comprises a selection element configured to selectively approach the ferroelectric memories included in each of the plurality of memory cells (Page 9, Fig. 1b & Fig. 1c, a thin oxide n-type field-effect transistor (FET) enables access to each PCM device’ Fig. 1a, the resulting current flowing through each device is summed up to generate the synaptic output in which sub-bit lines are connected to sum outputs per synapse).
Regarding Claim 10, Boybat in view of LUO discloses the neural network device of claim 1,
LUO discloses wherein each of the at least two ferroelectric memories comprise at least one of a capacitor having a metal-ferroelectric-metal structure; a ferroelectric tunnel junction (FTJ) element; or a ferroelectric field-effect transistor (FeFET) ([0061], FIG. 3B, in the dielectric layer 320 made of a material having a ferroelectric property; [0074], FIG. 4, the bit lines 501 of the plurality of symmetrical memory cells 100 in the memory cell array group 110a of the neural network layer 110 are input to the input end In of the interface module 200 at another end of the memory cell array group 110a, the positive output terminal Out of the interface module 200 is input to the positive word line 301 of the symmetrical memory cell 100 at one end of the memory cell array group at a corresponding position of the next level neural network layer 120) The same reason or rational of obviousness motivation applied as used above in claim 1.
Boybat also discloses a thin oxide n-type field-effect transistor (FET) enables access to each PCM device (Page 9, Fig. 1b & Fig. 1c)
Regarding Claim 11, System claim 11 of using the corresponding device claimed in claims 1, and the rejections of which are incorporated herein for the same reasons as used above.
Boybat also discloses wherein the neural network device is configured to perform a neural network operation, based on input data received from the processor, and to generate an information signal corresponding to the input data, based on a result of the neural network operation (Abstract, phase change memory devices, develop a comprehensive model and demonstrate via simulations the effectiveness of the concept for both spiking and non-spiking neural network; Introduction, hardware implementations of deep neural networks).
Regarding Claims 12-13, System claims 12-13 of using the corresponding device claimed in claims 3 & 4, and the rejections of which are incorporated herein for the same reasons as used above.
Regarding Claim 14, Boybat in view of LUO discloses the electronic system of claim 12,
Boybat discloses wherein the processing circuitry is configured to control voltage input to an input terminal of a word line, of the plurality of word lines, as a pulse train during the training of the neural network, and a state-change characteristic curve of each of the plurality of memory cells during the training of the neural network is represented by a linear long-term potentiation and depression characteristic (Fig. 2, using pulse-trains to program, Synapses based on phase change memory (PCM) device that consists of a phase-change material layer sandwiched between top and bottom electrodes with gradually increasing crystalline region by the application of potentiation pulses).
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Regarding Claim 15, Analogous rejection as the rejection of Claim 14 applies.
Furthermore, of LUO discloses that after a bias scan voltage is additionally applied from 0 to 6V, the programmable diode show a feature of a diode that is turned on in a forward direction, and after a bias scan voltage is additionally applied from 0 to −6V, the programmable diode shows a feature of a diode that is turned on in a reverse direction ([0065],FIG. 3D)
Regarding Claims 16-18, System claims 16-18 of using the corresponding device claimed in claims 5-6 & 9, and the rejections of which are incorporated herein for the same reasons as used above.
Regarding Claim 19, Boybat in view of LUO discloses the electronic system of claim 18,
Boybat discloses wherein the selection elements include transistors (Page 9, Fig. 1b & Fig. 1c, a thin oxide n-type field-effect transistor (FET) enables access to each PCM device’).
Regarding Claim 20, Boybat in view of LUO discloses the electronic system of claim 18,
Boybat discloses , wherein the selection elements include threshold switches configured to allow a flow of current when a difference between voltages applied to both ends of the threshold switches is greater than or equal to a threshold value (Page 9, Fig. 1b & Fig. 1c, a thin oxide n-type field-effect transistor (FET) enables access to each PCM device that integrates the circuitry for addressing, an eight-bit on-chip analog-to-digital converter (ADC) for readout, and voltage-mode or current-mode programming. An analog-front-end (AFE) board is connected to the chip and accommodates digital-to-analog converters (DACs) and ADCs, discrete electronics, such as power supplies, voltage and current reference sources)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20120307545 A : Interleaved Bit Line Architecture For 2T2C Ferroelectric Memories
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Samuel D Fereja whose telephone number is (469)295-9243. The examiner can normally be reached 8AM-5PM.
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/SAMUEL D FEREJA/Primary Examiner, Art Unit 2487
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