DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This communication is in response to the amendment filed on 05/28/2026.
Claims 1-14 and 21-26 are pending and are rejected. Claims 15-20 have been canceled. Claims 21-26 are new. Claims 1-13 have been amended.
Response to Arguments
Applicant’s arguments with respect to claim 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant further argued that Kodama does not discloses or suggest a hint from a processor device to a network interface device to indicate an occupancy of the cache of the processor. However, Kodama teaches the start indication sent from the CPU that includes a processor cache when combine the teaching of newly cited reference Irie.
The amendment overcome the Drawings Objection and the Rejection under 35. U.S.C § 101. The previous Objection/Rejection have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-11, 16-18, 20-24 are rejected under 35 U.S.C. 103 as being unpatentable over Kodama et al. (US 5623607 A), hereafter Kodama in view of Irie (US 6038644 A) et al, hereafter Irie.
Regarding claim 1, Kodama teaches a network interface device comprising:
a hardware interface to a processor device (col. 2, lines 60-4, Referring now to FIG. 1 and the flow chart of FIG. 2, the flow of control is described in brief. First of all, a write data transfer operation is started by a start indication sent to the disk control unit 3 from the higher-rank CPU 15 via optical channel 1);
a hardware interface to a network to receive an incoming message from the network to send to the processor device (col. 2, lines 32-33, In FIG. 1, a disk control unit 3 includes an optical communication control unit 4 for controlling communication to a predetermined protocol with a higher rank optical channel 1. Referring now to Fig.1, the optical communication control unit 4 interfaces with the higher-rank CPU 15);
a data queue between the hardware interface to the processor device and the hardware interface to the network (col. 4, lines 3-8, when the remaining write data number A is larger than the buffer capacity B (A>B) (step 202), a request for data in an amount corresponding to the value P to be stored in the buffer 5 in a unit of the packet capacity is sent to the higher-rank CPU 15 in order to initiate the transfer of data to the buffer from the higher-rank CPU 15); and
logic to receive a hint from a processor delice to indicate an occupancy of the processor cache (col. 2, lines 61-67, fig. 1, a write data transfer operation is started by a start indication sent to the disk control unit 3 from the higher-rank CPU 15 (hint from a processor) via optical channel 1. The write data transfer control involves the data transfer control for transfer of data in a quantity equal to the buffer capacity or less carried out at the beginning of the control); and adjust a transfer rate of the incoming message from the data queue to the processor device in response to the hint (col. 4, lines 3-10, when the remaining write data number A is larger than the buffer capacity B, a request for data in an amount corresponding to the value P to be stored in the buffer 5 in a unit of the packet capacity is sent to the higher-rank CPU 15 in order to initiate the transfer of data to the buffer from the higher-rank CPU 15. Then, in order to monitor the data request indication number, the value P is subtracted from the values B and A (adjust a transfer rate)).
Kodama does not explicitly teach the processor device including a processor cache.
Irie teaches
the processor device including a processor cache (col. 10, lines 9-14, the multicast table 400 holds in correspondence to each of the memory areas included in the main memory, a status indicative of whether data which belongs to the memory area is cached by one of the processor units. This held status will be called a processor unit caching status).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the processor includes a cache, as taught by Irie. One would be motivated to do so to store frequently accessed data and instructions so the processor can retrieve them much faster than from main memory.
Regarding claims 2, 10, and 25, Kodama and Irie teach all limitation of parent claims 1, 9, and 24, wherein Kodama further teaches the logic is to:
incoming message comprises a first incoming message of a plurality of incoming messages associated with multiple bi-directional streams (col. 2, lines 61-63, the request queues 520-1 to 520-N are provided respectively corresponding to the plural units respectively connected by lines 5010-1 to 5010-N and respectively receive messages from the corresponding units sequential. Col. , lines , the output selector 530-1 to 530-N are provided in correspondence to the plural units connected respectively by lines 5030-1 to 5030-N, and the transfer control logics 510-1 to 510-N are provided in correspondence to the output selectors 530-1 to 530-N), wherein the hint comprises a first hint associated with a first bi-directional stream, wherein other bi-direction streams receive separate hints (col. 2, lines 64-66, the write data transfer control involves the data transfer control for transfer of data in a quantity equal to the buffer capacity), and wherein the logic is to adjust a plurality of transfer rates of the plurality of incoming messages based on hints associated with respective bi-directional streams (col. 4, lines 9, the value P is subtracted from the values B and A).
Kodama does not explicitly teach incoming messages associated with multiple bi-directional streams.
Irie teaches
incoming messages associated with multiple bi-directional streams (col. 13, lines 7-15, the request queues 520-1 to 520-N are provided respectively corresponding to the plural units respectively connected by lines 5010-1 to 5010-N and respectively receive messages from the corresponding units sequentially. The output selector 530-1 to 530-N are provided in correspondence to the plural units connected respectively by lines 5030-1 to 5030-N, and the transfer control logics 510-1 to 510-N are provided in correspondence to the output selectors 530-1 to 530-N.).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the bi-direction connection for transfer data between devices, as taught by Irie. One would be motivated to do so to store frequently accessed data and instructions so the processor can retrieve them much faster than from main memory.
Regarding claims 3 and 11, Kodama and Irie teach all limitations of parent claims 1 and 9, wherein Kodama further teaches the logic is to receive the hint from the processor device on every transaction from the processor device to the network interface (col. 2, lines 45-47, the optical communication control unit 4 includes a buffer 5 which stores write data, received from the higherrank CPU 15 through the optical channel 1).
Regarding claims 4, 12, and 26, Kodama and Irie teach all limitation of parent claims 1, 9, and 24, Kodama further teaches wherein the logic to receive the hint from the processor device on both data transaction and on instruction transactions (col. 2, lines 64-67, The write data transfer control involves the data transfer control for transfer of data in a quantity equal to the buffer capacity or less carried out at the beginning of the control, the data transfer control; col. 3, lines 43-46, first of all, as an initial value of a remaining number A of write data, the number of all of the write data obtained from the start indication of the write data transfer received from the higher-rank CPU 15 is set).
Regarding claims 6, 20, and 21, Kodama and Irie teach all limitation of parent claims 1, 9, and 16, wherein Ilda further teaches the incoming message is associated with a bi-directional stream between the network interface device and the processor device, wherein the bi-directional stream comprises a Peripheral Component Interconnect (PCI) connection, a Compute Express Link (CXL) connection, or a Peripheral Component Interconnect Express (PCIe) connection (col. 13, lines 41-45, in FIG. 8, the multicast transfer control unit 600 has the bitmap queues 610-1 to 610-n which temporarily holds requests from the processor units, the port reservation table 650, the parallel request detect logic 620, the request select logic 630 and the parallel request queue 640.).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the bi-direction connection include a PCI express, as taught by Irie. One would be motivated to do so to store frequently accessed data and instructions so the processor can retrieve them much faster than from main memory.
Regarding claims 7 and 22, Kodama and Irie teach tall limitations of parent claims 1 and 9, wherein Ilda further teaches the network interface device is a network interface controller (NIC), a smart network interface controller (SmartNIC), an Infrastructure Processing Unit (IPU), or a Data Processing Unit (DPU) (col. 24, lines 57-61, fig. 7, traffic of the coherent read requests is accumulated in unit of a process and is stored in the process control block 710, as an interface to execute process assignment, based upon the traffic of the coherent read requests).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the communication connection include a network interface, as taught by Irie. One would be motivated to do so to improve the bus congestion by the coherent read requests in the shared bus.
Regarding claims 8 and 23, Kodama and Ilda teach all limitations of parent claims 1 and 9, wherein Kodama further teaches the hint comprises a first hint, wherein the logic is to receive a second hint to indicate a type of the processor cache, to indicate an access speed associated with the processor cache (col. 4, lines 15-19, if the write data number A is not larger than the buffer capacity B, data requests will be sent successively to the higher-rank CPU in a unit of the packet capacity as long as the value A is larger than or equal to the value P).
Regarding claim 9, Kodama teaches a system comprising:
a network interface device (col. 2, lines 32-33, In FIG. 1, a disk control unit 3 includes an optical communication control unit 4 for controlling communication to a predetermined protocol with a higher rank optical channel 1. Referring now to Fig.1, the optical communication control unit 4 interfaces with the higher-rank CPU 15);
a processor device of a server coupled to the network interface device (col. 2, lines 60-4, Referring now to FIG. 1 and the flow chart of FIG. 2, the flow of control is described in brief. First of all, a write data transfer operation is started by a start indication sent to the disk control unit 3 from the higher-rank CPU 15 via optical channel 1); and
a memory architecture of the processor device, the memory architecture including logic (col. 1, lines 37-42, a memory coupled to a higher-rank CPU) to:
send a hint to the network interface device to indicate an occupancy of the processor cache (col. 2, lines 61-67, fig. 1, a write data transfer operation is started by a start indication sent to the disk control unit 3 from the higher-rank CPU 15 (hint from a processor) via optical channel 1. The write data transfer control involves the data transfer control for transfer of data in a quantity equal to the buffer capacity or less carried out at the beginning of the control), and receive an incoming message from the network interface device with an adjusted transfer rate in response to the hint (col. 4, lines 3-10, when the remaining write data number A is larger than the buffer capacity B, a request for data in an amount corresponding to the value P to be stored in the buffer 5 in a unit of the packet capacity is sent to the higher-rank CPU 15 in order to initiate the transfer of data to the buffer from the higher-rank CPU 15. Then, in order to monitor the data request indication number, the value P is subtracted from the values B and A (adjust a transfer rate)).
Kodama does not explicitly teach the processor device including a processor cache.
Irie teaches
the processor device including a processor cache (col. 10, lines 9-14, the multicast table 400 holds in correspondence to each of the memory areas included in the main memory, a status indicative of whether data which belongs to the memory area is cached by one of the processor units. This held status will be called a processor unit caching status).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the processor includes a cache, as taught by Irie. One would be motivated to do so to store frequently accessed data and instructions so the processor can retrieve them much faster than from main memory.
Regarding claim 24, Kodama teaches a method comprising:
receiving a hint from a processor device at a network interface device to indicate an occupancy of a processor cache of the processor cache (col. 2, lines 61-67, fig. 1, a write data transfer operation is started by a start indication sent to the disk control unit 3 from the higher-rank CPU 15 (hint from a processor) via optical channel 1. The write data transfer control involves the data transfer control for transfer of data in a quantity equal to the buffer capacity or less carried out at the beginning of the control); and
adjusting a transfer rate of an incoming message from a data queue of the network interface device to the processor device in response to the hint (col. 4, lines 3-10, when the remaining write data number A is larger than the buffer capacity B, a request for data in an amount corresponding to the value P to be stored in the buffer 5 in a unit of the packet capacity is sent to the higher-rank CPU 15 in order to initiate the transfer of data to the buffer from the higher-rank CPU 15. Then, in order to monitor the data request indication number, the value P is subtracted from the values B and A (adjust a transfer rate)).
Kodama does not explicitly teach a processor cache.
Irie teaches
a processor cache (col. 10, lines 9-14, the multicast table 400 holds in correspondence to each of the memory areas included in the main memory, a status indicative of whether data which belongs to the memory area is cached by one of the processor units. This held status will be called a processor unit caching status).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the processor includes a cache, as taught by Irie. One would be motivated to do so to store frequently accessed data and instructions so the processor can retrieve them much faster than from main memory.
26. (New) The method of claim 24, wherein receiving the hint from the processor device comprises receiving the hint on both data transactions and on instruction transactions.
Claims 5, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kodama in view of Irie and further in view of Channabasappa et al. (US 8848526 B1), hereafter Channabasappa.
Regarding claims 5 and 13, Kodama and Ilda teach all limitation of parent claims 1 and 9, Kodama does not explicitly teach wherein the processor cache comprises one or more of buffer space type, a register file buffer space type, part of a cache buffer space type, an L1 cache buffer space type, part of the L1 cache buffer space type, buffer space configured out of the L1 cache buffer space type, an L2 cache buffer space type, part of the L2 cache buffer space type, or buffer space configured out of the L2 cache buffer space type.
Channabasappa teaches
the processor cache comprises one or more of: a first in first out buffer space type, a time aware cache buffer space type, a register file buffer space type, part of a cache buffer space type, an L1 cache buffer space type, part of the L1 cache buffer space type, buffer space configured out of the L1 cache buffer space type, an L2 cache buffer space type, part of the L2 cache buffer space type, or buffer space configured out of the L2 cache buffer space type (col. 3, lines 49-50, buffer circuitry 120 in the form of a FIFO).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the communication connection includes a FIFO, as taught by Channabasappa. One would be motivated to do so for controlling data rates across a transmit interface through programmable idle insertion operations.
Claim 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kodama in view of Irie and further in view of Chan (US 5889936 A).
Regarding claim 14, Kodama and Irie teach the system of claim 9, Kodama does not explicitly teach wherein the memory architecture comprises a memory management unit, where in the memory management unit is to:
dynamically manage one or more of: a first cache that can be split into a FIFO structure, a second cache that is capable of being split into more than one FIFO structures, a third cache that is capable of being split into a register file structures, a fourth cache that is capable of being split into more than one register file structures, a fifth cache that is capable of being split into a time-aware memory, or a sixth cache that is capable of being split into more than one time-aware memories.
Chan teaches
dynamically manage one or more of: a first cache that can be split into a FIFO structure, a second cache that is capable of being split into more than one FIFO structures, a third cache that is capable of being split into a register file structures, a fourth cache that is capable of being split into more than one register file structures, a fifth cache that is capable of being split into a time-aware memory, or a sixth cache that is capable of being split into more than one time-aware memories (col. 6, lines 39-41, the FIFO clocks in parallel data into a memory location of FIFO in response to the divide-by-N clock signal over write control line).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the communication connection includes a multiple FIFO, as taught by Chan. One would be motivated to do so to perform high speed functional testing of an integrated circuit or a system.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH NGUYEN whose telephone number is (571)270-0657. The examiner can normally be reached M-F.
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/ANH NGUYEN/Primary Examiner, Art Unit 2458
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