DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This communication is in response to the application filed on 12/12/2022.
Claims 1-20 are pending and are rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/12/2022 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because the block 666 in Fig. 6 should be written as block 626. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 16-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Regarding to claim 16, the claim describes one or more computer readable storage medium.
Further, Applicant's specification, fails to explicitly define the scope of computer readable storage medium. The broadest reasonable interpretation of a claim drawn to a computer readable storage medium typically covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media, particularly when the specification is silent. See MPEP 2111.01. A claim that covers both statutory and non-statutory embodiments (under the broadest reasonable interpretation of the claim when read in light of the specification and in view of one skilled in the art) embraces subject matter that is not eligible for patent protection and therefore is directed to non-statutory subject matter. See MPEP §2106.
Thus, in giving the term its plain meaning (see MPEP 2111.01), the claimed computer readable storage medium is considered to include data signals per se. Data signals per se are not statutory as they fail to fall into one of the four statutory categories of invention.
As an additional note, a non-transitory computer program having executable programming instructions stored thereon is considered statutory as non-transitory computer program excludes transitory data signals.
Claim 17-12 depend on claim 16 and is rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-11, 16-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kodama et al. (US 5623607 A), hereafter Kodama in view of Ildda (US 20060047899 A1) et al, hereafter Ilda.
Regarding claim 1, Kodama teaches a network interface device comprising:
one or more substrates (col. 2, lines 36, a lower-rank disk unit); and
a logic coupled to the one or more substrates, where the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware (col. 2, lines 32-33, In FIG. 1, a disk control unit 3 includes an optical communication control unit 4), the logic to:
receive an incoming message including a hint from a processor of a server via a bi-directional stream, wherein the hint includes one or more of buffer space type data or buffer space available data (col. 2, lines 61-67, fig. 1, a write data transfer operation is started by a start indication sent to the disk control unit 3 from the higher-rank CPU 15 (hint from a processor) via optical channel 1. The write data transfer control involves the data transfer control for transfer of data in a quantity equal to the buffer capacity or less carried out at the beginning of the control); and
adjust a transfer rate of outgoing messages via the bi-directional stream in response to the hint (col. 4, lines 3-10, when the remaining write data number A is larger than the buffer capacity B, a request for data in an amount corresponding to the value P to be stored in the buffer 5 in a unit of the packet capacity is sent to the higher-rank CPU 15 in order to initiate the transfer of data to the buffer from the higher-rank CPU 15. Then, in order to monitor the data request indication number, the value P is subtracted from the values B and A (adjust a transfer rate)).
Kodama does not explicitly teach via the bi-directional stream.
Ilda teaches
via the bi-directional stream ([0096] The buffer unit 12 of the FB-DIMM 10 comprises memory interface units 65, 66 which can perform a memory access from the bi-direction of the loop).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the bi-direction connection for transfer data between devices, as taught by Ilda. One would be motivated to do so to improve the processing speed of the channel control unit and improve the data transfer speed.
Regarding claims 2 and 10, Kodama and Ilda teach all limitation of parent claims 1 and 9, wherein Kodama further teaches the logic is to:
receive a plurality of incoming messages including a plurality of hints from the processor of the server via a plurality of bi-directional streams on a stream-by-stream basis (col. 2, lines 61-63, a write data transfer operation is started by a start indication sent to the disk control unit 3 from the higher-rank CPU),
wherein the plurality of hints include buffer space type data and buffer space available data (col. 2, lines 64-66, the write data transfer control involves the data transfer control (step 101) for transfer of data in a quantity equal to the buffer capacity);
and
adjust a plurality of transfer rates of outgoing messages via the plurality of bi-directional streams in response to the plurality of hints on the stream-by-stream basis (col. 4, lines 9, the value P is subtracted from the values B and A).
Kodama does not explicitly teach via the bi-directional stream.
Ilda teaches
via the bi-directional stream ([0014] the memory access can be performed in bi-directions of the loop-shaped serial interface).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the bi-direction connection for transfer data between devices, as taught by Ilda. One would be motivated to do so to improve the processing speed of the channel control unit and improve the data transfer speed.
Regarding claims 3 and 11, Kodama and Ilda teach all limitation of parent claims 1 and 9, wherein Kodama further teaches the adjusted transfer rate is to pace the outgoing messages to one or more of: the processor of the server, a buffer space associated with the processor of the server, or a memory associated with the processor of the server (col. 4, lines 15-17, if the write data number A is not larger than the buffer capacity, data requests will be sent successively to the higher-rank CPU).
Regarding claims 6 and 20, Kodama and Ilda teach all limitation of parent claims 1 and 16, wherein Ilda further teaches the bi-directional stream comprises a Peripheral Component Interconnect (PCI) connection, a Compute Express Link (CXL) connection, or a Peripheral Component Interconnect Express (PCIe) connection ([0005] the interface with the memory controller has a serial interface similar to a PCI express).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the bi-direction connection include a PCI express, as taught by Ilda. One would be motivated to do so to improve the processing speed of the channel control unit and improve the data transfer speed.
Regarding claim 7, Kodama and Ilda teach the network interface device of claim 1, wherein Ilda further teaches the network interface device is a network interface controller (NIC), a smart network interface controller (SmartNIC), an Infrastructure Processing Unit (IPUs), or a Data Processing Unit (DPU) ([0067] Each of the channel control units CHN1 and CHN2 (110) comprises a network interface).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the communication connection include a network interface, as taught by Ilda. One would be motivated to do so to improve the processing speed of the channel control unit and improve the data transfer speed.
Regarding claim 8, Kodama and Ilda teach the network interface device of claim 1, wherein Kodama further teaches one or more of the outgoing messages include one or more of data or instructions (col. 4, lines 15-19, if the write data number A is not larger than the buffer capacity B, data requests will be sent successively to the higher-rank CPU in a unit of the packet capacity as long as the value A is larger than or equal to the value P).
Regarding claim 9, Kodama teaches a system comprising:
a processor of a server; and a memory architecture communicatively coupled to the processor of the server, the memory architecture including logic coupled to one more substrates (col. 1, lines 37-42, a memory coupled to a higher-rank CPU), wherein the logic is to:
send an outgoing message including a hint to a network interface device via a bi-directional stream, wherein the hint includes one or more of buffer space type data or buffer space available data (col. 2, lines 61-67, fig. 1, a write data transfer operation is started by a start indication sent to the disk control unit 3 from the higher-rank CPU 15 (hint from a processor) via optical channel 1. The write data transfer control involves the data transfer control for transfer of data in a quantity equal to the buffer capacity or less carried out at the beginning of the control); and
receive an incoming message from the network interface device via the bi-directional stream, wherein the incoming message is associated with an adjusted transfer rate of incoming messages from the network interface device in response to the hint (col. 4, lines 3-10, when the remaining write data number A is larger than the buffer capacity B, a request for data in an amount corresponding to the value P to be stored in the buffer 5 in a unit of the packet capacity is sent to the higher-rank CPU 15 in order to initiate the transfer of data to the buffer from the higher-rank CPU 15. Then, in order to monitor the data request indication number, the value P is subtracted from the values B and A (adjust a transfer rate)).
Kodama does not explicitly teach via the bi-directional stream.
Ilda teaches
via the bi-directional stream ([0096] The buffer unit 12 of the FB-DIMM 10 comprises memory interface units 65, 66 which can perform a memory access from the bi-direction of the loop).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the bi-direction connection for transfer data between devices, as taught by Ilda. One would be motivated to do so to improve the processing speed of the channel control unit and improve the data transfer speed.
Regarding claim 16, Kodama teaches at least one computer readable storage medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
send, via a consumer device, an outgoing message including a hint to a producer device via a bi-directional stream, wherein the hint includes one or more of buffer space type data or buffer space available data (col. 2, lines 61-67, fig. 1, a write data transfer operation is started by a start indication sent to the disk control unit 3 from the higher-rank CPU 15 (hint from a processor) via optical channel 1. The write data transfer control involves the data transfer control for transfer of data in a quantity equal to the buffer capacity or less carried out at the beginning of the control); and
receive, via the consumer device, an incoming message from the producer device via the bi-directional stream, wherein the incoming message is associated with an adjusted transfer rate of incoming messages from the producer device in response to the hint (col. 4, lines 3-10, when the remaining write data number A is larger than the buffer capacity B, a request for data in an amount corresponding to the value P to be stored in the buffer 5 in a unit of the packet capacity is sent to the higher-rank CPU 15 in order to initiate the transfer of data to the buffer from the higher-rank CPU 15. Then, in order to monitor the data request indication number, the value P is subtracted from the values B and A (adjust a transfer rate)).
Kodama does not explicitly teach via the bi-directional stream.
Ilda teaches
via the bi-directional stream ([0096] The buffer unit 12 of the FB-DIMM 10 comprises memory interface units 65, 66 which can perform a memory access from the bi-direction of the loop).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the bi-direction connection for transfer data between devices, as taught by Ilda. One would be motivated to do so to improve the processing speed of the channel control unit and improve the data transfer speed.
Regarding claim 17, Kodama and Ilda teach the at least one computer readable storage medium of claim 16, wherein Kodama further teaches the hint comprises one or more of: a rate, a rate adjustment, or a credit return (col. 3, lines 6-8, a request for data having a capacity of the buffer 5 or less is indicated to the optical channel).
Regarding claim 18, Kodama and Ilda teach the at least one computer readable storage medium of claim 16, wherein Ilda further teaches the consumer device comprises a memory centric device, and wherein the memory centric device has one or more of: a cache, a time-aware memory, a FIFO connected to a processor, or a register file connected to the processor ([0096] according to the set content in an initial set register 54, when receiving a memory access request from the CPU 112).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the memory includes a register file connect to the CPU, as taught by Ilda. One would be motivated to do so to improve the processing speed of the channel control unit and improve the data transfer speed.
Claims 4-5, 12-13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kodama in view of Ildda and further in view of Channabasappa et al. (US 8848526 B1), hereafter Channabasappa.
Regarding claims 4 and 12, Kodama and Ilda teach all limitation of parent claims 1 and 9, Kodama does not explicitly teach wherein the logic is to:
send a feedback hint in one or more of the outgoing messages to the processor of the server, wherein the feedback hint contains information for rate matching operations of the processor of the server to the network interface device, and wherein the feedback hint is based on the adjusted transfer rate.
Channabasappa teaches
send a feedback hint in one or more of the outgoing messages to the processor of the server, wherein the feedback hint contains information for rate matching operations of the processor of the server to the network interface device, and wherein the feedback hint is based on the adjusted transfer rate (col. 4, lines 15-20, the status of the transmit FIFO may be communicated to the core to vary the rate at which data is fed to the FIFO along the output bus 126. Thus, when the FIFO is close to filling, the core can be alerted to slow the flow of response data from the core, and assist the FIFO in freeing buffering resources).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the communication connection includes a FIFO, as taught by Channabasappa. One would be motivated to do so for controlling data rates across a transmit interface through programmable idle insertion operations.
Regarding claims 5 and 13, Kodama and Ilda teach all limitation of parent claims 1 and 9, Kodama does not explicitly teach cache buffer space type, a register file buffer space type, part of a cache buffer space type, an L1 cache buffer space type, part of the L1 cache buffer space type, buffer space configured out of the L1 cache buffer space type, an L2 cache buffer space type, part of the L2 cache buffer space type, or buffer space configured out of the L2 cache buffer space type.
Channabasappa teaches
the buffer space comprises one or more of: a first in first out buffer space type, a time aware cache buffer space type, a register file buffer space type, part of a cache buffer space type, an L1 cache buffer space type, part of the L1 cache buffer space type, buffer space configured out of the L1 cache buffer space type, an L2 cache buffer space type, part of the L2 cache buffer space type, or buffer space configured out of the L2 cache buffer space type (col. 3, lines 49-50, buffer circuitry 120 in the form of a FIFO).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the communication connection includes a FIFO, as taught by Channabasappa. One would be motivated to do so for controlling data rates across a transmit interface through programmable idle insertion operations.
Regarding claim 19, Kodama and Ilda teach the at least one computer readable storage medium of claim 16, wherein Ilda further teaches the consumer device comprises a memory centric device, and ([0057] a connection unit connects each channel control unit, a shared memory, a cache memory and each disk control unit to each other).
Kodama and Ilda do not explicitly teach
wherein the memory centric is structured to implement one or more of: a FIFO from a cache memory, a time-aware memory from the cache memory, or a register file structure from the cache memory.
Channabasappa teaches
wherein the memory centric is structured to implement one or more of: a FIFO from a cache memory, a time-aware memory from the cache memory, or a register file structure from the cache memory (col. 4, lines 64-67, in register circuitry via a suitable application programming interface (API). Additional circuitry in the transmit interface includes serializer circuitry to convert parallel data words from the FIFO to serial data words).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the communication connection includes a FIFO, as taught by Channabasappa. One would be motivated to do so for controlling data rates across a transmit interface through programmable idle insertion operations.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kodama in view of Ildda and further in view of Chan (US 5889936 A).
Regarding claim 14, Kodama and Ilda teach the system of claim 9, Kodama does not explicitly teach wherein the memory architecture comprises a memory management unit, where in the memory management unit is to:
dynamically manage one or more of: a first cache that can be split into a FIFO structure, a second cache that is capable of being split into more than one FIFO structures, a third cache that is capable of being split into a register file structures, a fourth cache that is capable of being split into more than one register file structures, a fifth cache that is capable of being split into a time-aware memory, or a sixth cache that is capable of being split into more than one time-aware memories.
Chan teaches
dynamically manage one or more of: a first cache that can be split into a FIFO structure, a second cache that is capable of being split into more than one FIFO structures, a third cache that is capable of being split into a register file structures, a fourth cache that is capable of being split into more than one register file structures, a fifth cache that is capable of being split into a time-aware memory, or a sixth cache that is capable of being split into more than one time-aware memories (col. 6, lines 39-41, the FIFO clocks in parallel data into a memory location of FIFO in response to the divide-by-N clock signal over write control line).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the communication connection includes a multiple FIFO, as taught by Chan. One would be motivated to do so to perform high speed functional testing of an integrated circuit or a system.
Regarding claim 15, Kodama and Ilda teach the system of claim 9, Kodama does not explicitly teach wherein the buffer space available data is communicated with only two bits, only three bits, or only eight bits.
the buffer space available data is communicated with only two bits, only three bits, or only eight bits.
Chan teaches
the buffer space available data is communicated with only two bits, only three bits, or only eight bits (col. 5, lines 41-43, each of the marker fields stores 3 bits of marker data also referred to as a marker group).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Kodama disclosure, the field allow 3 bits data, as taught by Chan. One would be motivated to do so to perform high speed functional testing of an integrated circuit or a system.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhuo (US 20210377787 A1) and Narasimha ((US 20210306904 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH NGUYEN whose telephone number is (571)270-0657. The examiner can normally be reached M-F.
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/ANH NGUYEN/Primary Examiner, Art Unit 2458