DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending.
3. This office action is in response to the Applicant’s communication filed 08/20/2025 in response to PTO Office Action mailed 06/04/2025. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
Response to Arguments
4. Applicant’s arguments with respect to the amended independent claims have been considered but are moot in view of the new ground(s) of rejection in which the Examiner has cited newly presented prior art, Namekawa (US Pub. No. 2008/0212384 A1 hereinafter “Namekawa”), as necessitated by the amended independent claims disclosing an isolation circuit configured to decouple output nodes of the amplifier circuit from input nodes of the latch circuit.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1, 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Afghahi et al. (US Pub. No. 2009/0010041 A1 hereinafter “Afghahi”) in view of Namekawa (US Pub. No. 2008/0212384 A1 hereinafter “Namekawa”).
Referring to claim 1, Afghahi discloses an apparatus, comprising:
an amplifier circuit configured to amplify, during a first time period, a difference between a first input signal and a second input signal to generate a voltage difference between a first output node and a second output node, wherein the first input signal and the second input signal encode a plurality of data symbols (Afghahi – Par. [0009] discloses conventional sense amplifier 200 is illustrated in FIG. 2. This sense amplifier includes a differential amplifier 205 that compares a voltage P derived from bit line B (FIG. 1) at its positive input to a voltage N derived from bit line Bx (FIG. 1) at its negative input. If voltage P is higher than the voltage N, the voltage difference is amplified onto differential outputs P0 and N0 by the differential amplifier's gain.);
a latch circuit configured to increase, during a second time period, the voltage difference between the first output node and the second output node (Afghahi – Par. [0009] discloses a regenerative latch 210 would then drive voltage P full rail to VDD and pull voltage N to ground. Conversely, if voltage N is higher than voltage P, the regenerative latch drives voltage N full rail to VDD and pulls voltage P to ground.); and
an isolation circuit configured to decouple the amplifier circuit from the first output node and the second output node during a third time period (Afghahi – Par. [00039] discloses the isolation transistors must of course stay on so that the memory cell being accessed may be decoded by the sense amplifier.); and
wherein the latch circuit is further configured to regenerate, during the third time period, respective voltages of the first output node and the second output node to generate a particular voltage level on at least one of the first output node or the second output node that corresponds to a value of a corresponding one of the plurality of data symbols (Afghahi – Par. [0009] discloses a regenerative latch 210 would then drive voltage P full rail to VDD and pull voltage N to ground. Conversely, if voltage N is higher than voltage P, the regenerative latch drives voltage N full rail to VDD and pulls voltage P to ground.).
Afghahi fails to disclose an isolation circuit configured to decouple output nodes of the amplifier circuit from input nodes of the latch circuit during a third time period.
Namekawa discloses an isolation circuit configured to decouple output nodes of the amplifier circuit from input nodes of the latch circuit during a time period (Namekawa – Par. [0051] & fig. 1 disclose at this time, the connection cutoff unit 2 isolates the differential input circuit 1 or analog amplifier from the latch-type amplifier 3.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Namekawa’s teachings with Afghahi’s techniques for the benefit of the connection cutoff unit isolates the differential input circuit or analog amplifier from the latch-type amplifier to suppress power consumption (Namekawa – Par. [0051]).
Referring to claims 7 and 14, note the rejections of claim 1 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
7. Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Afghahi in view of Namekawa, and further in view of Carman (US Pub. No. 2023/0395131 A1 hereinafter “Carman”).
Referring to claim 4, Afghahi and Namekawa disclose the apparatus of claim 1, however, fails to explicitly disclose wherein to amplify the voltage difference between the first input signal and the second input signal, the amplifier circuit is further configured to discharge the first output node and the second output node using the first input signal and the second input signal.
Carman discloses wherein to amplify the voltage difference between the first input signal and the second input signal, the amplifier circuit is further configured to discharge the first output node and the second output node using the first input signal and the second input signal (Carman – Par. [0044] discloses at time 172, the ARPREa signal 76 and the ARPREb signal 82 are asserted causing the gut node a 56 and the gut node b 58 to be discharged to VSS (e.g., to 0 V) as illustrated by the lines 164, 166, 168, and 170. In certain embodiments, the discharged gut nodes may be pulled below 0 V to lower the overall voltage to provide a larger window in interpreting the data in exchange for increased power consumption in the sense amplifier 120.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Carman’s teachings with Afghahi and Namekawa’s techniques for the benefit of using the latch transistors also used in latching and amplification, the sense amplifiers may be smaller and consume less area in the memory device while maintaining timing and/or operation capabilities (Carman – Par. [0013]).
Referring to claim 5, Afghahi and Namekawa disclose the apparatus of claim 1, however, fails to explicitly disclose wherein to increase the voltage difference, the latch circuit is further configured to decouple the first output node from the second output node during the second time period.
Carman discloses wherein to increase the voltage difference, the latch circuit is further configured to decouple the first output node from the second output node during the second time period (Carman – See claim 16.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Carman’s teachings with Afghahi and Namekawa’s techniques for the benefit of using the latch transistors also used in latching and amplification, the sense amplifiers may be smaller and consume less area in the memory device while maintaining timing and/or operation capabilities (Carman – Par. [0013]).
Allowable Subject Matter
8. Claims 2, 3, 8-12 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “wherein the latch circuit is further configured to pre-charge the first output node and the second output node during a fourth time period subsequent to the third time period.”, in combination with other recited limitations in dependent claim 2.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “wherein the amplifier circuit is further configured to amplify, using a first local clock signal of the plurality of local clock signals, the voltage difference between the first input signal and the second input signal; wherein the latch circuit is further configured to integrate the voltage difference using a second local clock signal of the plurality of local clock signals, and regenerate, using a third local clock signal of the plurality of local clock signals, the voltage difference to generate a first output signal and a second output signal; wherein to increase the voltage difference, the latch circuit is further configured to increase the voltage difference between the first output node and the second output node using the second local clock signal of the plurality of local clock signals; and wherein to regenerate the respective voltages of the first output node and the second output node, the latch circuit is further configured to regenerate the respective voltages of the first output node and the second output node using the third local clock signal of the plurality of local clock signals.”, in combination with other recited limitations in dependent claim 6.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “further comprising pre-charging the latch circuit during a fourth time period subsequent to the third time period.”, in combination with other recited limitations in dependent claim 8.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “amplifying, by an amplifier circuit using a first local clock signal of the plurality of local clock signals, a voltage difference between the first input signal and the second input signal; integrating, by the sampler circuit, the voltage difference using a second local clock signal of the plurality of local clock signals; and regenerating, by a latch circuit using a third local clock signal of the plurality of local clock signals, the voltage difference to generate a first output signal and a second output signal.”, in combination with other recited limitations in dependent claim 13.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “wherein the sampler circuit includes a latch circuit, and wherein the sampler circuit is configured to pre-charge the latch circuit during a fourth time period subsequent to the third time period.”, in combination with other recited limitations in dependent claim 15.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “wherein the sampler circuit is further configured to: amplify, using a first local clock signal of the plurality of local clock signals, the voltage difference between the first input signal and the second input signal; integrate the voltage difference using a second local clock signal of the plurality of local clock signals; and regenerate, using a third local clock signal of the plurality of local clock signals, the voltage difference to generate the first output signal and the second output signal.”, in combination with other recited limitations in dependent claim 20.
Claims 3, 9-12 and 16-19 are allowable based on their dependencies of claims 2, 8 and 15.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 270-7754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Dayton Lewis-Taylor/
Examiner, Art Unit 2181
/Farley Abad/Primary Examiner, Art Unit 2181