Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-11, and 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eastep, US Patent Appl. Pub. No. 2016/0179173.
Regarding claim 1, Eastep discloses an integrated circuit (FIG(s) 1-5) comprising:
circuitry (FIG(s) 1 and 3) configured to:
allocate a first portion of a power budget to a first module and a second portion of the power budget to a second module (FIG. 1, paragraph 0029, lines 1-13, FIG. 5, 510-512, paragraph 0049, lines 11-18, paragraph 0050, lines 1-6), wherein the first module and the second module are instances of integrated circuitry (paragraph 0022, lines 6-12, paragraph 0023, lines 1-10, paragraph 0035, lines 1-16); and
reallocate the power budget between the first module and the second module (FIG. 1, paragraph 0030, FIG, 2B, paragraph 0033, FIG. 3, paragraph 0040, FIG. 4, 418-NO, 420, paragraph 0048, lines 1-5, FIG. 5, 514-NO, 510, paragraph 0050, lines 1-6, lines 9-11), responsive to a performance difference between a performance level of the first module and a performance level of the second module during execution of a same type of task (during a given program phase, all power domains/cores/components execute the same task – paragraphs 0011-0012; paragraph 0013, lines 1-8, paragraph 0017, lines 1-6, paragraph 0018, lines 1-10, paragraph 0029, lines 1-13, paragraph 0030, FIG. 4, paragraph 0046, paragraph 0048, lines 1-5), wherein the performance level of the first module and a performance level of the second module are determined based on received hardware performance metrics (FIG. 4, 412, paragraph 0046, paragraph 0050, lines 1-6).
Regarding claims 8 and 15, Eastep discloses a method and system with all claim limitations addressed above for claim 1.
Regarding claims 2, 9, and 16, Eastep further discloses the integrated circuit, method, and system, wherein the hardware performance metrics are based on performance counters in the first module and the second module (performance counters monitoring the performance metric/application activity during execution of particular application phase on respective power domain/component – paragraph 0030, lines 1-7, paragraph 0038, lines 4-7).
Regarding claims 3, 10, and 17, Eastep further discloses the integrated circuit, method, and system, as per claims 2, 9, and 16, respectively, wherein the hardware performance metrics comprising comprise one or more of a rate of instructions retired, a rate of instructions issued, and a rate of cache hits (paragraph 0046, lines 5-12).
Regarding claims 4, 11, and 18, Eastep further discloses the integrated circuit, method, and system wherein the first module and the second module are in different power domains (paragraph 0012, lines 1-3, paragraph 0029, lines 5-13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 7, 12, 14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eastep, US Patent Appl. Pub. No. 2016/0179173 in view of Kaburlasos et al., US Patent Appl. Pub. No. 2019/0377395.
Regarding claims 5, 7, 12, 14 and 19, Eastep discloses the integrated circuit, method, and system, as per claims 4, 11, and 18, respectively.
With respect to claims 5, 12, and 19, Eastep does not specifically state initially allocating, by the power management circuitry, the power budget such that the first portion is equal to the second portion.
With respect to claims 7 and 14, Eastep does not specifically state reallocating the power budget between the first module and the second module, in further response to a given time interval has elapsed.
Kaburlasos teaches dynamic power budget allocation in multi-processor system, wherein workload is assigned to each of the processor units (FIG(s) 15A-B, GPU[0]-[3], 1520,1525, 1530, and 1535) and an initial power budget is established for operation of each of the processor units, and further, upon determining that one or more processor units requires an increased power budget based on one or more criteria, dynamically reallocates an amount of the global power budget to the one or more processor units (Abstract). Kaburlasos further teaches setting the same initial (default) power budget to each GPU (FIG. 16B, 1634, paragraph 0177, lines 8-12), executing the workload for a predetermined time interval (FIG. 16B, 1636, paragraph 0178, lines 1-5), and upon expiration of the time interval, re-evaluating the GPU’s power budget requirements and re-allocating unused power budget from less power demanding GPU(s)s to GPU(s) requiring more power (FIG. 16B, 1638, 1640-Yes, 1642-Yes, 1644, paragraph 0179). Accordingly, the dynamic re-allocation of the total power budget prevents unnecessary power throttling or reducing the operation of certain processors while other processors remain underutilized, thus improving the overall system performance (paragraphs 0003-0004).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above-described system and functionality, as suggested by Kaburlasos with the integrated circuit, method and system disclosed by Eastep in order to implement initially allocating, by the power management circuitry, the power budget such that the first portion is equal to the second portion and reallocating the power budget between the first module and the second module, in further response to a given time interval has elapsed. One of ordinary skill in the art would be motivated to do so in order to improve the overall system performance.
Allowable Subject Matter
Claims 6, 13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 08/28/2025 have been fully considered but they are not persuasive.
Regarding claim 1, the applicant argued that the Eastep reference fails to disclose or suggest the features of "wherein the first module and the second module are instances of integrated circuitry."
The examiner disagrees. Eastep clearly discloses the processing device 110 being a dual/multi core processor on a single chip or integrated circuit (paragraph 0022, lines 6-12, paragraph 0023, lines 1-10, paragraph 0035, lines 1-16). Thus, each core within the single chip/ integrated circuit is an instance of the integrated circuitry.
In addition, the applicant argued that the Eastep reference fails to disclose or suggest the claim 1 features "circuitry configured to ... reallocate the power budget between the first module and the second module, responsive to a performance difference between a performance level of the first module and a performance level of the second module during execution of a same type of task."
The examiner disagrees. Eastep discloses reallocation of power between power domains for particular phase, wherein each phase is a program segment executing within a software application – i.e. a phase is one of the tasks of the software application (paragraphs 0011-0013). Eastep further discloses one or more processor cores 112 (FIG. 1) corresponding to the different power domains, wherein reallocation of power between the cores/power domains is done based on the current phase being processed – i.e. when the cores execute the same phase (same task) and upon detecting which phase/task is being repeated/currently executed by the cores, power is reallocated between them (paragraphs 0029-0030). Contrary to applicant’s argument, Eastep does not state or suggest that each of the cores executes different phase. Thus, Eastep meets the argued claim language.
The same was argued for the other independent claims 8 and 15.
Applicant’s arguments, see Remarks, filed 08/28/2025, with respect to the rejection under 35 U.S.C. 103 of amended claims 6, 13, and 20 have been fully considered and are persuasive. Accordingly, the rejection 35 U.S.C. 103 of claims 6, 13, and 20 has been withdrawn.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/STEFAN STOYNOV/ Primary Examiner, Art Unit 2175