CTNF 18/065,323 CTNF 87590 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election with traverse of Species I, encompassing claims 1-12, in the reply filed on 3/15/2026 is acknowledged. The traversal is on the grounds that “the Office Action has not established that there would be a serious search burden on the Examiner should the Examiner conduct the examination of the claimed subject matter of Species I and II”. This is not found persuasive because, as stated in said Office Action, Species I does not require the negative power boost IC device of Species II, but it also does not require "a plurality of integrated circuit (IC) devices" that are required by Species II. Furthermore, the Applicant did not elect Species III in the previous response which requires an inverting power boost converter which, according to the specification, is equivalent to a negative power boost IC device, but provided no arguments regarding that election. It is clear that Species I in particular does not require the negative power boost IC device of Species Il or the inverting power boost converter of previously-unelected Species III. These reasons all show why there is a serious search burden. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 & 4-10 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by White (US Patent # 6,067,236) . Regarding Claim 1, White discloses a system package for a power supply, comprising: circuitries (i.e. voltage regulator 10, DC-to-AC converter 20, multiplier 30, sampling circuitry 40, regulator controller 50) comprising circuit elements; and a plurality of connection pins comprising: low-voltage pins (i.e. INPUT4 pin & GND3 pin to which low-voltage source voltage V DC is applied); input/output (IO) pins (i.e. 1MON1 pin, PS OK pin, SHUTDOWN5 pin, VADJ6 pin of six-pin connector P2) arranged in regions proximate to edges of the system package; and high-voltage pins (i.e. terminal 3Z1 which connects the high-voltage output of multiplier 30 to a high-voltage trace) arranged in an inner region of the system package away from all edges (i.e. by gap 110) of the system package (i.e. as shown at least in Fig. 5) (Fig. 1-8, 11; Abstract; Column 1, line 25- Column 2, line 62; Column 4, line 1- Column 7, line 62; Column 11, line 25-46). Regarding Claim 4, White discloses that a distance (i.e. spacing between circuit elements must be such that no short circuits occur and/or gap 110) between an individual high- voltage pin of the high-voltage pins and an edge of the system package satisfies a predetermined creepage distance associated with a voltage output by the individual high-voltage pin (Fig. 3, 5; Column 11, line 25-46). Although White does not explicitly use the phrase “creepage distance”, this is an inherent consideration when designing a circuit according to the working voltage that will be used in the intended application. White even mentions that, due to the high voltage that is achieved at the left-most end of the multiplier Z1, spacing between circuit elements must be such that no short circuits occur. White also considers the insulative material or additional insulation to allow for smaller spacing since it is a key factor in determining said spacing or creepage distance. Even further, the minimum required creepage distance is dictated by international safety standards such as IEC 60664-1 and is defined as the critical safety measurement of the shortest path along the surface of a solid insulating between two conductive parts which prevents high-voltage electricity from creeping across the surface and causing an electrical arc or short circuit. Regarding Claim 5, White discloses that the plurality of connection pins further comprises ground pins (i.e. GND3 pin) in a region of the system package between the IO pins and the high-voltage pins (Fig. 2, 2A, 3, 3A; Column 7, line 31-42). Regarding Claim 6, White discloses that the IO pins comprise at least one of a control pin (i.e. SHUTDOWN5 pin & VADJ6 pin) or a data signal pin (i.e. 1MON1 pin & PS OK pin of sampling circuitry 40) associated with serial communication (Fig. 2, 2A, 3, 3A; Column 7, line 31-42). Regarding Claim 7, White discloses that the IO pins comprise at least one control pin (i.e. SHUTDOWN5 pin & VADJ6 pin) configured to control an output voltage at an individual high-voltage pin of the high-voltage pins (Fig. 2, 2A, 3, 3A; Column 7, line 31-42). Regarding Claim 8, White discloses that the IO pins comprise at least one control pin configured to control a current associated with an output voltage at an individual high-voltage pin of the high-voltage pin (Fig. 2, 2A, 3, 3A; Column 7, line 31- Column 8, line 34). Regarding Claim 9, White discloses that the IO pins comprise at least one readout pin (i.e. 1MON1 pin & PS OK pin of sampling circuitry 40 and/or appropriate monitoring devices) configured to read a configuration associated with an output voltage at an individual high-voltage pin of the high-voltage pins (Fig. 2, 2A, 3, 3A; Column 5, line 63- Column 6, line 11; Column 7, line 31-42). Regarding Claim 10, White discloses that the low-voltage pins comprise at least one input voltage pin (i.e. INPUT4 pin to which low-voltage source voltage V DC is applied) configured to receive an input voltage (i.e. voltage V DC ), and an output voltage (i.e. voltage V OUT ) at an individual high-voltage pin (i.e. terminal 3Z1 which connects the high-voltage output of multiplier 30 to a high-voltage trace) of the high-voltage pins is based at least in part on a voltage level of the input voltage (Fig. 2, 2A, 3, 3A; Column 7, line 31-42) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over White (US Patent # 6,067,236) . Regarding Claim 2, White does not explicitly disclose that the high-voltage pins are configured to output a voltage between 0 Volt and -400 Volt (V). However, White states that an object of the invention is to provide a power supply device having a high output-to-input voltage ratio of at least 1000 and the output voltage is dependent on the input voltage while also being able to be further adjusted by varying the R14 potentiometer shown in Fig. 2. Therefore, White is capable of configuring the circuit to output a voltage within the claimed range. Regarding the negative voltage, White shows in Fig. 7 that an inverting converter may be used in place of converter shown in Fig. 2. It would have been obvious to one of ordinary skill in the art at the time the invention was made to have the high-voltage pins configured to output a voltage between 0 Volt and -400 Volt (V), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding Claim 3, White does not explicitly disclose that the high-voltage pins are configured to output a voltage at -375 Volt (V). However, White states that an object of the invention is to provide a power supply device having a high output-to-input voltage ratio of at least 1000 and the output voltage is dependent on the input voltage while also being able to be further adjusted by varying the R14 potentiometer shown in Fig. 2. Therefore, White is capable of configuring the circuit to output the claimed voltage. Regarding the negative voltage, White shows in Fig. 7 that an inverting converter may be used in place of converter shown in Fig. 2. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have the high-voltage pins are configured to output a voltage at -375 Volt (V), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) . 07-21-aia AIA Claim s 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over White (US Patent # 6,067,236) in view of Nakamura (US Patent Application Publication # 2015/0108604) . Regarding Claim 11, White does not explicitly disclose a temperature indicator. Nakamura teaches a temperature indicator (i.e. temperature sensor or thermistor for temperature detection) (Fig. 10; Abstract; Paragraph 0058, 0143). Nakamura teaches that it is well known in the art of circuit boards and semiconductor modules with power supplies to include a sensor such as temperature sensor or thermistor in order to provide temperature detection and monitoring. White states that pins of sampling circuitry 40 can provide data to monitoring devices. It would have been obvious to one skilled in the art to provide a temperature indicator such as a temperature sensor or thermistor for temperature detection in the system of White, as taught by Nakamura, in order to provide temperature data which can be used to protect the circuitry from overheating by shutting down the system. Regarding Claim 12, White does not explicitly disclose that the system package is a ball grid array (BGA) package. Nakamura teaches the system package is a ball grid array (BGA) package (Fig. 10; Abstract; Paragraph 0024, 0047, 0111). Nakamura teaches that it is well known in the art of circuit boards and semiconductor modules with power supplies to use a ball grid array (BGA) package configuration. Ball grid arrays (BGA) are known in the art for offering low thermal resistance which enhances heat dissipation and providing shorter electrical paths which improves electrical performance. It would have been obvious to one skilled in the art to use a ball grid array (BGA) package configuration for the system of White, as taught by Nakamura, in order to improve the heat dissipation and improved electrical performance. Relevant Cited Art The cited art in PTO-892 was found during the examiner's search, but was not relied upon for this office action. However, it is still considered pertinent to the applicant's disclosure. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RHADAMES J ALONZO MILLER whose telephone number is (571)270-7829. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RJA/ Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/ Supervisory Patent Examiner, Art Unit 2847 Application/Control Number: 18/065,323 Page 2 Art Unit: 2847 Application/Control Number: 18/065,323 Page 3 Art Unit: 2847 Application/Control Number: 18/065,323 Page 4 Art Unit: 2847 Application/Control Number: 18/065,323 Page 5 Art Unit: 2847 Application/Control Number: 18/065,323 Page 6 Art Unit: 2847 Application/Control Number: 18/065,323 Page 7 Art Unit: 2847 Application/Control Number: 18/065,323 Page 8 Art Unit: 2847 Application/Control Number: 18/065,323 Page 9 Art Unit: 2847 Application/Control Number: 18/065,323 Page 10 Art Unit: 2847
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