DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/21/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,8,11-13, and 18 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2020/0313639 A1; 03/2016 in view of Lan et al.; US 2021/0327873 A1; 04/2020 and further in view of Chitnis; US 2008/0284541 A1; 05/2007
Claim 1: Kim discloses a method of forming a BAW resonator/integrated circuit structure ( Fig. 1A an acoustic resonator device #101), the method comprising: forming a piezoelectric layer ( Fig. 1A piezoelectric layer #120 ) on a surface of a growth substrate ( Fig. 1A thinned substrate #112 ); forming a first electrode ( Fig. 1A a topside metal electrode #130 ) on the piezoelectric layer ( Fig. 1A #120 ); forming a sacrificial layer ( [0081] forming a sacrificial layer #1910 overlying a portion of the first electrode #1810 and a portion of the piezoelectric film #1620 ) overlapping the first electrode ( Fig. 1A #130) and the piezoelectric layer ( Fig. 1A #120 ); forming a support layer ( [0081] Further, phosphorous doped SiO.sub.2 (PSG) can be used as the sacrificial layer with different combinations of support layer ) on the piezoelectric layer ( Fig. 1A #120 ), the sacrificial layer ( as described above ) and the first electrode ( Fig. 1A #130 );
providing an integrated circuit wafer including: a substrate ( Fig. 1A #112 ); a plurality of first layers on the substrate ( Fig. 1A #112 ), bonding an upper surface of the support layer ( as discussed above ) to an upper surface of the integrated circuit wafer to form a bonded interface therebetween ( [0041] A backside cap structure #161 is bonded to the thinned seed substrate #112, underlying the first and second backside trenches #113, #114 ); forming a first opening ( Fig. 1A topside trench shown in annotated figure) through the piezoelectric layer ( Fig. 1A #120 ) to expose the first electrode ( Fig. #130 ) on a lower surface of the piezoelectric layer ( Fig. 1A a backside metal electrode #131 ) that is opposite the upper surface ( Fig. 1A topside metal electrode #130 ); forming a first conductive layer ( Fig. 1A topside metal #145) on the upper surface of the piezoelectric layer ( Fig. 1A #120 ) and in the first opening ( Fig. 1A topside micro-trench #121 ) to ohmically couple to the first electrode ( Fig. 1A #130); removing a portion of the first conductive layer ( Fig. 1A #145 ) to form a second electrode ( Fig. 1A topside metal plug #146) on the upper surface of the piezoelectric layer ( Fig. 1A #120 ) that is insulated from the first electrode ( Fig. 1A #130 ) and to form a first contact ( Fig. 1A bond pad #144 ) that is ohmically coupled ( Fig. 1A #144 and #130 are in contact ) to the first electrode ( Fig. 1A #130 ); forming a passivation layer ( [0080] forming a first passivation layer #1810 ) on the upper surface of the piezoelectric layer ( [0080] overlying the piezoelectric film #1620 ) to cover the second electrode ( Fig. 1A #146 ) and partially cover the first contact ( Fig. 1A #144 ); forming a second opening ( Fig. 1A backside trench #113 ) through the piezoelectric layer ( Fig. 1A #120 ) and through the support layer ( as discussed above ) to expose at least one of the ohmic conductors ( Fig. 1A backside metal plug #147 ) included in the plurality of second layers forming the back-end of line portion of the integrated circuit wafer ( Fig. 1A bond pads #143, #144, and topside metal #145 with topside metal plug #146 ); forming a second conductive layer ( Fig. 1A #144 ) to ohmically couple to the upper surface of the piezoelectric layer ( Fig. 1A #120 ) and in the second opening ( Fig. 1A backside trench #113 ) and removing the sacrificial layer ( sacrificial layer is removed during manufacturing process).
Kim does not appear to disclose the plurality of first layers forming a front-end of line portion of the integrated circuit wafer having electronic semiconductor switching devices therein ; and a plurality of second layers forming a back-end of line portion of the integrated circuit wafer including ohmic conductors ohmically coupling regions of the electronic semiconductor switching devices to an outer one of the second layers of the integrated circuit wafer positioned opposite the electronic semiconductor switching devices; to ohmically couple the first electrode, through the first contact and the at least one of the ohmic conductors to at least one of the electronic semiconductor switching devices; processing the growth substrate to remove the growth substrate and expose an upper surface of the piezoelectric layer that is covered by the growth substrate.
Lan discloses the plurality of first layers forming a front-end of line portion of the integrated circuit wafer having electronic semiconductor switching devices therein ( [0053] Fig. 4 illustrates a 3D integrated circuit (3D IC) chip including a compound semiconductor field effect transistor (FET) power amplifier (PA) integrated with narrow band acoustic filters and broadband integrated passive device filters, according to aspects of the present disclosure ); and a plurality of second layers forming a back-end of line portion of the integrated circuit wafer ( Fig. 4 BEOL layers #450 ) including ohmic conductors ohmically coupling regions of the electronic semiconductor switching devices ( Fig. 4 source and drain of #410) to an outer one of the second layers of the integrated circuit wafer ( Fig. 4 left most ) positioned opposite the electronic semiconductor switching devices ( as shown in Fig. 4 ); to ohmically couple the first electrode ( Fig. 5J an electrode #438 ), through the first contact and the at least one of the ohmic conductors ( [0067] In addition, through vias (e.g., through aluminum nitride (AlN) via (TAV)) are formed to land on source/drain ohmic contacts of the source/drain regions of the compound semiconductor HEMT active device 410 ) to at least one of the electronic semiconductor switching devices ( Fig. 5K #430 is connected to the drain in #410 ).
Lan does not appear to disclose processing the growth substrate to remove the growth substrate and expose an upper surface of the piezoelectric layer that is covered by the growth substrate.
However, Chitnis teaches processing the growth substrate ( Fig. 3 growth substrate 12 ) to remove the growth substrate ( [0038] In some embodiments, the epitaxial layer 14 can also be thinned or further processed, such as by etching or grinding, after removal of the growth substrate 12 ) and expose an upper surface of the piezoelectric layer ( Fig. 3 epitaxial layer 14; an epitaxial layer can be a piezoelectric layer ) that is covered by the growth substrate ( Fig. 3 #12 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chitnis with Kim and Lan to implement the plurality of first layers forming a front-end of line portion of the integrated circuit wafer having electronic semiconductor switching devices therein ; and a plurality of second layers forming a back-end of line portion of the integrated circuit wafer including ohmic conductors ohmically coupling regions of the electronic semiconductor switching devices to an outer one of the second layers of the integrated circuit wafer positioned opposite the electronic semiconductor switching devices; to ohmically couple the first electrode, through the first contact and the at least one of the ohmic conductors to at least one of the electronic semiconductor switching devices; processing the growth substrate to remove the growth substrate and expose an upper surface of the piezoelectric layer that is covered by the growth substrate; because the connection between the device and the electrode is necessary to properly power the device and interconnect it to form complex electronic circuits.
Claim 2: Kim, Lan, and Chitnis disclose the method of claim 1 (as discussed above).
Neither Kim nor Chitnis appear to disclose the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise CMOS transistors.
However, Lan teaches the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise CMOS transistors ( [0034] Subsequent doping of the substrate #200 with charge carrier ions/atoms may change the charge carrying capabilities of the substrate #200 according to a CMOS process [0038] The substrate #200, the wells #202-208, and the layers may enable formation of a compound semiconductor transistor ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lan with Kim and Chitnis to implement the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise CMOS transistors because CMOS devices create the core logic and functionality of an IC and CMOS is well known as a foundation for modern digital electronics.
Claim 8: Kim, Lan, and Chitnis disclose the method of claim 1 (as discussed above).
Neither Kim nor Chitnis appear to disclose the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise GaN HEMT devices, CMOS devices, power MOSFET devices, IGBT devices, HEMT devices, resistive memory devices, phase change materials, magnetic devices, and/or spintronic devices.
However, Lan teaches the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise GaN HEMT devices, CMOS devices, power MOSFET devices, IGBT devices, HEMT devices, resistive memory devices, phase change materials, magnetic devices, and/or spintronic devices ( [0054] the die #440 includes the acoustic device #430 integrated in the single crystal, compound semiconductor layer #442. In one configuration, the acoustic device #430 is arranged side-by-side with the compound semiconductor HEMT active device #410 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lan with Kim and Chitnis to implement the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise GaN HEMT devices, CMOS devices, power MOSFET devices, IGBT devices, HEMT devices, resistive memory devices, phase change materials, magnetic devices, and/or spintronic devices because these options enable diverse, high-performance applications on a single die.
Claim 11: Kim and Lan disclose the method of Claim 10 (as discussed above).
Kim discloses wherein forming the first electrode ( Fig. 1A a topside metal electrode #130 ) on the piezoelectric layer ( Fig. 1A #120 ) is followed by forming a sacrificial layer ( [0081] forming a sacrificial layer #1910 overlying a portion of the first electrode #1810 and a portion of the piezoelectric film #1620 ) overlapping the first electrode ( Fig. 1A #130) and the piezoelectric layer ( Fig. 1A #120 ), the method further comprising: forming a first opening ( Fig. 1A topside trench shown in annotated figure) through the piezoelectric layer ( Fig. 1A #120 ) to expose the first electrode ( Fig. #130 ) on the lower surface of the piezoelectric layer ( Fig. 1A a backside metal electrode #131 ); forming a first conductive layer ( Fig. 1A topside metal #145) on the upper surface of the piezoelectric layer ( Fig. 1A #120 ) and in the first opening ( Fig. 1A topside micro-trench #121 ) to ohmically couple to the first electrode ( Fig. 1A #130); removing a portion of the first conductive layer ( Fig. 1A #145 ) to form a second electrode ( Fig. 1A #146 ) on the upper surface of the piezoelectric layer ( Fig. 1A #120 ) that is insulated from the first electrode ( Fig. 1A #130 ) and to form a first contact ( Fig. 1A bond pad #144 ) that is ohmically coupled ( Fig. 1A #144 and #130 are in contact ) to the first electrode ( Fig. 1A #130); forming a passivation layer ( [0080] forming a first passivation layer #1810 ) on the upper surface of the piezoelectric layer ( [0080] overlying the piezoelectric film #1620 ) to cover the second electrode ( Fig. 1A #146 ) and partially cover the first contact ( Fig. 1A #144 ); forming a second opening ( Fig. 1A backside trench #113 ) through the piezoelectric layer ( Fig. 1A #120 ) and through the support layer ( as discussed above ) to expose the upper surface of the integrated circuit wafer ( Fig. 1A #101 ); and forming a second conductive layer ( Fig. 1A #144 ) on the upper surface of the piezoelectric layer ( Fig. 1A #120) and in the second opening ( Fig. 1A #113) to ohmically couple the first electrode ( Fig. 1A #130 )
Kim does not appear to disclose processing the growth substrate to remove the growth substrate and to expose an upper surface of the piezoelectric layer that is covered by the growth substrate; at least one of the electronic semiconductor switching devices.
Chitnis discloses processing the growth substrate ( Fig. 3 growth substrate 12 ) to remove the growth substrate ( [0038] In some embodiments, the epitaxial layer 14 can also be thinned or further processed, such as by etching or grinding, after removal of the growth substrate 12 ) and expose an upper surface of the piezoelectric layer ( Fig. 3 epitaxial layer 14; an epitaxial layer can be a piezoelectric layer ) that is covered by the growth substrate ( Fig. 3 #12 ).
Chitnis does not appear to disclose at least one of the electronic semiconductor switching devices.
However, Lan teaches at least one of the electronic semiconductor switching devices therein ( [0053] Fig. 4 illustrates a 3D integrated circuit (3D IC) chip including a compound semiconductor field effect transistor (FET) power amplifier (PA) integrated with narrow band acoustic filters and broadband integrated passive device filters, according to aspects of the present disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lan with Kim and Chitnis to implement at least one of the electronic semiconductor switching devices because there must be at least one contact to allow the device to operate and be part of the larger circuit.
Claim 12: Kim, Lan, and Chitnis disclose the method of Claim 11 (as discussed above).
Neither Kim nor Chitnis appear to disclose the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise GaN HEMT transistors.
However, Lan teaches the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise GaN HEMT transistors ( Fig. 5J HEMT active device #410 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lan with Kim and Chitnis to implement the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise GaN HEMT transistors because these transistors provide significant advantages over traditional silicon-based devices for applications requiring high efficiency, speed, and power density.
Claim 13: Kim, Lan, and Chitnis disclose the method of Claim 11 ( as discussed above).
Neither Kim nor Chitnis appear to disclose the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise CMOS transistors.
However, Lan teaches the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise CMOS transistors ( [0034] Subsequent doping of the substrate #200 with charge carrier ions/atoms may change the charge carrying capabilities of the substrate #200 according to a CMOS process [0038] The substrate #200, the wells #202-208, and the layers may enable formation of a compound semiconductor transistor ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lan with Kim and Chitnis to implement the electronic semiconductor switching devices included in the front-end of line portion of the integrated circuit wafer comprise CMOS transistors because their performance is unmatched in the categories of power consumption, fast switching speeds, and high integration density.
Claim 18: Kim discloses a method of forming a BAW resonator/integrated circuit structure ( [0046] Figs. 2 and 3 are simplified diagrams illustrating steps for a method of manufacture for an acoustic resonator device ) , the method comprising: forming a piezoelectric layer ( Fig. 1A piezoelectric layer #120 ) on a surface of a growth substrate ( Fig. 1A thinned substrate #112 ); forming a first electrode ( Fig. 1A a topside metal electrode #130 ) on the piezoelectric layer ( Fig. 1A a topside metal electrode #130 ) forming a sacrificial layer [0081] forming a sacrificial layer #1910 overlying a portion of the first electrode #1810 and a portion of the piezoelectric film #1620 ) overlapping the first electrode ( Fig. 1A #130 ) and the piezoelectric layer ( Fig. 1A #120 ); forming a support layer ( [0081] Further, phosphorous doped SiO.sub.2 (PSG) can be used as the sacrificial layer with different combinations of support layer ) on the piezoelectric layer ( Fig. 1A piezoelectric layer #120 ), the sacrificial layer ( as discussed above ) and the first electrode ( Fig. 1A #130 ); providing an integrated circuit wafer including: a substrate ( Fig. 1A #112) ; bonding an upper surface of the support layer (as discussed above) to an upper surface of the integrated circuit wafer to form a bonded interface therebetween ( [0041] A backside cap structure #161 is bonded to the thinned seed substrate #112, underlying the first and second backside trenches #113, #114 ); forming a second electrode (Fig. 1A topside metal plug #146) on the upper surface of the piezoelectric layer ( Fig. 1A #120 ) that is insulated from the first electrode ( Fig. 1A #130 ); forming a passivation layer ( [0080] forming a first passivation layer #1810 ) on the upper surface of the piezoelectric layer ( [0080] overlying the piezoelectric film #1620 ) to cover the second electrode ( Fig. 1A #146); forming an opening ( Fig. 1A backside trench #113 ) through the piezoelectric layer ( Fig. 1A #120 ) and through the support layer ( as discussed above) to expose at least one of the ohmic conductors ( Fig. 1A backside metal plug #147 ) included in the plurality of second layers forming the back-end of line portion of the integrated circuit wafer ( Fig. 1A bond pads #143, #144, and topside metal #145 with topside metal plug #146 ); and forming a conductive layer ( Fig. 1A #144 ) on the upper surface of the piezoelectric layer ( Fig. 1A #120) and in the opening ( Fig. 1A #113) to ohmically couple the first ( Fig. 1A #130) or second electrode ( Fig. 1A #146 )
Kim does not appear to disclose a plurality of first layers on the substrate, the plurality of first layers forming a front-end of line portion of the integrated circuit wafer having electronic semiconductor switching devices therein; and a plurality of second layers forming a back-end of line portion of the integrated circuit wafer including ohmic conductors ohmically coupling regions of the electronic semiconductor switching devices to an outer one of the second layers of the integrated circuit wafer positioned opposite the electronic semiconductor switching devices; to the at least one of the electronic semiconductor switching devices in the front-end of line portion of the integrated circuit wafer; processing the growth substrate to remove the growth substrate and to expose an upper surface of the piezoelectric layer that is covered by the growth substrate.
Lan discloses a plurality of first layers on the substrate ( Fig. 4 #440 ), the plurality of first layers forming a front-end of line portion of the integrated circuit wafer having electronic semiconductor switching devices therein ( [0053] Fig. 4 illustrates a 3D integrated circuit (3D IC) chip including a compound semiconductor field effect transistor (FET) power amplifier (PA) integrated with narrow band acoustic filters and broadband integrated passive device filters, according to aspects of the present disclosure ); and a plurality of second layers forming a back-end of line portion of the integrated circuit wafer ( Fig. 4 BEOL layers #450 ) including ohmic conductors ohmically coupling regions of the electronic semiconductor switching devices ( Fig. 4 source and drain of #410) to an outer one of the second layers of the integrated circuit wafer ( Fig. 4 left most ) positioned opposite the electronic semiconductor switching devices ( as shown in Fig. 4 ); to the at least one of the electronic semiconductor switching devices in the front-end of line portion of the integrated circuit wafer ( [0053] Fig. 4 illustrates a 3D integrated circuit (3D IC) chip including a compound semiconductor field effect transistor (FET) power amplifier (PA) integrated with narrow band acoustic filters and broadband integrated passive device filters, according to aspects of the present disclosure).
Lan does not appear to disclose processing the growth substrate to remove the growth substrate and to expose an upper surface of the piezoelectric layer that is covered by the growth substrate.
However, Chitnis teaches processing the growth substrate ( Fig. 3 growth substrate 12 ) to remove the growth substrate ( [0038] In some embodiments, the epitaxial layer 14 can also be thinned or further processed, such as by etching or grinding, after removal of the growth substrate 12 ) and expose an upper surface of the piezoelectric layer ( Fig. 3 epitaxial layer 14; an epitaxial layer can be a piezoelectric layer ) that is covered by the growth substrate ( Fig. 3 #12 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chitnis with Kim and Lan to implement a plurality of first layers on the substrate, the plurality of first layers forming a front-end of line portion of the integrated circuit wafer having electronic semiconductor switching devices therein; and a plurality of second layers forming a back-end of line portion of the integrated circuit wafer including ohmic conductors ohmically coupling regions of the electronic semiconductor switching devices to an outer one of the second layers of the integrated circuit wafer positioned opposite the electronic semiconductor switching devices; to the at least one of the electronic semiconductor switching devices in the front-end of line portion of the integrated circuit wafer; processing the growth substrate to remove the growth substrate and to expose an upper surface of the piezoelectric layer that is covered by the growth substrate because ohmic conductors are used to ensure efficient and reliable electrical connectivity.
Claim 10 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2020/0313639 A1; 03/2016 in view of Lan et al.; US 2021/0327873 A1; 04/2020
Claim 10: Kim discloses a method of forming a MEMS/integrated circuit structure ( [0046] Figs. 2 and 3 are simplified diagrams illustrating steps for a method of manufacture for an acoustic resonator device ), the method comprising: forming a piezoelectric layer ( Fig. 1A piezoelectric layer #120 ) on a surface of a growth substrate ( Fig. 1A thinned substrate #112 ); forming a first electrode ( Fig. 1A a topside metal electrode #130 ) on the piezoelectric layer ( Fig. 1A #120 ); forming a support layer ( [0081] Further, phosphorous doped SiO.sub.2 (PSG) can be used as the sacrificial layer with different combinations of support layer ) on the piezoelectric layer ( Fig. 1A #120 ) and the first electrode ( Fig. 1A #130 ); bonding an upper surface of the support layer (as discussed above) to an upper surface of an integrated circuit wafer to form a bonded interface therebetween ( [0041] A backside cap structure #161 is bonded to the thinned seed substrate #112, underlying the first and second backside trenches #113, #114 ), wherein the integrated circuit wafer includes: a substrate ( Fig. 1A #112 ); a plurality of first layers on the substrate ( Fig. 1A #120 and #145 ).
Kim does not appear to disclose the plurality of first layers forming a front-end of line portion of the integrated circuit wafer having electronic semiconductor switching devices therein; and a plurality of second layers forming a back-end of line portion of the integrated circuit wafer including ohmic conductors ohmically coupling regions of the electronic semiconductor switching devices to an outer one of the second layers of the integrated circuit wafer positioned opposite the electronic semiconductor switching devices.
However, Lan teaches the plurality of first layers forming a front-end of line portion of the integrated circuit wafer having electronic semiconductor switching devices therein ( [0053] Fig. 4 illustrates a 3D integrated circuit (3D IC) chip including a compound semiconductor field effect transistor (FET) power amplifier (PA) integrated with narrow band acoustic filters and broadband integrated passive device filters, according to aspects of the present disclosure ); and a plurality of second layers forming a back-end of line portion of the integrated circuit wafer ( Fig. 4 BEOL layers #450 ) including ohmic conductors ohmically coupling regions of the electronic semiconductor switching devices ( Fig. 4 source and drain of #410) to an outer one of the second layers of the integrated circuit wafer ( Fig. 4 left most ) positioned opposite the electronic semiconductor switching devices ( as shown in Fig. 4 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lan with Kim to implement the plurality of first layers forming a front-end of line portion of the integrated circuit wafer having electronic semiconductor switching devices therein; and a plurality of second layers forming a back-end of line portion of the integrated circuit wafer including ohmic conductors ohmically coupling regions of the electronic semiconductor switching devices to an outer one of the second layers of the integrated circuit wafer positioned opposite the electronic semiconductor switching devices because ohmic connections are required for reliable electrical connections between active components and BEOL metal interconnects.
Claims 3-7 and 14-16 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2020/0313639 A1; 03/2016 in view of Lan et al.; US 2021/0327873 A1; 04/2020 and Chitnis; US 2008/0284541 A1; 05/2007 as applied to claims 2 and 13 above, and further in view of Kay et al.; US 2023/0041856 A1; 10/2021
Claim 3: Kim, Lan, and Chitnis disclose the method of claim 2 ( as discussed above)
Neither Kim nor Lan nor Chitnis appear to disclose the integrated circuit wafer further comprises: a sealing layer on the plurality of second layers; and a phosphate silicate glass layer on the sealing layer.
However, Kay teaches the integrated circuit wafer further comprises: a sealing layer ( [0047] An intermediary layer may be or include a bonding layer, a BOX layer, an etch stop layer, a sealing layer, an adhesive layer or layer of other material that is attached or bonded to plate #310 and substrate #320 ) on the plurality of second layers ( Fig. 3A intermediate material layers #322 ) ; and a phosphate silicate glass layer ( [0067] the highly conforming dielectric layer #560 and #562 is one of phosphosilicate glass (PSG) ) on the sealing layer ( Fig. 2 back-side dielectric layer #216 ) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kay with Kim, Lan, and Chitnis to implement the integrated circuit wafer further comprises: a sealing layer on the plurality of second layers; and a phosphate silicate glass layer on the sealing layer because this type of glass is used for passivation, planarization, and thermal management.
Claim 4: Kim, Lan, Chitnis, and Kay disclose the method of claim 3 ( as discussed above).
Kim discloses bonding the upper surface of the support layer ( [0081] Further, phosphorous doped SiO.sub.2 (PSG) can be used as the sacrificial layer with different combinations of support layer ) to the upper surface of the integrated circuit wafer is preceded by:
Neither Kim nor Lan nor Chitnis appear to disclose forming a SiO2 bond layer on the phosphate silicate glass layer to provide the upper surface of the integrated circuit wafer.
However, Kay teaches forming a SiO2 bond layer ( [0068] bonding layer (BOX) #522 is SiO2) layer on the phosphate silicate glass layer ( [0067] the highly conforming dielectric layer #560 and #562 is one of phosphosilicate glass (PSG) ) to provide the upper surface of the integrated circuit wafer ( Fig. 4 #1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kay with Kim, Lan, and Chitnis to implement forming a SiO2 bond layer on the phosphate silicate glass layer to provide the upper surface of the integrated circuit wafer because the bonding layer prevents phosphorous out-diffusion, improves stability, and enhances the overall reliability of the IC.
Claim 5: Kim, Lan, Chitnis, and Kay disclose the method of claim 3 (as discussed above)
Kim teaches forming the support layer ( [0081] Further, phosphorous doped SiO.sub.2 (PSG) can be used as the sacrificial layer with different combinations of support layer ) comprises forming a SiO2 layer ( [0082] the support layer #2010 can include silicon dioxide) on the piezoelectric layer ( Fig. 1A #120 ), the sacrificial layer ( [0081] forming a sacrificial layer #1910 overlying a portion of the first electrode #1810 and a portion of the piezoelectric film #1620 ) and the first electrode (Fig. 1A #130).
Claim 6: Kim, Lan, Chitnis, and Kay disclose the method of claim 3 ( as discussed above).
Neither Kim nor Lan nor Chitnis appear to disclose the phosphate silicate glass layer has a thickness in a range between about 1 um and about 3 um.
However, Kay teaches the phosphate silicate glass layer has a thickness in a range between about 1 um and about 3 um ( [0072] a thickness ths of the polished highly conforming dielectric layer #562 above the pillar #550 is between 10 nm and 10 um) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kay with Kim, Lan, and Chitnis to implement the phosphate silicate glass layer has a thickness in a range between about 1 um and about 3 um because this thickness balances competing requirements such as dopant delivery, mechanical stress, reflow properties, and etch selectivity.
Claim 7: Kim, Lan, Chitnis, and Kay disclose the method of claim 3 ( as discussed above).
Kim teaches the substrate comprises a Si substrate ( [0046] the seed substrate can include silicon).
Claim 14: Kim, Lan, and Chitnis disclose the method of Claim 13 (as discussed above).
Neither Kim nor Lan nor Chitnis appear to disclose the integrated circuit wafer further comprises: a sealing layer on the plurality of second layers; and a phosphate silicate glass layer on the sealing layer.
However, Kay teaches the integrated circuit wafer further comprises: a sealing layer ( [0047] An intermediary layer may be or include a bonding layer, a BOX layer, an etch stop layer, a sealing layer, an adhesive layer or layer of other material that is attached or bonded to plate #310 and substrate #320 ) on the plurality of second layers ( Fig. 3A intermediate material layers #322 ) ; and a phosphate silicate glass layer ( [0067] the highly conforming dielectric layer #560 and #562 is one of phosphosilicate glass (PSG) ) on the sealing layer ( Fig. 2 back-side dielectric layer #216 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kay with Kim, Lan, and Chitnis to implement the integrated circuit wafer further comprises: a sealing layer on the plurality of second layers; and a phosphate silicate glass layer on the sealing layer because the sealing layer would act as a contamination barrier to the glass layer.
Claim 15: Kim, Lan, Chitnis, and Kay disclose the method of Claim 14 (as discussed above).
Kim discloses bonding the upper surface of the support layer ( [0081] Further, phosphorous doped SiO.sub.2 (PSG) can be used as the sacrificial layer with different combinations of support layer ) to the upper surface of the integrated circuit wafer is preceded by:
Neither Kim nor Lan nor Chitnis appear to disclose forming a SiO2 bond layer on the phosphate silicate glass layer to provide the upper surface of the integrated circuit wafer.
However, Kay teaches forming a SiO2 bond layer ( [0068] bonding layer (BOX) #522 is SiO2) layer on the phosphate silicate glass layer ( [0067] the highly conforming dielectric layer #560 and #562 is one of phosphosilicate glass (PSG) ) to provide the upper surface of the integrated circuit wafer ( Fig. 4 #1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kay with Kim, Lan, and Chitnis to implement forming a SiO2 bond layer on the phosphate silicate glass layer to provide the upper surface of the integrated circuit wafer because the bonding layer would prevent phosphorous from diffusing out of the glass layer.
Claim 16: Kim, Lan, Chitnis, and Kay disclose the method of Claim 14 (as discussed above).
Kim teaches forming the support layer ( [0081] Further, phosphorous doped SiO.sub.2 (PSG) can be used as the sacrificial layer with different combinations of support layer ) comprises forming a SiO2 layer ( [0082] the support layer #2010 can include silicon dioxide) on the piezoelectric layer ( Fig. 1A #120 ), the sacrificial layer ( [0081] forming a sacrificial layer #1910 overlying a portion of the first electrode #1810 and a portion of the piezoelectric film #1620 ) and the first electrode (Fig. 1A #130).
Response to Amendment / Arguments
Applicant's arguments filed 07/21/26 have been fully considered but they are not persuasive. Applicant’s first argument on page 12 that multiple embodiments of Kim are improperly Combined Rendering the Rejection of all Claims Improper is not persuasive. The figures are not applicable is reputed with the following paragraph of Kim [0035] FIGS. 16A-16C through FIGS. 31A-31C are simplified diagrams illustrating various cross-sectional views of a single crystal acoustic resonator device and of method steps for a transfer process using a sacrificial layer for single crystal acoustic resonator devices according to an example of the present invention. This does not mean that the embodiment is different from the one in Fig. 1A since they both state it is according to an example of the present invention as mentioned in [0018]. Applicant’s second argument on pages 12-16 that the seed substrate of Kim cannot be properly construed as multiple distinct elements of the claimed method is not persuasive. Chitnis teaches the new feature “remove the growth substrate and expose an upper surface of the piezoelectric layer.” Further, in Kim the backside cap structure is only part of the integrated circuit wafer as described in the claim feature. Additionally, the substrate 112 is used for both the growth substrate and a substrate for the IC wafer in Fig. 1A. Applicant’s third argument that the action fails to establish a Prima Facie case of obviousness for each and every limitation of the claims is not persuasive. Chitnis addresses the amendment and the other arguments related to Kim and Lan are addressed above.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
