DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 30 June 2026 is acknowledged. Claims 6, 7, and 18-20 have been canceled. Claims 1, 4, and 8-13 have been amended. Claims 21-25 have been added. Claims 1-5, 8-17, and 21-25 are pending.
Information Disclosure Statement
Information disclosure statement filed 14 July 2026 has been fully considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-17, 22, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US Patent Application Publication 2022/0093472, hereinafter Hsu ‘472) in view of Pao et al. (US Patent Application Publication 2021/0391439, hereinafter Pao ‘439), both of record.
With respect to claim 1, Hsu ‘472 teaches (FIGs. 27-36) an integrated circuit (IC) structure substantially as claimed, comprising:
a channel material (215) ([0063-0071]);
a gate electrode material (350) ([0063-0071]); and
a multi-dipole gate structure (216′, 220, 220′, 280, and 282) between the gate electrode material (350) and the channel material (215) ([0063-0071]),
wherein the multi-dipole gate structure (216′, 220, 220′, 280, and 282) includes a high-k dielectric (282), a first dipole material (216′) having a first material composition, and a second dipole material (220 and 220′) having a second material composition, wherein the first material composition is different from the second material composition, and wherein one of the first dipole material and the second dipole material is a P-shifter dipole material (216′) and another one of the first dipole material and the second dipole material is an N-shifter dipole material (220 and 220′) ([0063-0071]).
Thus, Hsu ‘472 is shown to teach all the features of the claim with the exception of wherein the first dipole material and the second dipole material are diffused in the high-k dielectric.
However, Pao ‘439 teaches (FIGs. 1-15) first (224) and second (230) dipole materials diffused in a high-k dielectric (222) ([0028, 0030, 0032, 0034]) to provide transistors with different threshold voltages ([0015-0016]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dipole material and the second dipole material of Hsu ‘472 diffused in the high-k dielectric as taught by Pao ‘439 to provide transistors with different threshold voltages.
With respect to claim 2, Hsu ‘472 teaches wherein the P-shifter dipole material (216′) includes one or more of aluminum, vanadium, niobium, titanium, boron, gallium, molybdenum, chromium, cobalt, tantalum, or tungsten ([0071]).
With respect to claim 3, Hsu ‘472 teaches wherein the P-shifter dipole material (216′) includes one or more of aluminum, niobium, or vanadium ([0071]).
With respect to claim 4, Hsu ‘472 teaches wherein the N-shifter dipole material (220 and 220′) includes one or more of lanthanum, molybdenum, strontium, scandium, magnesium, manganese, barium, cerium, erbium, dysprosium, europium, gadolinium, holmium, yttrium, lutetium, neodymium, samarium, or terbium ([0066]).
With respect to claim 5, Hsu ‘472 teaches wherein the N-shifter dipole material (220 and 220′) includes one or more of lanthanum, scandium, or yttrium ([0066]).
With respect to claim 8, Hsu ‘472 teaches wherein a concentration of the first dipole material (216′) in the multi-dipole gate structure (216′, 220, 220′, 280, and 282) decreases closer to the channel material (215) ([0063-0071]).
With respect to claim 9, Hsu ‘472 teaches wherein: the multi-dipole gate structure (216′, 220, 220′, 280, and 282) further includes an interface layer (280), the interface layer is between the channel material (215) and the high-k dielectric, the high-k dielectric is between the interface layer and the gate electrode material (350), and a concentration of atoms of the first dipole material (216′) is highest at an interface between the interface layer and the high-k dielectric, and gradually decreases away from the interface (see examples in FIGs. 15-17 and 26) ([0063-0071]).
With respect to claim 10, Hsu ‘472 and Pao ‘439 teach the device as described in claim 9 above, but primary reference Hsu ‘472 does not explicitly teach the additional limitation wherein a concentration of atoms of the second dipole material is highest at an interface between the interface layer and the high-k dielectric and gradually decreases away from the interface.
However, Pao ‘439 teaches (FIGs. 1-15) first (224) and second (230) dipole materials diffused in a high-k dielectric (222) ([0028, 0030, 0032, 0034]) to provide transistors with different threshold voltages ([0015-0016]). When applied to the device of Hsu ‘472, this would result in a concentration of atoms of the second dipole material being highest at an interface between the interface layer (280 of Hsu ‘472) and the high-k dielectric (282 of Hsu ‘472) and gradually decreasing away from the interface (see examples in FIGs. 15-17 and 26 of Hsu ‘472).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a concentration of atoms of the second dipole material of Hsu ‘472 and Pao ‘439 highest at an interface between the interface layer and the high-k dielectric and gradually decreases away from the interface as taught by Pao ‘439 to provide transistors with different threshold voltages.
With respect to claim 11, Hsu ‘472 teaches (FIGs. 27-36) an integrated circuit (IC) structure substantially as claimed, comprising:
a substrate (202) ([0063-0071]); and
a stack of nanoribbons (215) of one or more semiconductor materials over the substrate (202) ([0063-0071]),
wherein a portion of at least one of the nanoribbons (215) of the stack is a channel region (215) of a transistor (200B) ([0063-0071]), the transistor comprising a transistor gate stack (216′, 220′, 280, 282, and 350) that includes:
a gate electrode material (350) ([0063-0071]),
an interface layer (280) in contact with the channel region (215) ([0063-0071]),
a high-k dielectric (282) between the interface layer (280) and the gate electrode material (350) ([0063-0071]),
atoms of a first dipole material (216′) ([0063-0071]), and
atoms of a second dipole material (220′), different from the first dipole material (216′) ([0063-0071]).
Thus, Hsu ‘472 is shown to teach all the features of the claim with the exception of wherein atoms of the second dipole material are intermixed with atoms of the first dipole material.
However, Pao ‘439 teaches (FIGs. 1-15) first (224) and second (230) dipole materials intermixed together in a high-k dielectric (222) ([0028, 0030, 0032, 0034]) to provide transistors with different threshold voltages ([0015-0016]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed atoms of the second dipole material of Hsu ‘472 intermixed with atoms of the first dipole material as taught by Pao ‘439 to provide transistors with different threshold voltages.
With respect to claim 12, Hsu ‘472 teaches wherein a concentration of the atoms of the first dipole material (216′) is highest at an interface between the interface layer (280) and the high-k dielectric (282) and gradually decreases away from the interface (see examples in FIGs. 15-17 and 26) ([0063-0071]).
With respect to claim 13, Hsu ‘472 and Pao ‘439 teach the device as described in claim 11 above, but primary reference Hsu ‘472 does not explicitly teach the additional limitation wherein a concentration of the atoms of the second dipole material is highest at an interface between the interface layer and the high-k dielectric and gradually decreases away from the interface.
However, Pao ‘439 teaches (FIGs. 1-15) first (224) and second (230) dipole materials diffused in a high-k dielectric (222) ([0028, 0030, 0032, 0034]) to provide transistors with different threshold voltages ([0015-0016]). When applied to the device of Hsu ‘472, this would result in a concentration of the atoms of the second dipole material being highest at an interface between the interface layer (280 of Hsu ‘472) and the high-k dielectric (282 of Hsu ‘472) and gradually decreasing away from the interface (see examples in FIGs. 15-17 and 26 of Hsu ‘472).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a concentration of the atoms of the second dipole material of Hsu ‘472 and Pao ‘439 highest at an interface between the interface layer and the high-k dielectric and gradually decreases away from the interface as taught by Pao ‘439 to provide transistors with different threshold voltages.
With respect to claim 14, Hsu ‘472 teaches wherein the first dipole material (216′) is aluminum, niobium, or vanadium ([0071]).
With respect to claim 15, Hsu ‘472 teaches wherein the second dipole material (220′) is lanthanum, scandium, or yttrium ([0066]).
With respect to claim 16, Hsu ‘472 teaches wherein the transistor gate stack (216′, 220′, 280, 282, and 350) wraps around the channel region (215) ([0063-0071]).
With respect to claim 17, Hsu ‘472 teaches wherein: the transistor is a first transistor (200B), and a portion of at least one of the nanoribbons (215) of the stack is a channel region (215) of a second transistor (200A), the second transistor comprising a transistor gate stack that excludes the atoms of the first dipole material, the atoms of the second dipole material, or both the atoms of the first dipole material and the atoms of the second dipole material ([0063-0071]).
With respect to claim 22, Hsu ‘472 teaches (FIGs. 27-36) an integrated circuit (IC) structure substantially as claimed, comprising:
a stack of nanoribbons (215) of one or more semiconductor materials ([0063-0071]), wherein:
a portion of at least one of the nanoribbons (215) of the stack is a channel region (215) of a transistor (200B) ([0063-0071]),
the transistor (200B) includes a gate stack (216′, 220′, 280, 282, and 350) comprising a gate electrode material (350), an interface layer (280), and a high-k dielectric (282) ([0063-0071]),
the interface layer (280) is between the channel region (215) and the high-k dielectric (282) ([0063-0071]),
the high-k dielectric (282) is between the interface layer (280) and the gate electrode material (350) ([0063-0071]), and
atoms of a second dipole material (220’) are different from atoms of a first dipole material (216’) ([0063-0071]).
Thus, Hsu ‘472 is shown to teach all the features of the claim with the exception of the high-k dielectric includes atoms of a first dipole material and atoms of a second dipole material.
However, Pao ‘439 teaches (FIGs. 1-15) a high-k dielectric (222) including atoms of first (224) and second (230) dipole materials ([0028, 0030, 0032, 0034]) to provide transistors with different threshold voltages ([0015-0016]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the high-k dielectric of Hsu ‘472 including atoms of a first dipole material and atoms of a second dipole material as taught by Pao ‘439 to provide transistors with different threshold voltages.
With respect to claim 24, Hsu ‘472 teaches wherein a concentration of the atoms of the first dipole material (216’) is highest at an interface between the interface layer (280) and the high-k dielectric (282) and gradually decreases away from the interface (see examples in FIGs. 15-17 and 26) ([0063-0071]).
With respect to claim 25, Hsu ‘472 and Pao ‘439 teach the device as described in claim 24 above, but primary reference Hsu ‘472 does not explicitly teach the additional limitation wherein a concentration of the atoms of the second dipole material is highest at the interface and decreases away from the interface.
However, Pao ‘439 teaches (FIGs. 1-15) first (224) and second (230) dipole materials diffused in a high-k dielectric (222) ([0028, 0030, 0032, 0034]) to provide transistors with different threshold voltages ([0015-0016]). When applied to the device of Hsu ‘472, this would result in a concentration of the atoms of the second dipole material being highest at an interface between the interface layer (280 of Hsu ‘472) and the high-k dielectric (282 of Hsu ‘472) and gradually decreasing away from the interface (see examples in FIGs. 15-17 and 26 of Hsu ‘472).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a concentration of the atoms of the second dipole material of Hsu ‘472 and Pao ‘439 highest at the interface and decreases away from the interface as taught by Pao ‘439 to provide transistors with different threshold voltages.
Claims 21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘472 and Pao ‘439 as applied to claims 9 and 22 above, and further in view of Bao et al. (US Patent Application Publication 2023/0261074, hereinafter Bao ‘074).
With respect to claims 21 and 23, Hsu ‘472 and Pao ‘439 teach the device as described in claims 9 and 22 above with the exception of the additional limitations wherein the first dipole material and the second dipole material are further in the interface layer; and wherein the interface layer includes the atoms of the first dipole material and the atoms of the second dipole material.
However, Bao ‘074 teaches (FIGs. 11 and 12) first (130) and second (145) dipole materials diffused into an interface layer (120) ([0045-0046]) to adjust the voltage of nanosheet devices without infringing on the small amount of space separating each of the nanosheets ([0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dipole material and the second dipole material of Hsu ‘472 and Pao ‘439 further in the interface layer as taught by Bao ‘074; and to have formed the interface layer of Hsu ‘472 and Pao ‘439 including the atoms of the first dipole material and the atoms of the second dipole material as taught by Bao ‘074 to adjust the voltage of nanosheet devices without infringing on the small amount of space separating each of the nanosheets.
Response to Arguments
Applicant’s amendments to claim 4 are sufficient to overcome the 35 U.S.C. 112(b) rejection of claim 4 made in the non-final rejection filed 8 April 2026. The 35 U.S.C. 112(b) rejection of claim 4 has been withdrawn.
Applicant's arguments filed 30 June 2026 with respect to the 35 U.S.C. 102(a)(1) rejection of claims 1, 6, and 11, and the 35 U.S.C. 103 rejection of claim 7 have been fully considered but they are not persuasive.
Applicant argues (remarks, p. 7) that Hsu ‘472 repeatedly uses patterning and selective masking steps to ensure that dipole materials are incorporated only in intended regions and layers. This results in a layer-specific and segregated distribution of dipole materials: n-dipole materials (220’) are incorporated in the interfacial layer (280) and p-dipole materials (216’) are incorporated in the high-k dielectric layer (282). Furthermore, Hsu ‘472 teaches that only the p-dipole material (216’) is diffused into the high-k dielectric layer (282). Thus, the structural arrangement in Hsu ‘472 (dipoles segregated into different layers) is not incidental; rather, it is an inevitable consequence of the fabrication paradigm of Hsu ‘472 based on sequential deposition, masking, and selective drive-in processes. In contrast, amended claim 1 recites that both the first dipole material and the second dipole material are diffused in the high-k dielectric material. This recitation necessarily reflects a different fabrication strategy, namely one in which both dipole species are introduced such that they co-exist within the same high-k dielectric layer, rather than being confined to different layers. Hsu ‘472 does not teach or suggest modifying its process flow such that both dipole materials would be driven into the same high-k dielectric layer, or the interfacial-layer-specific dipole would be relocated into the high-k dielectric. To the contrary, the teaching of Hsu ‘472 is directionally opposite: it deliberately allocates different dipole materials to different layers (interfacial vs. high-k), using masking and selective deposition to maintain that separation. Accordingly, achieving the claimed structure of amended claim 1 starting from the disclosure of Hsu ‘472 would require discarding the layer-specific dipole placement strategy of Hsu ‘472, and redesigning the fabrication process to enable co-diffusion of multiple dipole species into the high-k dielectric. Such modifications are not suggested by Hsu ‘472 and would alter its fundamental operating principle. Examiner respectfully disagrees.
Hsu ‘472 is not cited to address the limitation, “wherein the first dipole material and the second dipole material are diffused in the high-k dielectric.” Rather, Pao ‘439 teaches the aforementioned limitation as set forth in the 35 U.S.C. 103 rejection of claim 1 above. Pao ‘439 teaches (FIGs. 1-15) first (224) and second (230) dipole materials diffused in a high-k dielectric (222) ([0028, 0030, 0032, 0034]) to provide transistors with different threshold voltages ([0015-0016]). More specifically, Pao ‘439 discloses, e.g., “[T]he anneal process (300) includes a high anneal temperature between about 500° C. and about 900° C. so as to allow lanthanum, yttrium, or aluminum in the first dipole layer (224) and/or the second dipole layer (230) to diffuse into the gate dielectric layer (222),” at paragraph [0034].
In light of the teachings of Pao ‘439, one of ordinary skill in the art could modify the layer arrangement of Hsu ‘472 such that the first dipole material (216’) and the second dipole material (220 and 220’) are diffused in the high-k dielectric (282) to provide transistors having different threshold voltages with a reasonable expectation of success.
Further, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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