DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendments, filed on 04/02/2026, have been received and made of record. In response to the most recent Office Action, dated 12/02/2025, claims 1, 7, 8, 12, 14, 19 and 22 have been amended.
Claims 1-3, 5-19 and 22 are currently pending.
Response to Arguments
Applicant’s amendments, filed on 04/02/2026, have been entered and fully considered. In light of the amendments, the Applicant has presented the argument that the new limitations of claims 1 and 22 are not taught by the reference Nogawa (US 2019/0165676 A1). The argument submitted by the Applicant has been reproduced below and can be found on page 8 of the submitted remarks:
As amended, claim 1 recites, in part, "a second amplifier having first and second inputs and an output, the first input of the second amplifier coupled to the output of the first amplifier, the second input of second amplifier coupled to the switching terminal and coupled to the power converter output through a first path and a second path." The references cited in the Office Action are not alleged to, and indeed do not, teach or suggest these features of claim 1. For at least this reason, claim 1 is patentable over the references cited in the Office Action.
As amended, claim 14 recites, in part, "generating a slope signal responsive to receiving a second voltage at a switching terminal of the power converter, and receiving the first voltage through at least one of two paths to the output of the power converter." The references cited in the Office Action are not alleged to, and indeed do not, teach or suggest these features of claim 14. For at least this reason, claim 14 is patentable over the references cited in the Office Action.
As amended, claim 22 recites, in part, "a second amplifier having first and second inputs and an output, the first input of the second amplifier coupled to the output of the first amplifier, the second input of second amplifier coupled to the switching terminal and coupled to the power converter output through a first path and a second path." The references cited in the Office Action are not alleged to, and indeed do not, teach or suggest these features of claim 22. For at least this reason, claim 22 is patentable over the references cited in the Office Action.
The Examiner respectfully disagrees and would like to start off by reminding applicant that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Nogawa teaches a circuit (Figure 13) that comprises the second amplifier (Figure 13 Component 36) that has a first input (Figure 13 Component 39) and a second input (Figure 13 Component 37). The second input is coupled to the switching terminal and the output through a current sense circuit (Figure 13 Component 19). The current sense circuit is shown in further detail in Figures 7-9, however, for citation purposes Figure 7 has been chosen as the embodiment teaching Component 19 from Figure 13. Figure 7 shows that the input of the second amplifier is Vcurrent and it comes from two paths. The first one being from the right terminal of the inductor (Figure 7 Component 3) and the capacitor (Figure 7 Component 4). The second path being from the left terminal of the inductor (Figure 7 Component 3). For illustrative purposes the Examiner has annotated Figure 7 as Annotated Figure 7A (See Below) to provide a clearer analysis of what the Examiner wants to point out. Annotated Figure 7A Component SP shows the second path and Component FP shows the first path. Both of these paths connect Vcurrent which is the input value to the second input of the second amplifier to the switching terminal and the power converter output. Therefore, this interpretation teaches the newly recited limitations of claims 1 and 22.
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Applicant’s arguments, see page 8 (See Above as well), filed 04/02/2026, with respect to claim 14 has been fully considered and are persuasive. The 35 U.S.C. 102(a)(1) and 102(a)(2) rejection of claim 14 has been withdrawn.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 7 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Nogawa (US 2019/0165676 A1).
Regarding claim 1, Nogawa teaches a circuit (Figure 13) comprising: a power stage (Figure 13 Components 21+22+3) having a power terminal (Figure 13 Component Vin), a switching terminal (Figure 13 Component 38 which is a node for the switching terminal SW), and control inputs (Figure 13 Component 21 and 22 control terminals that receive the control signal from Component 18; These inputs would be received at the control terminals of Components 21 and 22 as Paragraph 0031 highlights that these switches are transistors); a first amplifier having first and second inputs and an output (Figure 13 Component 23), the first input of the first amplifier coupled to a reference terminal (Figure 13 Component 26 receives the voltage reference Vref from Component 24), the second input of the first amplifier coupled to a power converter output (Figure 13 Component 27 receives a feedback voltage FB from the power converter output shows at Component 28); a second amplifier having first and second inputs and an output (Figure 13 Component 36; A comparator is a special type of amplifier therefore still reads on the limitation of being an amplifier; Also the immediate disclosure shows that the second amplifier being claimed is indeed a comparator), the first input of the second amplifier coupled to the output of the first amplifier (Figure 13 Component 39 is coupled to the output of Component 23), the second input of second amplifier coupled to the switching terminal and coupled to the power converter output through a first path and a second path (Figure 13 Component 37 is coupled to the switching terminal and the power converter output through Component 19 which is seen in further detail in Figure 7; Figure 7 has been annotated below as Annotated Figure 7A to show the first and second paths; Annotated Figure 7A Component FP is the first path and Component SP is the second path); and control circuitry coupled between the output of the second amplifier and the control inputs of the power stage (Figure 13 Component 18).
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Regarding claim 2, Nogawa teaches all the limitations of claim 1. Nogawa further teaches a filter coupled between the switching terminal and the power converter output (Figure 13 Components 3 and 4; The filter is coupled between the output and the switching terminal because of the configuration of Component 3 being between Components 38 and 28 furthermore claim 3 which further defines it makes this interpretation valid).
Regarding claim 3, Nogawa teaches all the limitations of claim 2. Nogawa further teaches wherein the filter further comprises: an inductor coupled between the switching terminal and the power converter output (Figure 13 Component 3); and a capacitor coupled between the power converter output and a ground terminal (Figure 13 Component 4).
Regarding claim 7, Nogawa teaches all the limitations of claim 1. Nogawa further teaches a resistor coupled between the switching terminal and the second input of the second amplifier (Figure 13 Component 19 is shown in detail in Figures 7-9; Figure 7 shows that a resistor is present between Component SW and the output terminal outputting Vcurrent that goes to the second input terminal of Component 36), and a capacitor coupled between the second input of the second amplifier and the power converter output on the first path (Figure 7 also shows a capacitor coupled between the output terminal which is the right side terminal of Component 3 and the second input terminal of Component 36; Annotated Figure 7A Component FP shows that the capacitor is on the first path).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Nogawa (US 2019/0165676 A1) in view of Yaginuma (US 2022/0060107 A1).
Regarding claim 13, Nogawa teaches all the limitations of claim 1. Nogawa does not explicitly teach wherein the control circuitry is configurable to switch a state of the power stage at a constant frequency.
Yaginuma teaches a power converter (Figure 1), comprising: a power stage (Figure 1 Component 3) and a control circuit (Figure 1 Component 7), wherein the control circuit is configuration to switch a state of the power stage at a constant frequency (Paragraph 0050 recites “When the switching cycle is constant, the maximum sampling frequency Nmax is also a constant” which indicates that the power converter is controlled at a constant switching cycle; Constant switching cycles means constant switching frequency because a switching cycle is defined as one complete on+off period of a switch which has duration known as a switching period T and switching frequency is defined as 1/T).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nogawa to incorporate using a constant switching frequency as taught by Yaginuma. The benefit of a constant switching frequency is that it allows for quicker and more stable transient response.
Regarding claim 22, Nogawa teaches a power converter (Figure 13) comprising: a power converter input (Figure 13 Component Vin) and a power converter output (Figure 13 Component Vout/Component 28), the power converter further comprising: a power stage (Figure 13 Components 21+22+3) having a power terminal coupled to the power converter input (Figure 13 Component Vin), a switching terminal (Figure 13 Component 38/SW), and control inputs (Figure 13 Component 21 and 22 control inputs to switch the switches); a first amplifier having first and second inputs and an output (Figure 13 Component 23), the first input of the first amplifier coupled to a reference terminal (Figure 13 Component 23 receives Component Vref at Component 26), the second input of the first amplifier coupled to the power converter output (Figure 13 Component 23 receives Component Vout as a feedback voltage at Component 27); a second amplifier having first and second inputs and an output (Figure 13 Component 36; A comparator is a special type of amplifier therefore still reads on the limitation of being an amplifier; Also the immediate disclosure shows that the second amplifier being claimed is indeed a comparator), the first input of the second amplifier coupled to the output of the first amplifier (Figure 13 Component 39 is coupled to the output of Component 23), the second input of second amplifier coupled to the switching terminal and coupled to the power converter output through a first path and a second path (Figure 13 Component 37 is coupled to the switching terminal and the power converter output through Component 19 which is seen in further detail in Figure 7; Figure 7 has been annotated below as Annotated Figure 7A to show the first and second paths; Annotated Figure 7A Component FP is the first path and Component SP is the second path); and control circuitry coupled between the output of the second amplifier and the control inputs of the power stage (Figure 13 Component 18).
Nogawa does not teach a computing device comprising: a processing unit; a memory module coupled to the processing unit; and a power converter coupled to the processing unit and the memory module.
Yaginuma teaches a computing device (Figure 1), comprising: a processing unit (Figure 1 Component 23); a memory module coupled to the processing unit (Figure 1 Component 22); and a power converter coupled to the processing unit and the memory module (Figure 1 Component 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nogawa and incorporate placing the power converter within a computing processing device as taught by Yaginuma. The advantage of this design is that the power converter can be used to provide an efficient amount of power variably based on load demand.
Allowable Subject Matter
Claims 5-6 and 8-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests a clocking circuit that includes a sequential logic circuit coupled to the clock input and the output of the clocking circuit, the sequential logic circuit having a clear input; and a gating circuit having inputs and an output, the inputs of the gating circuit coupled to one of the outputs of the logic circuit and the output of the clocking circuit, and the output of the gating circuit coupled to the clear input of the sequential logic circuit. Claim 6 is dependent upon claim 5.
Regarding claim 8, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests a second capacitor and a second resistor coupled between the second input of the second amplifier and the power converter output; a switch coupled between a terminal of the second capacitor and a ground terminal or the power terminal; and second control circuitry having inputs and an output, the inputs of the second control circuitry coupled to a clock source and to one of the control inputs of the power stage, and the output of the second control circuitry coupled to a control terminal of the switch. Claims 9-12 depend upon claim 8.
Claims 14-19 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 14, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests generating a slope signal responsive to receiving a second voltage at a switching terminal of the power converters and receiving the first voltage through at least one of two paths to the output of the power converter. Claims 15-19 are dependent upon claim 14 and are therefore also allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sohma (US 2010/0181977 A1) teaches a switching regulator includes: a switching element switching in accordance with an input control signal; an inductor charged with a supply voltage by the switching of the switching element; a rectifying element discharging the inductor when the switching element is switched off and charging of the inductor is stopped; and a control circuit unit generating an error voltage based on a voltage difference between a proportional voltage and a predetermined reference voltage, generating and outputting a pulse signal with a duty cycle in accordance with the error voltage to a control electrode of the switching element. The control circuit unit generates a feedback voltage from the duty cycle of the pulse signal, generates the pulse signal with the duty cycle from a voltage difference between the generated feedback voltage and the error voltage, and varies the voltage difference from the duty cycle of the pulse signal. Sohma specifically teaches wherein the feedback voltage can go through a resistive divider and/or a capacitor for proper compensation.
Huang (US 9755519 B1) teaches a switching power converter with good stability and transient response is presented. There is provided a controller for a switching power converter of the type comprising one or more power switches. The controller contains a pulse width modulation comparator arranged to output a digital control signal to control the power switches of the switching power converter. A first input of the pulse width modulation comparator is derived from an output voltage of the switching power converter via a first feedback path. A second input of the pulse width modulation comparator is derived from the output voltage of the switching power converter via a second feedback path. One of the feedback paths has a signal extractor and a differential amplifier arranged to filter the output voltage and to provide good ground noise rejection.
Fukushima (US 2015/0326123 A1) teaches a control circuit of a DC/DC converter is disclosed. The control circuit includes a pulse modulator generating a comparison pulse, which is transitioned to an on level when a feedback voltage depending on an output voltage of the converter is lowered to a threshold voltage and then transitioned to an off level; a peak current detector asserting a detection signal when a coil current of the converter reaches a predetermined peak current; a logic part generating a control pulse which is transitioned to an on level when the comparison pulse is transitioned to the on level, and is transitioned to an off level at a time which is later among the time when the comparison pulse is transitioned to the off level and the time when the peak current detection signal is asserted; and a driver switching a switching transistor of the converter based on the control pulse.
Xue (US 2015/0263617 A1) teaches a buck switching regulator includes a feedback control circuit using a four-input comparator to regulate the output voltage to a substantially constant level with reduced voltage offset and with fast transient response. In some embodiments, the buck switching regulator uses the four-input comparator to compare a first feedback signal without ripple and a second feedback signal with injected ripple components to a reference level. The four-input comparator generates an output signal to control the switching of the power switches. The buck switching regulator generates an output voltage with increased accuracy and fast transient response. Furthermore, the buck switching regulator can be used with output capacitor having any value of ESR.
Yan (US 2014/0292300 A1) teaches a switching power converter having an output capacitor having a small equivalent series resistance (ESR) which is stabilized and jitter is reduced by sensing capacitor current with gain and combining the resulting signal with the output voltage signal to provide a feedback signal to control switching of the power converter. capacitor current can be sensed without interfering with operation of the filter capacitor by providing a branch circuit having a time constant matched to the output or filter capacitor but an arbitrarily high impedance so as to be effectively lossless. The gain provided in the capacitor current signal can be tuned to provide optimally short settling time after load transients within one switching cycle. Matching of time constants and/or tuning of gain can be performed automatically.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Shahzeb K Ahmad/Examiner, Art Unit 2838
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