DETAILED ACTION
This Office Action is in response to claims filed on 07/06/2026.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 8, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Maharana et al. Pub. No. US 2021/0311664 A1 (hereinafter Maharana) in view of Ahmad et al. Patent No. US 11,063,594 B1 (hereinafter Ahmad).
With regard to claim 1, Maharana teaches a method comprising ([0039], FIG. 6 is a flow diagram of an example method of NVMe direct virtualization in a memory sub-system in accordance with some embodiments of the present disclosure):
exposing a physical function of a hardware device on a bus, the physical function corresponding to a physical partition of multiple physical partitions of the hardware device ([0022], In one embodiment, the NVMe virtualization module 113 executes firmware or other logic to provide a number of virtual NVMe controllers in memory sub-system 110. NVMe virtualization module 113 associates each virtual NVME controller with a certain portion of the underlying memory components 112A to 112N, where each portion is addressable by a unique namespace. NVMe virtualization module 113 further assigns a corresponding PCIe physical function to each virtual NVMe controller, causing each virtual NVMe controller to appear as a separately addressable PCIe device (i.e., a physical controller) connected to the PCIe bus between the memory sub-system 110 and the host system 120. Host system 120, including separate virtual machines or partitions running thereon, can thus access each portion of the memory components 112A to 112N represented by a virtual NVMe controller separately and in parallel over the physical host interface (e.g., PCIe bus); [0025] As described above, NVMe virtualization module 113 associates one of physical functions 212-218 with each of virtual NVMe controllers 202-208 in order to allow each virtual NVMe controller 202-208 to appear as a physical controller on PCIe bus 210) …;
receiving, via the physical function, a request to perform one or more operations ([0024], Each of virtual NVMe controllers 202-208 manages storage access operations for the corresponding portion of the underlying memory components 112A to 112N, with which it is associated. For example, virtual NVMe controller 202 may receive data access requests from host system 120 over PCIe bus 210, including requests to read, write, or erase data in a first portion of memory component 112A. In response to the request, virtual NVMe controller 202 may perform the requested memory access operation on the data stored at an identified address in the first portion and return requested data and/or a confirmation or error message to the host system 120, as appropriate; [0026], As noted above, each physical function 212-218 (Examiner notes: each corresponding to a NVMe controller) can be assigned to any one of virtual machines 232-236 in the host system 120. When I/O data is received at a virtual NVMe controller 202-208 from a virtual machine 232-236 a virtual machine driver provides a guest physical address for a corresponding read/write command); and
performing the one or more operations on the physical partition ([0026], NVMe virtualization module 113 translates the physical function number to a bus, device, and function (BDF) number and then adds the command to a direct memory access (DMA) operation to perform the DMA operation on the guest physical address).
Maharana reasonably teaches physical function configuration spaces (Maharana, [0035]) and partitioning of memory into respective portions (Maharana, Abstract). However, Maharana does not explicitly teach that a physical partition supports a full configuration space including one or more compute resources, one or more memory resources, and one or more registers.
Ahmad teaches wherein the physical partition (Col. 43, lines 1-10, The SoC 100 may be coupled to a circuit board or card that is connected to the host data processing system 2802 by way of the PCIe link … The shell design, as implemented within the SoC 100, creates a plurality of partitions within the SoC 100. The term “partition” as used herein in connection with SoC 100, refers to a collection or set of SoC 100 resources that are allocated or reserved for use by any application that is implemented within that partition.) supports a full configuration space including one or more compute resources, one or more memory resources and one or more registers (Col. 27-Col. 28, lines 63-67 and lines 1-3, While SoC 100 has been largely described according to the different subsystems contained therein, e.g., Pl 104, PS 106, DPE array 102, NoC 108, and/or hardwired circuit blocks, the platform also provides resources in the form of “compute engines”, “hardware accelerator engines”, “memory resources”, “external interfaces”, and “pervasive interconnects” that extend across the different subsystems described; Col. 46, lines 34-43, As implemented, each application is only aware of the resources of the SoC 100 that are allocated to the partition in which that application is implemented … the PMC 1602 is configured to only allow each user to access the configuration space corresponding to that user’s partition. In other words, the PMC 1602 only allows user X to access the configuration space (e.g., configuration registers) for SoC 100 resources allocated to partition X (whether for a particular subset of the PL, a particular subset of the DPE array, and/or particular elements in the PS).)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Ahmad with the teachings of Maharana in order to provide a method that teaches a physical partitioning supporting a full configuration space including computing, memory, and register resources. The motivation for applying Ahmad teaching with Maharana teaching is to provide a method that allows for the physical partition to support a configuration space of resources for consumption by user processes, as combining the known memory resource partitioning system of Maharana with the configuration space resource allocation technique of Ahmad constitutes the application of a known technique to a known system in order to yield predictable results. Maharana and Ahmad are analogous art directed towards the logical partitioning and management of resources. Therefore, it would have been obvious for one of ordinary skill in the art to combine Ahmad with Maharana to teach the claimed invention in order to provide a method of providing full configuration space resource allocation to isolated partitions, thereby improving the utilization of resources of a system with respect to associated partitioned processes.
With regard to claim 2, Maharana teaches the method of claim 1, wherein the bus comprises a peripheral component interconnect express bus (FIG. 2, PCIe Bus 210; [0023], FIG. 2 illustrates an example physical host interface between a host system and a memory sub-system implementing NVMe direct virtualization in accordance with some embodiments of the present disclosure. In one embodiment, the controller 115 of memory sub-system 110 is connected to host system 120 over a physical host interface, such as PCIe bus 210).
With regard to claim 3, Maharana teaches the method of claim 1, further comprising:
exposing an additional physical function of the hardware device on the bus, the additional physical function corresponding to a device management module of the hardware device ([0027], Further, each physical function 212-218 may be implemented in either a privileged mode or normal mode … Typically a first physical function can implement a privileged mode and the remainder of the physical functions can implement a normal mode) that manages the multiple physical partitions of the hardware device ([0027], When Implemented in the privileged mode, the physical function has a single point of management that can control resource manipulation and storage provisioning for other functions implemented in the normal mode. In addition, a physical function in the privileged mode can perform management options, including for example, enabling/disabling of multiple physical functions, storage and quality of service provisioning (QoS), firmware and controller updates, vendor unique statistics and events, diagnostics, secure erase/encryption, among others).
With regard to claim 4, Maharana teaches the method of claim 3, further comprising:
receiving configuration information corresponding to software, the configuration information indicating resources requested for execution of the software ([0030], The associated virtual NVMe controller 202-208 may appear as a virtual storage resource to each of virtual machines 232, 234, 236 which the guest operating system or guest applications running therein can access; [0037], In one embodiment, controller 115 further includes quality of service (QoS) module 522 and sideband management (SM) bus 524. QoS can implement individual quality of service management for each virtual NVMe controller 202-208. When a large storage device, such as one of memory components 112A to 112N is sliced into smaller partitions, each controlled by a virtual NVMe controller 202-208, and that each can be used by different clients (e.g., virtual machines on host system 120), it may be beneficial to associate QoS characteristics with each individual partition (Examiner notes: A quality of service is associated with a plurality of sets of requirements and limitations governing an application’s access to system resources, enforced through controls such as time limits and predefined configuration of resource allocations). To meet these requirements, QoS module 522 attaches QoS controls (Examiner notes: QoS controls receives service specification and allocates system resources to ensure software is executed with its defined service level) to each virtual NVMe controller 202-208); and
configuring, based on the received configuration information, the physical partition including the indicated resources ([0037], The QoS controls may include, for example, an individual storage partition size, bandwidth, or other characteristics. QoS module 522 may monitor the performance of virtual NVMe controllers 202-208 over time and reconfigure resource assignments as needed to ensure compliance with QoS requirements).
With regard to claim 5, Maharana teaches the method of claim 4, the software comprising a software container, an application, or a software stack ([0028], Host system 120 runs multiple virtual machines 232, 234, 236, by executing a software layer 224, often referred to as “hypervisor,” above the hardware and below the virtual machines, as schematically shown in FIG. 2 … One or more applications may be running on each virtual machine under the guest operating system).
With regard to claim 6, Maharana teaches the method of claim 1, further comprising:
exposing a … physical function of the hardware device on the bus, the … physical function corresponding to a … physical partition of the multiple physical partitions ([0022], In one embodiment, the NVMe virtualization module 113 executes firmware or other logic to provide a number of virtual NVMe controllers in memory sub-system 110. NVMe virtualization module 113 associates each virtual NVME controller with a certain portion of the underlying memory components 112A to 112N, where each portion is addressable by a unique namespace. NVMe virtualization module 113 further assigns a corresponding PCIe physical function to each virtual NVMe controller, causing each virtual NVMe controller to appear as a separately addressable PCIe device (i.e., a physical controller) connected to the PCIe bus between the memory sub-system 110 and the host system 120. Host system 120, including separate virtual machines or partitions running thereon, can thus access each portion of the memory components 112A to 112N represented by a virtual NVMe controller separately and in parallel over the physical host interface (e.g., PCIe bus); [0025] As described above, NVMe virtualization module 113 associates one of physical functions 212-218 with each of virtual NVMe controllers 202-208 in order to allow each virtual NVMe controller 202-208 to appear as a physical controller on PCIe bus 210);
receiving, via the … physical function, a request to perform at least one operation ([0026], As noted above, each physical function 212-218 can be assigned to any one of virtual machines 232-236 in the host system 120. When I/O data is received at a virtual NVMe controller 202-208 from a virtual machine 232-236 a virtual machine driver provides a guest physical address for a corresponding read/write command); and
performing the at least one operation on the … physical partition ([0026], NVMe virtualization module 113 translates the physical function number to a bus, device, and function (BDF) number and then adds the command to a direct memory access (DMA) operation to perform the DMA operation on the guest physical address).
However, Maharana does not explicitly teach the limitation of additional physical functions and additional physical partitions.
In other embodiments, Maharana teaches additional physical functions … additional physical partitions ([0023], In other embodiments, however, there may be any other number (additional) of NVMe controllers, each having a corresponding physical function; [0058], In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in illustrative sense rather than a restrictive sense)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the embodiments disclosed by Maharana in order to provide a method that teaches an additional plurality of physical functions corresponding to additional physical partitions receiving and performing requests. The motivation for combining the embodiments disclosed by Maharana is to provide a method that allows for a desired number of physical functions to be provisioned (Maharana, [0035]), enabling greater granularity over partitioning computing resources to meet quality of service requirements (Maharana, [0037]). Maharana is art directed towards device partitioning and inter-process communication. Therefore, it would have been obvious for one of ordinary skill in the art to combine the embodiments of Maharana to teach the claimed invention in order to provide a method that can be performed across additional physical functions corresponding to physical partitions, thereby allowing a desired number of partitions to be provisioned to enable greater resource control.
With regard to claim 8, Maharana teaches a system comprising ([0016], FIG. 1 illustrates an example computing environment 100 that includes a memory sub-system 110 in accordance with some embodiments of the present disclosure):
a bus, the bus configured to expose a physical function ([0022], In one embodiment, the NVMe virtualization module 113 executes firmware or other logic to provide a number of virtual NVMe controllers in memory sub-system 110. NVMe virtualization module 113 associates each virtual NVME controller with a certain portion of the underlying memory components 112A to 112N, where each portion is addressable by a unique namespace. NVMe virtualization module 113 further assigns a corresponding PCIe physical function to each virtual NVMe controller, causing each virtual NVMe controller to appear as a separately addressable PCIe device (i.e., a physical controller) connected to the PCIe bus between the memory sub-system 110 and the host system 120. Host system 120, including separate virtual machines or partitions running thereon, can thus access each portion of the memory components 112A to 112N represented by a virtual NVMe controller separately and in parallel over the physical host interface (e.g., PCIe bus); [0025] As described above, NVMe virtualization module 113 associates one of physical functions 212-218 with each of virtual NVMe controllers 202-208 in order to allow each virtual NVMe controller 202-208 to appear as a physical controller on PCIe bus 210) and the bus configured to receive a request to perform one or more operations ([0024], Each of virtual NVMe controllers 202-208 manages storage access operations for the corresponding portion of the underlying memory components 112A to 112N, with which it is associated. For example, virtual NVMe controller 202 may receive data access requests from host system 120 over PCIe bus 210, including requests to read, write, or erase data in a first portion of memory component 112A. In response to the request, virtual NVMe controller 202 may perform the requested memory access operation on the data stored at an identified address in the first portion and return requested data and/or a confirmation or error message to the host system 120, as appropriate; [0026], As noted above, each physical function 212-218 (Examiner notes: each corresponding to a NVMe controller) can be assigned to any one of virtual machines 232-236 in the host system 120. When I/O data is received at a virtual NVMe controller 202-208 from a virtual machine 232-236 a virtual machine driver provides a guest physical address for a corresponding read/write command); and
a hardware device, the hardware device including multiple physical ([0023], The virtual NVMe controllers 202-208 are virtual entities that appear as physical controllers to other devices, such as host system 120, connected to PCIe bus by virtue of a physical function 212-218 associated with each virtual NVMe controller 202-208), …, wherein the multiple physical partitions includes a physical partition corresponding to the physical function ([0022], NVMe virtualization module 113 further assigns a corresponding PCIe physical function to each virtual NVMe controller, causing each virtual NVMe controller to appear as a separately addressable PCIe device (i.e., a physical controller) connected to the PCIe bus between the memory subsystem 110 and the host system 120).
Maharana reasonably teaches physical function configuration spaces (Maharana, [0035]) and partitioning of memory into respective portions (Maharana, Abstract). However, Maharana does not explicitly teach that a physical partition supports a full configuration space including one or more compute resources, one or more memory resources, and one or more registers.
Ahmad teaches each of the multiple the physical partition (Col. 43, lines 1-10, The SoC 100 may be coupled to a circuit board or card that is connected to the host data processing system 2802 by way of the PCIe link … The shell design, as implemented within the SoC 100, creates a plurality of partitions within the SoC 100. The term “partition” as used herein in connection with SoC 100, refers to a collection or set of SoC 100 resources that are allocated or reserved for use by any application that is implemented within that partition.) supporting a full configuration space including one or more compute resources, one or more memory resources and one or more registers (Col. 27-Col. 28, lines 63-67 and lines 1-3, While SoC 100 has been largely described according to the different subsystems contained therein, e.g., Pl 104, PS 106, DPE array 102, NoC 108, and/or hardwired circuit blocks, the platform also provides resources in the form of “compute engines”, “hardware accelerator engines”, “memory resources”, “external interfaces”, and “pervasive interconnects” that extend across the different subsystems described; Col. 46, lines 34-43, As implemented, each application is only aware of the resources of the SoC 100 that are allocated to the partition in which that application is implemented … the PMC 1602 is configured to only allow each user to access the configuration space corresponding to that user’s partition. In other words, the PMC 1602 only allows user X to access the configuration space (e.g., configuration registers) for SoC 100 resources allocated to partition X (whether for a particular subset of the PL, a particular subset of the DPE array, and/or particular elements in the PS).) which is substantially similar to claim 1 and therefore rejected with similar rationale.
Examiner notes: It would be obvious to one of ordinary skill in the art to recognize that the system of claim 8 is being substantially recited again for the method of claim 1.
With regard to claim 9, Maharana teaches the system of claim 8, wherein the bus comprises a peripheral component interconnect express bus (FIG. 2, PCIe Bus 210; [0023], FIG. 2 illustrates an example physical host interface between a host system and a memory sub-system implementing NVMe direct virtualization in accordance with some embodiments of the present disclosure. In one embodiment, the controller 115 of memory sub-system 110 is connected to host system 120 over a physical host interface, such as PCIe bus 210).
With regard to claim 10, Maharana teaches the system of claim 8, further comprising:
an additional physical function exposable on the bus ([0027], Further, each physical function 212-218 may be implemented in either a privileged mode or normal mode … Typically a first physical function can implement a privileged mode and the remainder of the physical functions can implement a normal mode); and
a device management module, corresponding to the additional physical function, that manages the multiple physical partitions of the device ([0027], When implemented in the privileged mode, the physical function has a single point of management that can control resource manipulation and storage provisioning for other functions implemented in the normal mode. In addition, a physical function in the privileged mode can perform management options, including for example, enabling/disabling of multiple physical functions, storage and quality of service provisioning (QoS), firmware and controller updates, vendor unique statistics and events, diagnostics, secure erase/encryption, among others).
With regard to claim 11, Maharana teaches the system of claim 10, wherein the device management module is to:
receive, via the bus and the additional physical function, configuration information corresponding to software, the configuration information indicating resources requested for execution of the software ([0030], The associated virtual NVMe controller 202-208 may appear as a virtual storage resource to each of virtual machines 232, 234, 236 which the guest operating system or guest applications running therein can access; [0037], In one embodiment, controller 115 further includes quality of service (QoS) module 522 and sideband management (SM) bus 524. QoS can implement individual quality of service management for each virtual NVMe controller 202-208. When a large storage device, such as one of memory components 112A to 112N is sliced into smaller partitions, each controlled by a virtual NVMe controller 202-208, and that each can be used by different clients (e.g., virtual machines on host system 120), it may be beneficial to associate QoS characteristics with each individual partition (Examiner notes: A quality of service is associated with a minimum set of requirements and limitations governing an application’s access to system resources, enforced through controls such as time limits and predefined resource allocations). To meet these requirements, QoS module 522 attaches QoS controls (Examiner note: QoS controls receives service specification and allocates system resources to ensure software is executed with its defined service level) to each virtual NVMe controller 202-208); and
configure, based on the received configuration information, the physical partition including the indicated resources ([0037], The QoS controls may include, for example, an individual storage partition size, bandwidth, or other characteristics. QoS module 522 may monitor the performance of virtual NVMe controllers 202-208 over time and reconfigure resource assignments as needed to ensure compliance with QoS requirements).
With regard to claim 12, Maharana teaches the system of claim 11, wherein the configuration information is received from a management application that provides and interface to manage resources in the device ([0040], At operation 610, the processing device provides a plurality of virtual memory controllers, such as virtual NVMe controllers 202-208. The virtual NVMe controllers 202-208 are virtual entities that appear as physical controllers to other devices, such as host system 120, connected to PCIe bus 210 by virtue of a physical function 212-218 associated with each virtual NVMe controller 202-208. In one embodiment, the virtual memory controllers are created inside controller 115, but may not be used until they are enabled, such as in response to input received from a system administrator via a management interface).
With regard to claim 13, Maharana teaches the system of claim 8, further comprising:
an … physical function exposable on the bus ([0022], In one embodiment, the NVMe virtualization module 113 executes firmware or other logic to provide a number of virtual NVMe controllers in memory sub-system 110. NVMe virtualization module 113 associates each virtual NVME controller with a certain portion of the underlying memory components 112A to 112N, where each portion is addressable by a unique namespace. NVMe virtualization module 113 further assigns a corresponding PCIe physical function to each virtual NVMe controller, causing each virtual NVMe controller to appear as a separately addressable PCIe device (i.e., a physical controller) connected to the PCIe bus between the memory sub-system 110 and the host system 120. Host system 120, including separate virtual machines or partitions running thereon, can thus access each portion of the memory components 112A to 112N represented by a virtual NVMe controller separately and in parallel over the physical host interface (e.g., PCIe bus); [0025] As described above, NVMe virtualization module 113 associates one of physical functions 212-218 with each of virtual NVMe controllers 202-208 in order to allow each virtual NVMe controller 202-208 to appear as a physical controller on PCIe bus 210) to receive a request to perform at least one operation ([0026], As noted above, each physical function 212-218 can be assigned to any one of virtual machines 232-236 in the host system 120. When I/O data is received at a virtual NVMe controller 202-208 from a virtual machine 232-236 a virtual machine driver provides a guest physical address for a corresponding read/write command); and
an … physical partition, corresponding to the … physical function to perform the at least one operation ([0026], NVMe virtualization module 113 translates the physical function number to a bus, device, and function (BDF) number and then adds the command to a direct memory access (DMA) operation to perform the DMA operation on the guest physical address), wherein the … physical partition is one of the multiple physical partitions ([0035], As described above, each virtual NVMe controllers 202-208 appears as a separate physical PCIe device connected to PCIe bus 210 by virtue of each having a separate physical function).
However, Maharana does not explicitly teach the limitation of additional physical functions and additional physical partitions.
In other embodiments, Maharana teaches additional physical functions … additional physical partitions ([0023], In other embodiments, however, there may be any other number of NVMe controllers, each having a corresponding physical function; [0058], In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in illustrative sense rather than a restrictive sense) which is substantially similar to claim 6 and therefore rejected with similar rationale.
Examiner notes: It would be obvious to one of ordinary skill in the art to recognize that the device of claim 13 is being substantially recited again for the method of claim 6.
With regard to claim 15, Maharana teaches a computing device comprising ([0047], FIG. 7 illustrates an example machine of a computer system 700 within a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein, can be executed):
a hardware device, the hardware device including a physical function exposed on the bus to receive, via the bus ([0023], The virtual NVMe controllers 202-208 are virtual entities that appear as physical controllers to other devices, such as host system 120, connected to PCIe bus by virtue of a physical function 212-218 associated with each virtual NVMe controller 202-208), a request to perform one or more operations ([0024], Each of virtual NVMe controllers 202-208 manages storage access operations for the corresponding portion of the underlying memory components 112A to 112N, with which it is associated. For example, virtual NVMe controller 202 may receive data access requests from host system 120 over PCIe bus 210, including requests to read, write, or erase data in a first portion of memory component 112A. In response to the request, virtual NVMe controller 202 may perform the requested memory access operation on the data stored at an identified address in the first portion and return requested data and/or a confirmation or error message to the host system 120, as appropriate), and the hardware device further including a physical partition, corresponding to the physical function ([0022], NVMe virtualization module 113 further assigns a corresponding PCIe physical function to each virtual NVMe controller, causing each virtual NVMe controller to appear as a separately addressable PCIe device (i.e., a physical controller) connected to the PCIe bus between the memory subsystem 110 and the host system 120), to perform the one or more operations, wherein the physical partition is one of multiple physical partitions of the hardware device ([0026], As noted above, each physical function 212-218 can be assigned to any one of virtual machines 232-236 in the host system 120. When I/O data is received at a virtual NVMe (Examiner notes: each corresponding to a NVMe controller) control 202-208 from a virtual machine 232-236, a virtual machine driver provides a guest physical address for a corresponding read/write command. NVMe virtualization module 113 translates the physical function number to a bus, device, and function (BDF) number and then adds the command to a direct memory access (DMA) operation to perform the DMA operation on the guest physical address),
Maharana reasonably teaches physical function configuration spaces (Maharana, [0035]) and partitioning of memory into respective portions (Maharana, Abstract). However, Maharana does not explicitly teach that a physical partition supports a full configuration space including one or more compute resources, one or more memory resources, and one or more registers.
Ahmad teaches wherein the physical partition (Col. 43, lines 1-10, The SoC 100 may be coupled to a circuit board or card that is connected to the host data processing system 2802 by way of the PCIe link … The shell design, as implemented within the SoC 100, creates a plurality of partitions within the SoC 100. The term “partition” as used herein in connection with SoC 100, refers to a collection or set of SoC 100 resources that are allocated or reserved for use by any application that is implemented within that partition.) supports a full configuration space including one or more compute resources, one or more memory resources and one or more registers (Col. 27-Col. 28, lines 63-67 and lines 1-3, While SoC 100 has been largely described according to the different subsystems contained therein, e.g., Pl 104, PS 106, DPE array 102, NoC 108, and/or hardwired circuit blocks, the platform also provides resources in the form of “compute engines”, “hardware accelerator engines”, “memory resources”, “external interfaces”, and “pervasive interconnects” that extend across the different subsystems described; Col. 46, lines 34-43, As implemented, each application is only aware of the resources of the SoC 100 that are allocated to the partition in which that application is implemented … the PMC 1602 is configured to only allow each user to access the configuration space corresponding to that user’s partition. In other words, the PMC 1602 only allows user X to access the configuration space (e.g., configuration registers) for SoC 100 resources allocated to partition X (whether for a particular subset of the PL, a particular subset of the DPE array, and/or particular elements in the PS).) which is substantially similar to claim 1 and therefore rejected with similar rationale.
Examiner notes: It would be obvious to one of ordinary skill in the art to recognize that the device of claim 15 is being substantially recited again for the method of claim 1.
With regard to claim 16, Maharana teaches the computing device of claim 15, wherein the bus comprises a peripheral component interconnect express bus (FIG. 2, PCIe Bus 210; [0023], FIG. 2 illustrates an example physical host interface between a host system and a memory sub-system implementing NVMe direct virtualization in accordance with some embodiments of the present disclosure. In one embodiment, the controller 115 of memory sub-system 110 is connected to host system 120 over a physical host interface, such as PCIe bus 210).
With regard to claim 17, Maharana teaches the computing device of claim 15, further comprising:
an additional physical function exposed on the bus ([0027], Further, each physical function 212-218 may be implemented in either a privileged mode or normal mode … Typically a first physical function can implement a privileged mode and the remainder of the physical functions can implement a normal mode); and
a device management module, corresponding to the additional physical function, that manages the multiple physical partitions of the hardware device ([0027], When Implemented in the privileged mode, the physical function has a single point of management that can control resource manipulation and storage provisioning for other functions implemented in the normal mode. In addition, a physical function in the privileged mode can perform management options, including for example, enabling/disabling of multiple physical functions, storage and quality of service provisioning (QoS), firmware and controller updates, vendor unique statistics and events, diagnostics, secure erase/encryption, among others).
With regard to claim 18, Maharana teaches the computing device of claim 17, wherein the device management module is to:
receive, via the bus and the additional physical function, configuration information corresponding to software, the configuration information indicating resources requested for execution of the software ([0030], The associated virtual NVMe controller 202-208 may appear as a virtual storage resource to each of virtual machines 232, 234, 236 which the guest operating system or guest applications running therein can access; [0037], In one embodiment, controller 115 further includes quality of service (QoS) module 522 and sideband management (SM) bus 524. QoS can implement individual quality of service management for each virtual NVMe controller 202-208. When a large storage device, such as one of memory components 112A to 112N is sliced into smaller partitions, each controlled by a virtual NVMe controller 202-208, and that each can be used by different clients (e.g., virtual machines on host system 120), it may be beneficial to associate QoS characteristics with each individual partition (Examiner notes: A quality of service is associated with a minimum set of requirements and limitations governing an application’s access to system resources, enforced through controls such as time limits and predefined resource allocations). To meet these requirements, QoS module 522 attaches QoS controls (Examiner note: QoS controls receives service specification and allocates system resources to ensure software is executed with its defined service level) to each virtual NVMe controller 202-208); and
configure, based on the received configuration information, the physical partition including the indicated resources ([0037], The QoS controls may include, for example, an individual storage partition size, bandwidth, or other characteristics. QoS module 522 may monitor the performance of virtual NVMe controllers 202-208 over time and reconfigure resource assignments as needed to ensure compliance with QoS requirements).
With regard to claim 19, Maharana teaches the computing device of claim 15, further comprising:
an … physical function exposed on the bus ([0022], In one embodiment, the NVMe virtualization module 113 executes firmware or other logic to provide a number of virtual NVMe controllers in memory sub-system 110. NVMe virtualization module 113 associates each virtual NVME controller with a certain portion of the underlying memory components 112A to 112N, where each portion is addressable by a unique namespace. NVMe virtualization module 113 further assigns a corresponding PCIe physical function to each virtual NVMe controller, causing each virtual NVMe controller to appear as a separately addressable PCIe device (i.e., a physical controller) connected to the PCIe bus between the memory sub-system 110 and the host system 120. Host system 120, including separate virtual machines or partitions running thereon, can thus access each portion of the memory components 112A to 112N represented by a virtual NVMe controller separately and in parallel over the physical host interface (e.g., PCIe bus); [0025] As described above, NVMe virtualization module 113 associates one of physical functions 212-218 with each of virtual NVMe controllers 202-208 in order to allow each virtual NVMe controller 202-208 to appear as a physical controller on PCIe bus 210) to receive a request to perform at least one operation ([0026], As noted above, each physical function 212-218 can be assigned to any one of virtual machines 232-236 in the host system 120. When I/O data is received at a virtual NVMe controller 202-208 from a virtual machine 232-236 a virtual machine driver provides a guest physical address for a corresponding read/write command); and
an … physical partition, corresponding to the … physical function, to perform the at least one operation ([0026], NVMe virtualization module 113 translates the physical function number to a bus, device, and function (BDF) number and then adds the command to a direct memory access (DMA) operation to perform the DMA operation on the guest physical address), wherein the … physical partition is one of the multiple physical partitions ([0035], As described above, each virtual NVMe controllers 202-208 appears as a separate physical PCIe device connected to PCIe bus 210 by virtue of each having a separate physical function).
However, Maharana does not explicitly teach the limitation of additional physical functions and additional physical partitions.
In other embodiments, Maharana teaches additional physical functions … additional physical partitions ([0023], In other embodiments, however, there may be any other number of NVMe controllers, each having a corresponding physical function; [0058], In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in illustrative sense rather than a restrictive sense) which is substantially similar to claim 6 and therefore rejected with similar rationale.
Examiner notes: It would be obvious to one of ordinary skill in the art to recognize that the device of claim 19 is being substantially recited again for the method of claim 6.
Claims 7, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Maharana et al. Pub. No. US 2021/03116655 (hereinafter Maharana) in view of Ahmad et al. Patent No. US 11,063,594 B1 (hereinafter Ahmad) as applied to claim 1 above, and further in view of Kovacevic Pub. No. US 2020/0409732 A1 (hereinafter Kovacevic).
With regard to claim 7, Maharana teaches the method of claim 1, wherein the request is received from software … of a host rather than via a hypervisor ([0024], Each of virtual NVMe controllers 202-208 manages storage access operations for the corresponding portion of the underlying memory components 112A to 112N, with which it is associated. For example, virtual NVMe controller 202 may receive data access requests from host system 120 over PCIe bus 210, including requests to read, write, or erase data in a first portion of memory component 112A).
However, Maharana does not explicitly teach that the received software of a host is via a kernel mode driver.
Kovacevic teaches via a kernel mode driver ([0068], The kernel mode 610 also includes a kernel I/O manager 645 that manages the communication between applications and the interfaces provided by device drivers … Kernel Device Drivers receive data from applications, filters the data, and pass it to a lower-level driver that supports device functionality)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Kovacevic with the teachings of Maharana and Ahmad in order to provide a method that teaches request received by software of a host occurs through the kernel mode driver of the host. The motivation for applying Kovacevic teaching with Maharana and Ahmad teaching is to provide a method that allows for an abstracted interface of the hardware components present on a device to be provided, enabling operating systems and user mode programs access to device components and resources without requiring the precise knowledge of the implementation of such components (Kovacevic, [0068]), provides protection to the OS from erroneous or malicious code (Kovacevic, [0057]), and among other functionality (Kovacevic, [0060]-[0067]). Maharana, Ahmad, and Kovacevic are analogous art directed towards I/O management. Therefore, it would have been obvious for one of ordinary skill in the art to combine Kovacevic with Maharana and Ahmad to teach the claimed invention in order to provide a method for securely routing host software request across diverse hardware configurations.
With regard to claim 14, Maharana teaches the system of claim 8, wherein the request is received from software … of a host rather than via a hypervisor ([0024], Each of virtual NVMe controllers 202-208 manages storage access operations for the corresponding portion of the underlying memory components 112A to 112N, with which it is associated. For example, virtual NVMe controller 202 may receive data access requests from host system 120 over PCIe bus 210, including requests to read, write, or erase data in a first portion of memory component 112A).
However, Maharana does not explicitly teach that the received software of a host is via a kernel mode driver.
Kovacevic teaches via a kernel mode driver ([0068], The kernel mode 610 also includes a kernel I/O manager 645 that manages the communication between applications and the interfaces provided by device drivers … Kernel Device Drivers receive data from applications, filters the data, and pass it to a lower-level driver that supports device functionality) which is substantially similar to claim 7 and therefore rejected with similar rationale.
Examiner notes: It would be obvious to one of ordinary skill in the art to recognize that the device of claim 14 is being substantially recited again for the method of claim 7.
With regard to claim 20, Maharana teaches the computing device of claim 15, wherein the request is received from software … of a host than via a hypervisor ([0024], Each of virtual NVMe controllers 202-208 manages storage access operations for the corresponding portion of the underlying memory components 112A to 112N, with which it is associated. For example, virtual NVMe controller 202 may receive data access requests from host system 120 over PCIe bus 210, including requests to read, write, or erase data in a first portion of memory component 112A).
However, Maharana does not explicitly teach that the received software of a host is via a kernel mode driver.
Kovacevic teaches via a kernel mode driver ([0068], The kernel mode 610 also includes a kernel I/O manager 645 that manages the communication between applications and the interfaces provided by device drivers … Kernel Device Drivers receive data from applications, filters the data, and pass it to a lower-level driver that supports device functionality) which is substantially similar to claim 7 and therefore rejected with similar rationale.
Examiner notes: It would be obvious to one of ordinary skill in the art to recognize that the device of claim 20 is being substantially recited again for the method of claim 7.
Conclusion
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/I.A.C./Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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