DETAILED ACTION
This Office Action is in response to the Applicant Election filed on 06/29/2026.
Currently, claims 1-13 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-13) in the reply filed on 06/29/2026 is acknowledged. Claims 1-13 are examined in this Office action.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 167.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the dimension of the third insulative structure in the direction is the same or substantially the same as a dimension of the first conductive structure in the direction (see claim 5) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection(s) to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YAO et al. (US Pub. No. 2023/0011391).
Regarding independent claim 1, Yao teaches an integrated circuit (IC) device (Fig. 1A), comprising:
a first layer (Fig. 1A, layer corresponding to 114, ¶ [0016]), comprising:
a first conductive structure (Fig. 1A, leftmost 112, ¶ [0016]),
a first portion (Fig. 1A, 112 overlapping with 122) of a second conductive structure (Fig. 1A, 112 + 122, ¶ [0016]) that is in parallel with the first conductive structure, and
an electrical insulator (Fig. 1A, 114, ¶ [0016]) between the first conductive structure and the first potion of the second conductive structure; and
a second layer (Fig. 1A, layer corresponding to 118 and 120, ¶ [0016]) over the first layer, the second layer comprising:
a second portion (Fig. 1A, 122, ¶122 [0016]) of the second conductive structure, and
an insulative structure (Fig. 1A, 116 + 118, ¶¶ [0016] & [0018]) comprising a first insulative structure (Fig. 1A, 116, ¶ [0019]) and a second insulative structure (Fig. 1A, 118, ¶ [0019]), the second insulative structure at least partially surrounding the first insulative structure,
wherein a portion of the insulative structure is over the first conductive structure in a direction (Fig. 1A, 116 overlaps 112 vertically), and an axis of the insulative structure in the direction is aligned with an axis of the first conductive structure in the direction (Fig. 1A, 116 and leftmost 112 are vertically aligned).
Regarding claim 9, Yao teaches the IC device according to claim 1, and Yao teaches that the first conductive structure (Fig. 1A, leftmost 112, ¶ [0016]) comprises a different metal (¶ [0032] teaches that 112 can be metal. The left metal wire 112 is different from the middle metal wire 112 and 122 because they are separated and not integrally connected) from the second conductive structure (Fig. 1A, 112 + 122, ¶ [0016]).
Regarding claim 10, Yao teaches the IC device according to claim 1 and Yao teaches that the first conductive structure (Fig. 1A, leftmost 112, ¶ [0016]) or the second conductive structure (Fig. 1A, 112 + 122, ¶ [0016]) is connected to a first end of a via (Fig. 1A, top of 106, ¶ [0016]), a second end of the via is connected to an electrode of a transistor (Fig. 3, ¶ [0035] teaches that 106 can be connected to an electrode of semiconductor device 302), and the first layer (Fig. 1A, layer corresponding to 114, ¶ [0016]) is between the transistor and the second layer (Fig. 1A, layer corresponding to 118 and 120, ¶ [0016]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being obvious over YAO et al. (US Pub. No. 2023/0011391).
Regarding claim 8, Yao teaches the IC device according to claim 1, and Yao teaches that a distance from a center of the first conductive structure (Fig. 1A, leftmost 112, ¶ [0016]) to a center of the second conductive structure (Fig. 1A, 112 + 122, ¶ [0016]) in another direction (horizontally in Fig. 1A) perpendicular to the direction is no greater than 20 nanometers (¶ [0018] teaches that each 112 have a width d1 and spacing d2. Therefore, a center to center distance between the leftmost 112 and the right adjacent 112 would be d1+d2. ¶ [0018] teaches that d1 and d2 can each be 5-1000 nm. Therefore, a center to center distance between adjacent 112 can be between 10-2000 nm. The range taught by Yao overlaps with the range claimed. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05.).) .
Claims 2-5 are rejected under 35 U.S.C. 103 as being obvious over YAO et al. (US Pub. No. 2023/0011391) in view of YUAN et al. (US Pub. No. 2018/0053757).
Regarding claim 2, Yao teaches the IC device according to claim 1, and Yao teaches that the first layer (Fig. 1A, layer corresponding to 114, ¶ [0016]) further comprises a third conductive structure (Fig. 1A, 112 to the right of the 112 overlapping 122, ¶ [0016]),
the first portion (Fig. 1A, 112 overlapping with 122) of the second conductive structure (Fig. 1A, 112 + 122, ¶ [0016]) is between the first conductive structure and the third conductive structure in a first direction (horizontal in Fig. 1A).
However, Yao does not explicitly teach that the first conductive structure comprising a first portion and a second portion that are separated from each other by at least part of a third insulative structure,
a distance between a center of the first conductive structure and a center of the third conductive structure in the first direction is equal to or greater than a dimension of the third insulative structure in a second direction,
the first direction is perpendicular to the direction, and
the second direction is perpendicular to the direction and to the first direction.
However, Yuan is a pertinent art that teaches the first conductive structure (Fig. 4, 12, ¶ [0030]) comprising a first portion (Fig. 4, top portion of 12 separated by a signal cut 16) and a second portion (Fig. 4, bottom portion of 12 separated by a signal cut 16) that are separated from each other by at least part of a third insulative structure (Fig. 4, 16, ¶ [0030]),
a distance between a center of the first conductive structure and a center of the third conductive structure in the first direction is equal to or greater than a dimension of the third insulative structure in a second direction (Yao Fig. 1A, ¶ [0018] teaches that a distance d2 between adjacent wires 112 can be between 5-1000 nm. Yuan ¶ [0030] teaches that 16 can have a width of 30 nm or less in a depth direction, corresponding to up-down in Yao Fig. 1B and up-down in Yuan Fig. 4. Therefore, it would be obvious that a pitch between two of Yao’s wires can be more than the depth of Yuan’s signal cut),
the first direction (horizontal in Yao Fig. 1A) is perpendicular to the direction, and
the second direction is perpendicular to the direction (vertical in Yao Fig. 1A) and to the first direction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yao’s device to further include signal cuts according to the teaching of Yuan (Fig. 4) in order to define desired active metal lines in a BEOL interconnect system (Yuan ¶ [0026]).
Regarding claim 3, Yao modified by Yuan teaches the IC device according to claim 2, and Yao modified by Yuan teaches that the third conductive structure (Yao Fig. 1A, 112 to the right of the 112 overlapping 122, ¶ [0016]) comprising a third portion and a fourth portion (Yao modified by Yuan’s metal lines would have upper and lower portions separated by Yuan’s signal cuts 16 depending on the desired connections between components) that are separated from each other by at least part of the third insulative structure (Yuan Fig. 4, 16, ¶ [0030]).
Regarding claim 4, Yao modified by Yuan teaches the IC device according to claim 2, and Yao teaches that a distance between the center of the first conductive structure (Fig. 1A, leftmost 112, ¶ [0016]) and a center of the second conductive structure (Fig. 1A, 112 + 122, ¶ [0016]) in the first direction is approximately half of the distance (¶ [0018] teaches that each 112 have a width d1 and spacing d2. Therefore, a center to center distance between the leftmost 112 and the right adjacent 112 would be d1+d2, and the center to center distance between the leftmost 112 and the third 112 from the left would be about double d1+d2) between the center of the first conductive structure and the center of the third conductive structure (Fig. 1A, 112 to the right of the 112 overlapping 122, ¶ [0016]) in the first direction (horizontal in Fig. 1A).
Regarding claim 5, Yao modified by Yuan teaches the IC device according to claim 2, and Yao modified by Yuan teaches that a dimension of the third insulative structure (Yuan Fig. 4, 16, ¶ [0030]) in the direction (vertical in Yao Fig. 1A) is the same or substantially the same (Yuan ¶ [0030] teaches that signal cut 16 separates two edges of a metal line 12. Therefore, Yuan’s signal cut 16 would be a same or substantially same height as a metal line in order to sever it into two separate portions.) as a dimension of the first conductive structure (Yao Fig. 1A, leftmost 112, ¶ [0016]) in the direction.
Claims 6-7 are rejected under 35 U.S.C. 103 as being obvious over YAO et al. (US Pub. No. 2023/0011391) in view of JOY et al. (US Pub. No. 2021/0118693).
Regarding claim 6, Yao teaches the IC device according to claim 1.
However, Yao does not explicitly teach that a line edge roughness of a surface of the first conductive structure or the second conductive structure is between about 1.1 and 1.5 nanometers.
However, Joy is a pertinent art that teaches that a line edge roughness of a surface of the first conductive structure or the second conductive structure is between about 1.1 and 1.5 nanometers (¶ [0048] teaches a line edge roughness of Joy’s metal lines can be about 0.5 nm to about 2 nm. The range taught by Joy overlaps with the range claimed. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05.).).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the line edge roughness of Yao’s lines/wires to be between 0.5 nm to 2 nm according to the teaching of Joy (¶ [0048]) in order to reduce random resistance variations (Joy ¶ [0037]).
Regarding claim 7, Yao modified by Joy teaches the IC device according to claim 5, and Joy teaches that the line edge roughness of the surface of the first conductive structure or the second conductive structure is about 1.2 nanometer ((¶ [0048] teaches a line edge roughness of Joy’s metal lines can be about 0.5 nm to about 2 nm.).
Claim 11 is rejected under 35 U.S.C. 103 as being obvious over YAO et al. (US Pub. No. 2023/0011391) in view of YANG et al. (US Pub. No. 2021/0242076).
Regarding independent claim 11, Yao teaches an integrated circuit (IC) device (Fig. 1A), comprising:
a plurality of structures (Fig. 1A, 116 + 118 + 112, ¶ [0016]), an individual structure comprising:
a first structure (Fig. 1A, 116, ¶ [0020]) comprising a first electrical insulator (¶ [0020] teaches that 116 can be an insulator such as silicon oxide),
a second structure (Fig. 1A, 118 surrounding 116, ¶ [0031]) comprising a second electrical insulator (¶ [0031]) and at least partially surrounding the first structure, and
a third structure (Fig. 1A, 112 overlapping 116, ¶ [0032]) over at least part of the first structure in a direction (vertical in Fig. 1A), the third structure comprising an electrically conductive material (¶ [0032]); and
a conductive structure (Fig. 1A, 112 + portion of 122 below a height of 118, ¶ [0016]) in parallel with the plurality of structures.
wherein a dimension of an individual conductive structure in the direction is the same or substantially the same as a dimension of the individual structure in the direction (Fig. 1A, a vertical height of 112, 116, and 118 is about the same as a vertical height of 112 and a portion of 122 below a height of 118).
However, Yao does not explicitly teach a plurality of conductive structures that are in parallel with the plurality of structures, individual conductive structures alternating with individual structures.
However, it would be obvious to modify Yao’s device to include additional interconnect vias 122 alternating with interconnect wires 112 not connected with an interconnect via in a similar manner to Yang (see Yang Fig. 16, 200, ¶ [0031]) depending on desired power/signal routing.
Claim 12 is rejected under 35 U.S.C. 103 as being obvious over YAO et al. (US Pub. No. 2023/0011391) in view of YANG et al. (US Pub. No. 2021/0242076) and further in view of YUAN et al. (US Pub. No. 2018/0053757).
Regarding claim 12, Yao in view of Yang teaches the IC device according to claim 11.
However, Yao does not explicitly teach that the third structure comprises a first portion and a second portion that are separated from each other by an insulative structure, a distance between two adjacent structures in a first direction is equal to or greater than a dimension of the insulative structure in a second direction, the first direction is perpendicular to the direction, and the second direction is perpendicular to the direction and to the first direction.
However, Yuan is a pertinent art that teaches that the third structure (Fig. 4, 12, ¶ [0030]) comprises a first portion (Fig. 4, top portion of 12 separated by a signal cut 16) and a second portion (Fig. 4, bottom portion of 12 separated by a signal cut 16) that are separated from each other by an insulative structure (Fig. 4, 16, ¶ [0030]), a distance between two adjacent structures in a first direction (left to right in Yuan Fig. 4 and left to right in Yao Fig. 1A) is equal to or greater than a dimension of the insulative structure in a second direction (Yao Fig. 1A, ¶ [0018] teaches that a distance d2 between adjacent wires 112 can be between 5-1000 nm. Yuan ¶ [0030] teaches that 16 can have a width of 30 nm or less in a depth direction, corresponding to up-down in Yao Fig. 1B and up-down in Yuan Fig. 4. Therefore, it would be obvious that a pitch between two of Yao’s wires can be more than the depth of Yuan’s signal cut), the first direction is perpendicular to the direction, and the second direction is perpendicular to the direction and to the first direction.
Claim 13 is rejected under 35 U.S.C. 103 as being obvious over YAO et al. (US Pub. No. 2023/0011391) in view of YANG et al. (US Pub. No. 2021/0242076) and further in view of JOY et al. (US Pub. No. 2021/0118693).
Regarding claim 13, Yao in view of Yang teaches the IC device according to claim 11.
However, Yao does not explicitly teach that a line edge roughness of a surface of the third structure or the individual conductive structure is between about 1.1 and 1.5 nanometers.
However, Joy is a pertinent art that teaches that a line edge roughness of a surface of the third structure or the individual conductive structure is between about 1.1 and 1.5 nanometers (¶ [0048] teaches a line edge roughness of Joy’s metal lines can be about 0.5 nm to about 2 nm. The range taught by Joy overlaps with the range claimed. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05.).).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the line edge roughness of Yao’s lines/wires to be between 0.5 nm to 2 nm according to the teaching of Joy (¶ [0048]) in order to reduce random resistance variations (Joy ¶ [0037]).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2022/0344264 by Yao et al discloses a semiconductor device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2020/0243377 by Liu discloses a semiconductor device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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