DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to the specification has been fully considered and resolve the specification objections. The specification objections have been withdrawn.
Applicant’s amendments to the claim 4 has been fully considered and resolve the 35 USC $112(b) rejections. The 35 USC $112(b) rejection has been withdrawn.
Applicant's arguments filed on 08/03/2026 have been fully considered but they are not persuasive. Applicant argues on pages 9 and 10 that the amended claim 1 and claim 8 limitations are not disclosed by the cited prior arts. Examiner respectfully disagrees. Hsieh discloses all the amended claim 1 and claim 8 limitations. The newly added claims 21-26 have introduced a new reference Tsai (US20220223684A1). Please see rejections below.
Claim Objections
Claim 8 is objected to because of the following informalities:
Claim 8 recites “a first via connected to the first conductive structure, and the via first separated..”; this should be written as “a first via connected to the first conductive structure, and the first via separated..”
Claim 8 recites “wherein the first portion is over the first conductive structure, and a second portion is over the second conductive structure”; this should be written as “wherein the first portion is over the first conductive structure, and the second portion is over the second conductive structure”
Claim 8 recites the “a second conductive structure in parallel with the first conductive structure in a direction” in line 3 of the claim. The same limitation is duplicated as “the first conductive structure is in parallel with the second conductive structure” in line 12 of the claim. One of the limitations should be removed.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23 and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites “wherein a cross-section of the first portion of the first via is smaller than a cross-section of a second portion of the first via” is unclear. This limitation is interpreted as “wherein a cross-sectional width of the first portion of the first via is less than a cross-sectional width of a second portion of the first via”
Claim 24 recites “wherein a cross-section of the first portion of the second via is smaller than a cross-section of a second portion of the second via” is unclear. This limitation is interpreted as “wherein a cross-sectional width of the first portion of the second via is less than a cross-sectional width of a second portion of the second via”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4 - 9, 12 – 14, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US20210028062A1; hereinafter Hsieh).
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Hsieh: FIG. 25
Regarding Claim 1 (Amended), Hsieh discloses an integrated circuit (IC) device (transistor and its overlying structure, [0008]), comprising:
a layer (IDL1 64), FIG. 25 reproduced above, [0021], comprising:
a gate contact of a transistor (gate contact plug 98), FIG. 25, [0030],
an additional contact of the transistor (source/drain contact plugs 96), FIG. 25, [0030], and
an electrical insulator (contact spacers 92) between the gate contact (98) and the additional contact (96), FIG. 25, [0030];
a first via (via 118 over 98) over the layer (64) in a direction (vertical direction), the first via connected to the gate contact (via 118 connected to gate contact plug 98 through metal line 108), FIG. 25, [0033], [0035];
a second via (via 118 over 96) over the layer (64) in the direction (vertical direction), the second via connected to the additional contact (via 118 connected to source/drain plug 96 through metal line 108), FIG. 25, [0033], [0035]; and
an insulative structure (dielectric layers 120 and 114) over the layer (64) in the direction (vertical direction), the insulative structure comprising a first insulative structure (spacers 120) and a second insulative structure (dielectric layer 114) at least partially surrounding the first insulative structure (120), FIG. 24, [0034], [0035].
wherein the gate contact (98) is in parallel with the additional contact (96), FIG. 25, [0030],
the first via (via 118 over 98) is in parallel with the second via (via 118 over 96), the insulative structure (dielectric layers 120 and 114) is between the first via and the second via, FIGS. 24 & 25, [0034], [0035].
Hsieh discloses all the elements of claim 1 except for “a dimension of the gate contact (98) in the direction is the same or substantially the same as a dimension of the additional contact (96) in the direction.” It has been held where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777. In the instant case the prior art device would not perform differently if modified to the claimed dimensions. Therefore the claimed limitations are considered met.
Regarding Claim 2 (Original), Hsieh discloses the IC device according to claim 1.
Hsieh discloses: wherein the first insulative structure (120) is over the electrical insulator (92), and at least a portion of the second insulative structure (114) is over the gate contact (98) or the additional contact (96), FIG. 25, [0030], [0035].
Regarding Claim 4 (Amended) , Hsieh discloses the IC device according to claim 1.
Hsieh discloses: wherein the insulative structure (dielectric layers 120 and 114) comprises another electrical insulator that is different from the electrical insulator (92) between the gate contact (98) and the additional contact (96), [0029], [0030], [0034].
Hsieh [0029], [0030] discloses the spacer 92 includes SiN, AlN, and HfOx. Hsieh [0034] discloses the dielectric layer 114 may be formed of a low k dielectric material. Therefore the insulative structure includes 114 which comprises a different material from the electrical insulator 92.
Regarding Claim 5 (Original), Hsieh discloses the IC device according to claim 1.
Hsieh discloses: wherein the first insulative structure (120) and the second insulative structure (114) comprise different materials, [0022], [0023], [0034], [0035].
Hsieh [0034] discloses the dielectric layer 114 may be formed of a low k dielectric material. Hsieh [0022], [0023], [0035] discloses spacers 120 may be formed of a dielectric material selected from SiN, SiON, and HfOx. Therefore, the first insulative structure 120 and the second insulative structure 114 comprise of different materials.
Regarding Claim 6 (Original), Hsieh discloses the IC device according to claim 1.
Hsieh discloses: further comprising:
an additional insulative structure (110) over the layer (64), wherein the additional contact (96) is separated from the first via (via 118 over 98) by the additional insulative structure (metal line spacers 110), FIG. 25, [0033].
Regarding Claim 7 (Original), Hsieh discloses the IC device according to claim 1.
Hsieh discloses: wherein the gate contact (98) is over at least part of a channel region of the transistor (region beneath gate stack 32, [0012]), and the additional contact (96) is over at least part of a source region or a drain region (source/drain region 42, [0015]) of the transistor, FIG. 25, [0030].
Regarding Claim 8 (Amended), Hsieh discloses an integrated circuit (IC) device (transistor and its overlying structure, [0008]), comprising:
a first conductive structure (gate contact plug 98 with the corresponding metal lines 108), FIG. 25, [0030], [0033].
a second conductive structure (source/drain contact plugs 96 with the corresponding metal lines 108) in parallel with the first conductive structure (98 with 108) in a direction (vertical direction), FIG. 25, [0030], [0033].
an insulative structure (dielectric layers 120 and 114) comprising a first portion (spacer 120 positioned over 98 and corresponding metal lines 108) and a second portion (spacer 120 positioned over 96 and corresponding metal lines 108), wherein the first portion is over the first conductive structure (98 and corresponding metal lines 108), and a second portion is over the second conductive structure (96 and corresponding metal lines 108), FIG. 24, [0034], [0035];
a first via (via 118 over 98) connected to the first conductive structure (98 and corresponding metal lines 108), the first via (118 over 98) separated from the second conductive structure (96 and corresponding metal lines 108) by the insulative structure (portions of 120 and 114), FIG. 25, [0034], [0035]; and
a second via (via 118 over 96) connected to the second conductive structure (96 and corresponding metal lines 108), FIG. 25, [0034], [0035].
wherein the first conductive structure (98 with corresponding 108) is in parallel with the second conductive structure (96 with corresponding 108), the first via (118 over 98) is in parallel with the second via (118 over 96), and the insulative structure (dielectric layers 120 and 114) is between the first via (118 over 98) and the second via, (118 over 96), FIG. 25, [0034], [0035].
Hsieh discloses all the elements of claim 8 except for “wherein a dimension of the second conductive structure (96 with corresponding 108) in the direction is the same or substantially the same as a dimension of the first conductive structure (98 with corresponding 108) in the direction.” It has been held where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777. In the instant case the prior art device would not perform differently if modified to the claimed dimensions. Therefore the claimed limitations are considered met.
Regarding Claim 9 (Original), Hsieh discloses the IC device according to claim 8.
Hsieh discloses: wherein the second conductive structure (96 with corresponding 108) is separated from the first conductive structure (98 with corresponding 108) by an electrical insulator (92), FIG. 25, [0030],
the insulative structure (dielectric layers 120 and 114) further comprises a third portion (114), and the third portion is over the electrical insulator (92), FIG. 25, [0034], [0035].
Regarding Claim 12 (Original), Hsieh discloses the IC device according to claim 9.
Hsieh discloses: wherein the insulative structure (120 and 114) comprises a different material from the electrical insulator (92), [0029], [0030], [0034].
Hsieh [0029], [0030] discloses the spacer 92 is formed of materials including SiN, AlN, and HfOx. Hsieh [0034] discloses the dielectric layer 114 may be formed of a low k dielectric material. Therefore the insulative structure includes 114 which comprises a different material from the electrical insulator 92.
Regarding Claim 13 (Original), Hsieh discloses the IC device according to claim 9.
Hsieh discloses: wherein the third portion (114) comprises a different material from the first portion or the second portion (120 positioned over 96 and 108), [0022], [0023], [0034], [0035].
Hsieh [0034] discloses the dielectric layer 114 may be formed of a low k dielectric material. Hsieh [0022], [0023], [0035] discloses spacers 120 may be formed of a dielectric material selected from SiN, SiON, and HfOx. Therefore, the third portion 114 comprises a different material from the first portion 120 or the second portion 120.
Regarding Claim 14 (Original), Hsieh discloses the IC device according to claim 8.
Hsieh discloses: further comprising: an additional insulative structure (110) between the second conductive structure (96 with corresponding 108) and the first via (via 118 over 98), FIG. 25, [0033].
Regarding 25 (New), Hsieh discloses the IC device according to claim 8, wherein the first portion (spacer 120 positioned over 98 with metal lines 108) of the insulative structure (dielectric layers 120 and 114) contacts the first via (118 over 98), FIG. 25, [0034], [0035].
Regarding Claim 26 (New), Hsieh discloses the IC device according to claim 8, wherein the second portion (spacer 120 positioned over 96 with metal lines 108) of the insulative structure (dielectric layers 120 and 114) contacts the second via (118 over 96), FIG. 25, [0034], [0035].
Claims 3, 10, 11, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Lee et al. (US20200027786A1; hereinafter Lee).
Regarding Claim 3 (Original), Hsieh discloses the IC device according to claim 1.
Hsieh does not disclose “wherein an edge of the first insulative structure is aligned with an edge of the gate contact or an edge of the additional contact in the direction.”
In a similar art, Lee discloses semiconductor devices including a transistor and contact plugs [0002].
Lee discloses: wherein an edge of the first insulative structure (134a) is aligned with an edge of the gate contact (144) or an edge of the additional contact in the direction, FIG. 4, [0044].
Lee discloses that a device as taught prevents shorting and improves isolation between the gate and source/drain contacts [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hsieh’s device in order to prevent shorting and improve isolation between the gate and source/drain contacts as disclosed by Lee [0080].
Regarding Claim 10 (Original), Hsieh discloses the IC device according to claim 9.
Hsieh does not disclose “wherein an edge of the third portion is aligned with an edge of the first conductive structure in the direction.”
Lee discloses: wherein an edge of the third portion (136b) is aligned with an edge of the first conductive structure (contact plug 126) in the direction (vertical direction), FIG. 16, [0073].
Lee discloses that a device as taught prevents shorting and improves isolation between the gate and source/drain contacts [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to prevent shorting and improve isolation between the gate and source/drain contacts as disclosed by Lee [0080].
Regarding Claim 11 (Original), The combination of Hsieh and Lee discloses the IC device according to claim 10.
Hsieh does not disclose “wherein another edge of the third portion is aligned with an edge of the second conductive structure in the direction.”
Lee discloses: wherein another edge of the third portion (136b) is aligned with an edge of the second conductive structure (144) in the direction, FIG. 4, [0044].
Lee discloses that a device as taught prevents shorting and improves isolation between the gate and source/drain contacts [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to prevent shorting and improve isolation between the gate and source/drain contacts as disclosed by Lee [0080].
Regarding Claim 21 (New), Hsieh discloses the IC device according to claim 1.
Hsieh does not disclose “wherein the second insulative structure contacts the first via and the second via.”
Lee discloses: wherein the second insulative structure (130b) contacts the first via (126) and the second via (144), FIG. 4, [0036].
Lee discloses that a device as taught prevents shorting and improves isolation between the gate and source/drain contacts [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hsieh’s device in order to prevent shorting and improve isolation between the gate and source/drain contacts as disclosed by Lee [0080].
Regarding Claim 22 (New), Hsieh discloses the IC device according to claim 1.
Hsieh does not disclose “wherein a first surface of the second insulative structure contacts the first via, wherein a second surface of the second insulative structure contacts the second via, and wherein the first surface opposes the second surface.”
Lee discloses: wherein a first surface of the second insulative structure (sidewall of 130b) contacts the first via (126), wherein a second surface of the second insulative structure (opposing sidewall of 130b) contacts the second via (144), and wherein the first surface opposes the second surface, FIG. 4, [0036].
Lee discloses that a device as taught prevents shorting and improves isolation between the gate and source/drain contacts [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Hsieh’s device in order to prevent shorting and improve isolation between the gate and source/drain contacts as disclosed by Lee [0080].
Claims 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Lee, further in view of Tsai et al. (US20220223684A1; hereinafter Tsai).
Regarding 23 (New), Hsieh discloses the IC device according to claim 1.
Hsieh does not disclose “wherein the second insulative structure contacts a first portion of the first via, wherein a cross-section of the first portion of the first via is smaller than a cross-section of a second portion of the first via.”
Lee discloses: wherein the second insulative structure (130b) contacts a first portion of the first via (upper side wall of 126), FIG. 4, [0036].
In a similar art, Tsai discloses a method of fabricating a semiconductor device. FIG. 16, [0011].
Tsai FIG. 13, [0048] discloses a deposition process 740 is performed to the IC device 200 to form a source/drain via 750. The via 750 can have a cross-sectional view profile where it has a wider upper portion 750A and a narrower lower portion 750B and the via is disposed in the dielectric layers ESL 610 and the ILD 660.
The combination of Hsieh, Lee, and Tsai discloses: wherein a cross-section of the first portion of the first via (Lee: width of the upper side wall of 126) is smaller than a cross-section of a second portion of the first via (Lee: width of another portion of 126), as disclosed by Tsai, FIG. 13, [0048], via 750 with a narrower portion 750B and wider portion 750A. Therefore the combination of Hsieh, Lee, and Tsai discloses the cross-section of the first portion of the first via is smaller than a cross-section of a second portion of the first via.
Tsai discloses that a device as taught maximizes processing window for forming vias and preventing unintended electrical bridging [0049]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to maximize processing window for forming vias and preventing unintended electrical bridging as disclosed by Tsai [0049].
Regarding 24 (New), Hsieh discloses the IC device according to claim 1.
Hsieh does not disclose “wherein the second insulative structure contacts a first portion of the second via, wherein a cross-section of the first portion of the second via is smaller than a cross-section of a second portion of the second via.”
Lee discloses: wherein the second insulative structure (130b) contacts a first portion of the second via (a portion of sidewall of 144), FIG. 4, [0036].
Tsai FIG. 13, [0048] discloses a deposition process 740 is performed to the IC device 200 to form a source/drain via 750. The via 750 can have a cross-sectional view profile where it has a wider upper portion 750A and a narrower lower portion 750B and the via is disposed in the dielectric layers ESL 610 and the ILD 660.
The combination of Hsieh, Lee, and Tsai discloses: wherein a cross-section of the first portion of the second via (Lee: width of a portion of the side wall of 144) is smaller than a cross-section of a second portion of the second via (Lee: width of another portion of the side wall of 144), as disclosed by Tsai, FIG. 13, [0048], via 750 with a narrower portion 750B and wider portion 750A. Therefore the combination of Hsieh, Lee, and Tsai discloses the cross-section of the first portion of the second via is smaller than a cross-section of a second portion of the second via.
Tsai discloses that a device as taught maximizes processing window for forming vias and preventing unintended electrical bridging [0049]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to maximize processing window for forming vias and preventing unintended electrical bridging as disclosed by Tsai [0049].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to Krishna J Palaniswamy whose telephone number
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supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number
for the organization where this application or proceeding is assigned is 571-483-7639.
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
