Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 12/15/2022 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because the non-patent literature submitted does not contain the proper bibliographic information as required by 37 CFR 1.98(b)(5). It has been placed in the application file, but the information referred to therein has not been considered as to the merits. The remainder of the information disclosure statement is in compliance with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609, and has been placed in the application file and the information referred to therein has been considered as to the merits.
Non-patent Literature documents 4, 5, & 6 fail to disclose pertinent page numbers.
Since the submission appears to be bona fide, applicant is given ONE (1) MONTH from the date of this notice to supply the above mentioned omissions or corrections in the information disclosure statement. NO EXTENSION OF THIS TIME LIMIT MAY BE GRANTED UNDER EITHER 37 CFR 1.136(a) OR (b). Failure to timely comply with this notice will result in the above mentioned information disclosure statement being placed in the application file with the non-complying information not being considered. See 37 CFR 1.97(i).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-8, 13-15, & 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gschwind et al PG Pub US 2017/0199742 A1 [hereinafter Gschwind].
Regarding claims 1, 8, & 15, Gschwind discloses:
managing, within a processor, an instruction effective-to-real-address table (I- ERAT) (the one or more directories may include an instruction translation lookaside buffer (ITLB) containing virtual address to physical address mapping. The instruction translation lookaside buffer is sometimes alternatively referred to as an instruction effective-to-real address translation (IERAT) directory[0004]) separate from a main ERAT (Instruction cache 310 includes multiple instruction cache lines, with each instruction cache line having multiple cache line segments, and each cache line segment including multiple instructions [0053]), wherein the I-ERAT has a smaller storage capacity than the main ERAT (a TLB is a buffer that caches data/instructions from a larger cache sed to speed up virtual-to-physical address translation for both executable instructions and data [0051]);
indicating an I-ERAT hit based on determining that an instruction address for an instruction cache is stored in the I-ERAT; bypassing an arbitrator within the processor and sending a translated address from the I-ERAT to the instruction cache based on detecting the I-ERAT hit (With an instruction hit being provided by hit/miss logic 340, an instruction is retrieved from the appropriate instruction cache line in instruction cache 310 and maintained in a cycle-boundary latch (CBL) 311 for instruction decode 312 for processing in the next cycle [0054] The suppress signal suppresses access to the instruction translation table for the next instruction fetch. The method may further include issuing an instruction cache hit where there is an address match between the results of the instruction directory access for the next instruction fetch and the buffered results of the most recent, instruction address translation table access [0008]); and
sending an address translation request through the arbitrator to the main ERAT based on an I-ERAT miss and writing a translation result of the main ERAT to the I- ERAT (if the segment is invalid, a cache miss is signaled even upon an address match between the addresses returned by the IDIR and ITLB [0055]).
Regarding claims 6, 13, & 20, the limitations of these claims have been noted in the rejection of claims 1, 8, & 15, Gschwind also discloses:
wherein the processor is a multi- thread processor and address mapping through the I-ERAT is based on a number of threads (Where the instruction cache is part of a simultaneous multi-threading (SMT) environment, the method may include generating a suppress signal for a particular thread of the simultaneous, multithread environment where, for the particular thread, the next instruction fetch is from the same address page, and the last instruction is not a branch instruction, or if a branch instruction [0013]).
Regarding claims 7 & 14, the limitations of these claims have been noted in the rejection of claims 1 & 8, Gschwind also discloses:
wherein bypassing of the arbitrator is further based on determining that an arbitration cycle of the arbitrator is available (for a next instruction fetch, processing accesses the instruction directory 320 to obtain the physical memory address of the instruction stored in the corresponding instruction cache line. For the entire cache line, this information is maintained in a cycle-boundary latch 321 for processing in the next cycle (or subsequent cycles) [0055]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 9-11, & 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Gschwind in view of Gaertner et al. PG Pub US 2011/0320761 A1 [hereinafter Gaertner].
Regarding claims 2, 9, & 16, the limitations of these claims have been noted in the rejection of claims 1, 8, & 15, it is noted that Gschwind failed to explicitly disclose:
wherein the processor comprises an instruction fetch unit (IFU) and a load store unit (LSU)
However, Gaertner discloses:
wherein the processor comprises an instruction fetch unit (IFU) and a load store unit (LSU) (The address translation unit receives address translation requests from a Load Store Unit (LSU), a Coprocessor (CoP) for data compression and cryptography, and/or an Instruction Fetch Unit (IFU), for example, wherein the LSU has the highest priority and the IFU has the lowest priority [0003]).
The systems of Gschwind and Gaertner are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Gschwind and Gaertner since “the lookup under miss sequence is only performed for LSU requests under lookup operation misses in the translation look aside buffer for IFU translation requests or CoP translation requests as current translation requests [0025].”
Regarding claims 3, 10, & 17, the limitations of these claims have been noted in the rejection of claims 2, 9, & 16, Gaertner also discloses:
wherein the I-ERAT is distributed between the IFU and the LSU with effective addresses stored in the IFU and real addresses stored in the LSU (The address translation unit receives address translation requests from a Load Store Unit (LSU), a Coprocessor (CoP) for data compression and cryptography, and/or an Instruction Fetch Unit (IFU), for example, wherein the LSU has the highest priority and the IFU has the lowest priority [0003]).
Regarding claims 4, 11, & 18, the limitations of these claims have been noted in the rejection of claims 3, 10, & 17, Gaertner also discloses:
wherein the LSU comprises the arbitrator and the main ERAT (the lookup under miss sequence is only performed for LSU requests under lookup operation misses in the translation look aside buffer for IFU translation requests or CoP translation requests as current translation requests [0025]).
Allowable Subject Matter
Claims 5, 12, & 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to disclose “wherein address translation through the I-ERAT completes at least two cycles faster than through the arbitrator and the main ERAT” as disclosed in claims 5, 12, & 19.
Gschwind discloses a system designed to reduce power consumption. The rejected claims as presented are being interpreted to read on the system of Gschwind. The examiner suggests amending the rejected claims to better define the limitations of an arbitrator, and its use.
Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Grohoski et al. PG Pub US 2010/0332786 A1 discloses invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN D ROSSITER whose telephone number is (571)270-3788. The examiner can normally be reached M-F 8AM-4PM.
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/SEAN D ROSSITER/Primary Examiner, Art Unit 2133