DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/05/2025 has been entered.
Applicant’s arguments filed on 08/05/2025 with respect to claims 1-20 have been fully considered but are not persuasive.
With respect to claim limitation “an edge-triggered pulse generator circuit configured to generate an updated clock signal having an updated clock edge triggered by an edge of the serial clock signal received from the previous node in the chain”, considering that clock circuitry 286 of figures 14 and 17 of Pyeon is being equated to claim ‘edge-triggered pulse generator circuit’, see paragraph 0133 of Pyeon, which discloses “The clock circuitry 286 includes a clock reproducer for adjusting the delay of incoming clock signal and producing properly synchronized clock signals. For this purpose, there are various possible implementations for the clock reproducer, for example, using a PLL or DLL, to adjust or synchronize clocks….. The clock regenerator of the clock circuitry 286 provides an output source synchronous clock signal CLKcsyco 289 synchronized with the input source synchronous clock signal CLKssyci 287 to the next device. The output clock signal CLKssyco 289 is the reproduced version of the input clock signal CLKssyci”. Note, based on the claim language, having an updated/reproduced clock signal ‘triggered’ by the input clock signal is equated to the output clock signal being edged.
With respect to claim limitation “logic circuitry configured to latch data on the serial data input using the serial clock signal received on the serial clock input and to send the updated serial clock signal on a serial clock output of the network node to the serial clock input of a next network node in the chain”, see paragraph 0133, which discloses “In response to an input source synchronous clock signal CLKcsyci 287, the clock circuitry 286 delivers clocks to the input circuitry 282, the memory core circuitry 288 and the output circuitry 284 for their respective operation.…. The input circuitry 222 and the output circuitry 284 perform interface operations in response to the clocks provided by the clock circuitry 286”.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-7 and 9-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pyeon et al., (US pub. # 2009/0154629), hereinafter, “Pyeon”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 1, 9 and 15, Pyeon discloses a serial communication network (see abstract of Pyeon), the network comprising: multiple network nodes (memory devices 1-4, as discloses in figs. 15 and 17) connected serially as a chain of network nodes (see fig. 15 and paragraph 0134), wherein each network node includes: a serial data input to receive data from a previous node in the chain (see paragraph 0135); a serial clock input to receive a serial clock signal from the previous node in the chain (see paragraph 0135); an edge-triggered pulse generator circuit (clock circuitry 286 of fig. 17, as discloses in paragraph 0133) configured to generate an updated clock signal having an updated clock edge triggered by an edge of the serial clock signal received from the previous node in the chain (see fig. 33A, paragraphs 0133, 0135 and 0230, particularly paragraph 0133, which discloses “The clock circuitry 286 includes a clock reproducer for adjusting the delay of incoming clock signal and producing properly synchronized clock signals. For this purpose, there are various possible implementations for the clock reproducer, for example, using a PLL or DLL, to adjust or synchronize clocks….. The clock regenerator of the clock circuitry 286 provides an output source synchronous clock signal CLKcsyco 289 synchronized with the input source synchronous clock signal CLKssyci 287 to the next device. The output clock signal CLKssyco 289 is the reproduced version of the input clock signal CLKssyci”); and logic circuitry (a clock reproducer, as disclose in paragraph 0133 and fig. 17) configured to latch data on the serial data input using the serial clock signal received on the serial clock input (see paragraph 0133, which discloses “In response to an input source synchronous clock signal CLKcsyci 287, the clock circuitry 286 delivers clocks to the input circuitry 282, the memory core circuitry 288 and the output circuitry 284 for their respective operation.…. The input circuitry 222 and the output circuitry 284 perform interface operations in response to the clocks provided by the clock circuitry 286”) and to send the updated serial clock signal on a serial clock output of the network node to the serial clock input of a next network node in the chain and send the data on a serial data output of the network node synchronized to the updated clock edge of the updated serial clock signal to the serial data input of the next network node in the chain (see fig. 17 and paragraph 0133, which discloses “FIG. 14 shows details of one of the memory devices shown in FIG. 13. Referring to FIG. 14, Device i has input circuitry 282 for receiving an input signal 283, output circuitry 284 for providing an output signal 285, clock circuitry 286 and memory core circuitry 288. The clock circuitry 286 includes a clock reproducer for adjusting the delay of incoming clock signal and producing properly synchronized clock signals. For this purpose, there are various possible implementations for the clock reproducer, for example, using a PLL or DLL, to adjust or synchronize clocks. In response to an input source synchronous clock signal CLKcsyci 287, the clock circuitry 286 delivers clocks to the input circuitry 282, the memory core circuitry 288 and the output circuitry 284 for their respective operation. The clock regenerator of the clock circuitry 286 provides an output source synchronous clock signal CLKcsyco 289 synchronized with the input source synchronous clock signal CLKssyci 287 to the next device. The output clock signal CLKssyco 289 is the reproduced version of the input clock signal CLKssyci. The input circuitry 222 and the output circuitry 284 perform interface operations in response to the clocks provided by the clock circuitry 286”).
3. As per claims 2 and 10, Pyeon discloses “The network of claim 1” [See rejection to claim 1 above], wherein the multiple network nodes include a master network node, and the serial clock signal originates from serial clock output of the master network node; and wherein the master network node includes a serial clock input connected to a serial clock output of a last network node of the multiple network node, and a serial data input connected to a serial data output of the last network node of the multiple network nodes, and wherein the master network node clocks data from the serial data output of the last network node using the updated clock edge of the updated serial clock signal output by the last network node (see fig. 15).
4. As per claims 3, 11 and 16, Pyeon discloses wherein the master network node that includes a chip select output, and the other network nodes of the multiple network nodes include a chip select input connected to the chip select output of the master network node (see fig. 15).
5. As per claims 4 and 17, Pyeon discloses wherein the other network nodes of the multiple network nodes include a five-wire interface (see fig. 16).
6. As per claims 5 and 12, Pyeon discloses wherein the multiple network nodes include a master network node, and the other network nodes of the multiple network nodes include a chip select input and a chip select output; wherein the chip select input of a network node is connected to a chip select output of a previous network node and the chip select output of the network node is connected to the ship select input of the next network node (see fig. 15 and abstract).
7. As per claims 6 and 19, Pyeon discloses wherein the other network nodes of the multiple network nodes include a six-wire interface (see fig. 16).
8. As per claims 7, 13, 18 and 20, Pyeon discloses wherein the multiple network nodes include a master network node to generate a master serial clock signal, and the other network nodes of the multiple network nodes include a one-shot circuit as the edge triggered pulse generator circuit to generate the updated serial clock signal having the updated clock edge and a predetermined pulse width (see paragraphs 0133 and 0135).
9. As per claim 14, Pyeon discloses wherein the updating the clock signal at the individual subordinate node of the network includes updating the clock signal by a one-hundredth subordinate node of the network (see paragraphs 0133 and 0135).
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claim 8 is rejected under 35 U.S.C. 103(a) as being unpatentable over Pyeon et al., (US pub. # 2009/0154629), hereinafter, “Pyeon”, in view of Mishra et al. (US pat. # 11,106,620), hereinafter, “Mishra”
12. As per claim 8, Pyeon discloses “The network of claim 1” [See rejection to claim 1 above], but fails to specifically disclose wherein the multiple network nodes include a master network node and subordinate network nodes; wherein a plurality of the subordinate network nodes are each connected to a sensor to provide sensor data to the subordinate node; and wherein the serial data input of the master node is connected to the serial data output of a last subordinate node in the chain of network nodes to receive the sensor data serially from the plurality of subordinate nodes.
Mishra discloses, wherein the multiple network nodes include a master network node and subordinate network nodes; wherein a plurality of the subordinate network nodes are each connected to a sensor to provide sensor data to the subordinate node; and wherein the serial data input of the master node is connected to the serial data output of a last subordinate node in the chain of network nodes to receive the sensor data serially from the plurality of subordinate nodes (see col. 6, lines 27-38, which discloses “FIG. 2 illustrates certain aspects of an apparatus 200 that includes multiple devices 202, and 222.sub.0-222.sub.N coupled to a serial bus 220. The devices 202 and 222.sub.0-222.sub.N may be implemented in one or more semiconductor IC devices, such as an application processor, SoC or ASIC. In various implementations the devices 202 and 222.sub.0-222.sub.N may include, support or operate as a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, RFFE devices, and/or other such components or devices. In some examples, one or more of the slave devices 222.sub.0-222.sub.N may be used to control, manage or monitor a sensor device”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Mishra’s teaching of an apparatus to enable slave devices coupled to a serial bus to be dynamically assigned using a mixed signal device address assignment procedure, into Pyeon’s teaching of a system that includes a memory controller and a plurality of semiconductor devices that are series-connected, for the benefit of improving addressability of slave devices coupled to a serial bus.
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181