DETAILED ACTION
This office action is in response to the application filed on 12/16/2022.
Claims 1-24 are pending in the application and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-24 are rejected under 35 U.S.C. 103 as being unpatentable over Zaks (U.S. Publication 2014/0189330) in view of Official Notice.
Regarding claims 1, 9, and 17, Zaks discloses an apparatus comprising: a retirement circuit [Fig. 7B; the processor includes a retirement unit]; a branch predictor circuit to predict a predicted path for a branch, and cause a speculative processing of the predicted path [paragraphs 0024-0027; a branch predictor predicts a path for a conditional branch and the processor speculatively executes that path]; a decode circuit to decode a single instruction into a decoded instruction, the single instruction having a field to indicate whether the retirement circuit is to allow retirement of the predicted path for the branch that is a misprediction [paragraphs 0024-0027; a branch instruction includes a field that indicates whether an incorrectly predicted path is allowed to complete execution or if it must be rolled back]; and an execution circuit to execute the decoded instruction to cause: the retirement circuit to allow the retirement of the predicted path that is the misprediction for the branch when the field is set to a first value, and the retirement circuit to disallow the retirement of the predicted path that is the misprediction for the branch when the field is otherwise [paragraphs 0024-0027; depending on the field in the instruction, the processor either completes execution of an incorrectly predicted path or rolls back the processor such that the incorrect path is not executed].
Although not explicitly stated, the claim language appears to require that the branch instruction and the single instruction be different instructions. In other words, the claim requires that a different instruction contains the field that modifies the operation of the branch instruction. This differs from Zaks in that Zaks discloses the field being within the branch instruction itself. However, the examiner takes official notice that using an instruction to modify the behavior of a different instruction (often called a hint instruction) was notoriously well known at the time of the effective filing date of the application. Such operation has benefits relative to using a single instruction, such as the ability to update legacy code without the need to modify the existing branch instruction. Such use of a hint instruction is an architectural decision with well-known trade-offs and would therefore have been obvious to a person having skill in the art.
Regarding claims 2, 10, and 18, Zaks discloses the apparatus of claim 1, wherein the field, when set to the first value, causes the retirement circuit to allow retirement of a predicted taken path that is the misprediction for the branch [paragraphs 0024-0027; in response to the field indicating a certain value, the mispredicted taken path is allowed to execute].
Regarding claims 3, 11, and 19, Zaks discloses the apparatus of claim 2, wherein the field, when set to the first value, causes the retirement circuit to disallow retirement of a predicted not-taken path that is the misprediction for the branch [paragraphs 0024-0027; in response to the field indicating a certain value, the mispredicted not-taken path is not executed].
Regarding claims 4, 12, and 20, Zaks discloses the apparatus of claim 1, wherein the field, when set to the first value, causes the retirement circuit to allow retirement of a predicted not-taken path that is the misprediction for the branch [paragraphs 0024-0027; in response to the field indicating a certain value, the mispredicted not-taken path is allowed to execute].
Regarding claims 5, 13, and 21, Zaks discloses the apparatus of claim 4, wherein the field, when set to the first value, causes the retirement circuit to disallow retirement of a predicted taken path that is the misprediction for the branch [paragraphs 0024-0027; in response to the field indicating a certain value, the mispredicted taken path is not allowed to execute].
Regarding claims 6, 14, and 22, Zaks discloses the apparatus of claim 1, wherein the retirement circuit is to disallow the retirement of the predicted path that is the misprediction for the branch when the field is otherwise by causing cancelation of the speculative processing of the single instruction [paragraphs 0024-0027; a mis-predicted path may be rolled back when the instruction field does not indicate the value].
Regarding claims 7, 15, and 23, Zaks discloses the apparatus of claim 1, wherein the field is a prefix of the single instruction [paragraph 0026; the field may be bits added to an instruction].
Regarding claims 8, 16, and 24, Zaks discloses the apparatus of claim 1, wherein the field is an immediate operand of the single instruction [paragraph 0026; the field contains a value that indicates the type of instruction].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corey Faherty whose telephone number is (571)270-1319. The examiner can normally be reached weekdays between 7:30 and 4:00 ET, with every other Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COREY S FAHERTY/Primary Examiner, Art Unit 2183
Prosecution Insights