DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the communication filed 04/09/2026.
Claims 1-17, 22, 23 have been elected in response to the restriction requirement.
Claims 18-21, 24, 25 have been withdrawn from consideration.
Claims 1-17, 22, 23 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17, 22, 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the one or more processing elements" in line 9 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-17 depend either directly or indirectly on claim 1 and are rejected under 35 U.S.C. 112(b) as a result.
Claim 22 recites the limitation "the one or more processing elements" in line 8 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 23 is a storage medium claim incorporating the limitations of claim 22 and lacks antecedent basis as a result.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1-17, 22, 23 would be allowable if amended to overcome the rejections under 35 U.S.C. 112(b) set forth in this OFFICE ACTION.
As per claim 1, the examiner found no prior arts that teach or fairly suggest, either alone or in combination, each and every limitations of the claim when the claim is taken into the consideration as a whole. In particular, no prior arts teach “extract a state of the computational device, the state comprising at least one of present and previous values transmitted via the connections between the processing elements and state contained within the one or more processing elements”.
Claims 2-17 depend either directly or indirectly on claim 1 and are allowable as a result.
Claims 22 and 23 are a method claim and a storage medium claim corresponding to the apparatus claim 1 and are allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
PG Pub. 2021/0,173,738 A1 discloses incorporating a checker core for fault tolerant processing, wherein the checker core receives committed instruction packets from a processor core and check the committed instruction packets for errors. The processor copies a corrected portion of an architectural state from the checker core to the processor core in response to detection of an error.
US Pat. 10,909,006 B2 discloses incorporating checker processor to detect an error when a mismatch is detected between a main processor and the checker processor. In response to the error, the processor restores previous architectural state to the main processor from an earlier point of program execution.
PG Pub. 2014/0,344,552 A1 discloses systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system.
PG Pub. 2014/0,136,895 A1 discloses method for a processing element to rollback to a checkpoint in response to a detection of a soft error.
PG Pub. 2007/0,334,435 A1 discloses processing units capable of rapid recovery from soft faults by retrieving control and logic state variable data from internal memory locations such as a high integrity random access memory.
PG Pub. 2005/0,050,304 A1 discloses a method of recovering from transient hardware faults of a processor by restoring the processor state corresponding to a previous instruction using data from the history buffer.
EP 2,869,202 A1 discusses a method for transient fault recovery by saving the current state of the CPU in a memory device at various points in the execution of the program code and reloading the CPU state with the last check-point when a transient fault is detected.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAE M KO whose telephone number is (571)270-3886. The examiner can normally be reached M-F 9 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAE M KO/Primary Examiner, Art Unit 2114
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