DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
Response to Amendment
With respect to the double patenting rejections, necessary amendments have been made to overcome the rejections; the rejections have been withdrawn.
With respect to the 112(b) rejections, necessary amendments have been made to overcome the rejections; the rejection have been withdrawn.
With respect to the 35 U.S.C. 101 rejections, necessary amendments have been made to overcome the rejections; the rejections have been withdrawn.
With respect to the 35 U.S.C. 103 rejections, the arguments are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of “Multitenancy” (Wikipedia, revised on 12 October 2022).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7, 9-23 are rejected under 35 U.S.C. 103 as being unpatentable over Bulygin et al (US 20200074086 A1) in view of “Multitenancy” (Wikipedia, revised on 12 October 2022) from henceforth referred to as Tenant-NPL
Per claim 1, Bulygin teaches:
An apparatus for monitoring a processing device from a trusted domain, the apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to: ([0049] methods may be performed by executing stored instructions with one or more logic devices (e.g., processors) in combination with one or more additional hardware elements such as storage devices, memory; [0023] communications is conducted over an authenticated channel)
receive a request for monitoring the processing device from a … virtual machine executing in the trusted domain; authenticate the request; ([0023] monitoring can be done remotely in which the host operating system is located remotely in a virtual machine or other cloud-hosted services and communicate over authenticated channel)
responsive to authenticating the request, trigger execution of an in-field scan circuitry integrated in the processing device during runtime operation of the processing device while the … virtual machine remains in an active execution state in the trusted domain; ([0025] responsive to a request from a third party tool, a local security agent may be launched in order to scan the host devices to collect information ([0044] the method in which it collects the data may include security mechanisms built-in to hardware and/or firmware by manufacturer of the hardware/firmware, which the Examiner interprets as including the in-field scan circuitry); if the virtual machine is not active, it would not be able to send a request to trigger the testing; [0023] the information such as firmware code and data of the host device may be extracted, along with configuration, timing, interrupts, execution counters, and related statistics of the host device may be collected)
obtain information from the in-field scan circuitry on a failure report related to a component of the processing device, with a possible failure having occurred at runtime of the processing device; and (FIG. 3, step 306, the system receives information from host device; [0044] the method collection can be performed via the in-field scan circuitry built in to the hardware; FIG. 3, step 316, [0036] the collected information is displayed in a report)
provide the information on the failure report to the … virtual machine in the trusted domain. ([0036] the report is transmitted and may be provided to a user interface in which an administrator or other users can view the result of the analysis; [0023] the remote monitoring can be conducted locally through a virtual machine)
Bulygin fails to teach
tenant virtual machine
However, Tenant-NPL teaches
tenant virtual machine (top of page 4, virtualized multitenancy).
It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Bulygin with the teaching of Tenant-NPL in order to teach the use of tenant virtual machine because Bulygin already teaches the use of “virtual machines” (Bulygin, [0023]) and does not restrict it to the use of a dedicated virtual machine. Thus, the use of a tenant virtual machine which involves multiple isolated instances of the application to run on more servers (Tenant-NPL, top of page 4) is an implementation choice for the claimed invention in Bulygin, for those who want to reap in the benefits of multitenacy (Tenant-NPL, top of page 4).
Per claim 2, Bulygin in view of Tenant-NPL teaches:
The apparatus of claim 1, wherein the machine-readable instructions further comprise instructions to determine information on a microcode update to be applied to the processing device to remedy a failure related to the component, and to configure the processing device to apply the microcode update (Bulygin, [0048] “When weaknesses, vulnerabilities, or misconfigurations in a system are identified as described above, a virtual patching capability may be deployed as an emergency stop gap to the risk until a more permanent fix is available from manufacturers of the system”)
Per claim 3, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 1, wherein the machine-readable instructions further comprise instructions to decode the request. (Bulygin, [0023] communication is held over an authenticated channel)
Per claim 4, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 1, wherein the machine-readable instructions further comprise instructions to forward information on the request to a secure arbitration module for processing the request based on a microcode routine associated with the request (Bulygin, [0025] local security agent is used as a secure arbitration module in which the request can be passed to the local security agent and based on the microcode routine associated with the request, the security agent may conduct different types of scans)
Per claim 5, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 4, wherein the machine-readable instructions further comprise instructions to receive information on the failure report from the secure arbitration module (Bulygin, [0024] local security agent collect information on the failure report and send the info to analysis services such as those on a cloud-hosted service)
Per claim 7, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 1, wherein the information on the failure report related to the component is based on a failure related to the component occurring in the field. (Bulygin, [0015] the monitoring and analysis can monitor runtime behavior performance in order to detect any vulnerabities)
Per claim 9, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 1, wherein the machine-readable instructions comprise instructions to obtain the information on the failure report related to the component in response to an interrupt raised by the in-field scan circuitry of the processing device. (Bulygin, [0023] during the scan, information related to vulnerabilities are captured, including interrupts; Bulygin, [0035] the information is collected in a report)
Per claim 10, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 2, wherein the machine-readable instructions comprise instructions to determine the information on the microcode update to be applied to the processing device to remedy the failure related to the component based on a mapping between failures and microcode updates. (Bulygin, [0048] the virtual patch concept involves identifying the vulnerability or misconfiguration and making specific modifications to the firmware or hardware settings such that the risk of an attack is removed; Bulygin, [0045] this includes analyzing the firmware components against others that are known to be good as well as keeping a database of independently collected measurements of firmware from a plurality of host devices that is integrated into the system backend along with information about the measurement source for each firmware measurement and enabling integrity checks of operational systems against the previously known measurements)
Per claim 11, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 10, wherein the machine-readable instructions comprise instructions to update the mapping between the failures and microcode updates. (Bulygin, [0045] adaptive whitelisting may be performed, which automatically incorporates measurements that meet a set of criteria into the expected values for a host)
Per claim 12, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 10, wherein the mapping is an operator- defined policy supplied by an operator of a computer system comprising the processing device. (Bulygin, [0045] the database with the mapping can be customized to be organization-specific)
Per claim 13, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 1, wherein the machine-readable instructions comprise instructions to obtain second information on a failure of a component of the processing device occurring in other computer systems, to determine information on a microcode update to be applied to the processing device to remedy the failure related to the component included in the second information, and to configure the processing device to apply the microcode update. (Bulygin, [0048] when weaknesses, vulnerabilities, or misconfigurations in a system are identified, specific modifications to the firmware or hardware settings are identified and adjusted in order to fix the issue)
Per claim 14, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 2, wherein the microcode update affects one or more elements of the group of
an operating frequency of the component of the processing device,
a use of one or more components of the processing device for performing an instruction being exposed by an instruction set architecture of the processing device,
instructions to emulate a functionality originally provided by the component,
a shared use of one or more components of the processing device in simultaneous multithreading, or
instructions being exposed by an instruction set architecture of the processing device.
(Bulygin, [0048] micro-code patch for a specific CPU vulnerability or enabling a BIOS write protect bit which when not enabled exposes a firmware storage control vulnerability. Instructions exposed through instruction set architecture (ISA) can be used for exploitation attempts and so the micro-code patch can help prevent such vulnerability attempts)
Per claim 15, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 2, wherein the microcode update relates to one or more elements of the group of
an input/output controller of the processing device, affecting the use of at least a part of an interface being coupled to the processing device,
a memory controller of the processing device, affecting the use of at least a portion of memory included in a computer system comprising the processing device, or
a storage controller of the processing device, affecting the use of at least a portion of storage circuitry included in a computer system comprising the processing device.
(Bulygin, [0048] microcode patch may enable a BIOS write protect bit)
Per claim 16, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 2, wherein the microcode update is configured to disable the component or portions of logic within the component. (Bulygin, [0015] may disable the network interface through a hardware interface in order to isolate the affected component)
Per claim 17, Bulygin in view of Tenant-NPL teaches:
The apparatus according to claim 1, wherein the processing device is an XPU, the XPU being one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU),an Artificial Intelligence (AI) accelerator, an accelerator card and offloading circuitry. (Bulygin, [0048] processing device is a CPU)
As per claim 18, the claim recites similar claim limitation as claim 1. Claim 18 further recites
…a plurality of processing devices…
…a plurality of components of the plurality of processing devices
…plurality of failure reports…
(Bulygin, [0016] the security monitoring mechanism may be deployed for use by multiple organizations and may include one or more host devices such as laptops, desktop computers, and/or other computing devices. A local agent may be installed on each of the host devices in each group in order to collect information from the respective host devices).
Per claim 19, Bulygin in view of Tenant-NPL teaches:
A computer system comprising the apparatus according to claim 1 and the processing device (Bulygin, [0016] host devices)
Per claim 20, Bulygin in view of Tenant-NPL teaches:
The computer system according to claim 19, wherein the apparatus is implemented as part of a system firmware of the computer system. (Bulygin [0044] method includes accessing a state and configuration of security mechanisms built-in to hardware and/or firmware by manufacturers of the hardware/firmware)
Per claim 21, the claim recites similar claim limitation as claim 1 and thus is rejected for similar reasons.
Per claim 22, Bulygin in view of Tenant-NPL teaches:
A non-transitory, computer-readable medium comprising a program code that, when the program code is executed on a processor, a computer, or a programmable hardware component, causes the processor, computer, or programmable hardware component to perform the method of claim 21. (Bulygin, [0004] includes a processor and a storage device storing instructions executable by the processor to collect firmware and/or hardware information relating to the client system and transmit, via the data interface, to a remote device)
Per claim 23, Bulygin in view of Tenant-NPL teaches:
A method for monitoring a processing device from an application in a trusted domain, the method comprising
transmitting, by a tenant virtual machine executing in a trusted domain, a request for monitoring the processing device in the trusted domain, the request causing execution of in-field scan circuitry integrated in the processing device during runtime operation of the processing device while the tenant virtual machine remains in an active execution state in the trusted domain; and (Bulygin, [0023] monitoring can be done remotely in which the host operating system is located in a virtual machine over authenticated channel; Bulygin, [0025] the monitoring request is sent from the virtual machine to the local security agent; if the virtual machine is not active, it would not be able to transmit the request; Bulygin, [0044] information may be collected from the security mechanisms built-in to hardware and/or firmware by manufacturers of the hardware/firmware; Bulygin, [0015] monitoring can collect runtime behavior; Tenant-NPL, top of page 4, virtualized multitenancy)
receiving, by the tenant virtual machine in the trusted domain, information on a failure report about the processing device from the in-field scan circuitry. (Bulygin, [0036] the report is generated from the gathered information; Tenant-NPL, top of page 4, virtualized multitenancy)
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bulygin et al (US 20200074086 A1) in view of “Multitenancy” (Wikipedia, revised on 12 October 2022) from henceforth referred to as Tenant-NPL in further view of Kuo (US 20070283222 A1)
Per claim 6,
Bulygin fails to teach
wherein the information on the failure report related to the component comprises information on a circuit-level failure affecting the component.
However, Kuo teaches
wherein the information on the failure report related to the component comprises information on a circuit-level failure affecting the component. (Kuo, [0060] errors due to design defects)
It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Bulygin with the teaching of Kuo in order to teach capturing information related to circuit-level failure when collecting vulnerability data because design defects may add vulnerabilities. By addressing them and changing the logic paths through patches, the system data signal is more likely to follow defect free logic paths (Kuo, [0060]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Bulygin et al (US 20200074086 A1) in view of “Multitenancy” (Wikipedia, revised on 12 October 2022) from henceforth referred to as Tenant-NPL in further view of Shanbhogue et al (US 20160364308 A1)
Per claim 8, Bulygin teaches
The apparatus according to claim 1, wherein the machine-readable instructions comprise instructions to obtain the information on the failure report related to the component of the processing device from the in-field scan circuitry of the processing device ([0036] a report on vulnerabilities is made through information gathered by the local security agent; [0044] information may be collected from the built-in security mechanisms by manufacturers of the hardware/software)
Bullygin fails to teach
by reading a register or memory region associated with the in-field scan circuitry.
However, Shanbhogue teaches
by reading a register or memory region associated with the in-field scan circuitry. ([0015] inventive concept is regarding enabling multiple types of in-field testing including built-in self-tests; [0025] control registers can be used to hold test results)
It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Bulygin with the teaching of Shanbhogue in order to make the information from the built-in self-test accessible (Shanbhogue [0025]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAYO LISA RUSIN whose telephone number is (703)756-1679. The examiner can normally be reached Monday-Friday 8:30 - 5:00 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.L.R./ Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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