DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This Office Action is in response to the application filed on December 20, 2022. Claims 1-20 are presently pending and are presented for examination.
Information Disclosure Statement
The information disclosure statements (IDSs) were submitted on January 27, 2023, September 8, 2023, June 7, 2024, September 20, 2024, May 14, 2025, and September 22, 2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Priority
Request for priority to Provisional App. No. 63/042,566 dated June 23, 2020 is acknowledged. Examiner notes Applicant may be requested to perfect one or more of the claims in the situation where applied prior art has priority falling between the filing date of the non-provisional application the date of the provisional application. No action by Applicant is requested at this time.
Additionally, Applicant’s request for priority to PCT/JP2021/008011 dated March 2, 2021 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 4, 10-14, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Pub. No. 2020/0249663 (hereinafter, “Liu”).
Regarding claim 1, Liu discloses A simulation device (see at least [0046] and the publication generally; the digital model) comprising circuitry configured to:
execute a first simulation of a first control of a first machine, wherein the first control is executed by a first controller (see at least [0010], [0019], and [0044]-[0045]; any one of the special devices may be considered the first machine with a first PLC facilitating digital twinning of the first machine and corresponding virtual model);
execute a second simulation of a second control of a second machine, wherein the second control is executed by a second controller so that the second machine operates in collaboration with the first machine (see at least [0010], [0019], and [0044]-[0045]; any one of the special devices may be considered the second machine with another PLC facilitating digital twinning of the second machine and corresponding virtual model); and
control progress of the first simulation and progress of the second simulation to maintain a simulated ratio of a progress speed of the first simulation and a progress speed of the second simulation to be equal to a ratio of a progress speed of the first control and a progress speed of the second control (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning).
Claims 19 and 20 are rejected under essentially the same reasoning as claim 1. Additionally, Liu discloses a PLC system which necessarily includes a non-transitory computer readable medium or equivalent; see at least Liu at [0010].
Regarding claim 2, Liu discloses all of the limitations of claim 1. Additionally, Liu discloses
wherein the first control includes first set of cycles (see at least [0044]-[0046]; control processes (i.e., cycles) for the first machine are monitored and synchronized),
wherein the second control includes second set of cycles (see at least [0044]-[0046]; control processes (i.e., cycles) for the second machine are monitored and synchronized), and
wherein the circuitry is configured to control an execution timing of each of the first set of cycles in the first simulation and an execution timing of each of the second set of cycles in the second simulation to maintain the simulated ratio to be equal to the ratio (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning).
Regarding claim, 3 discloses all of the limitations of claim 1. Additionally, Liu discloses
wherein the first controller is configured to execute each of the first set of cycles after a first control period (see at least [0019]; each set of cycles is executed responsive to a previous control concluding through the line),
wherein the second controller is configured to execute each of the second set of cycles after a second control period (see at least [0019]; each set of cycles is executed responsive to a previous control concluding through the line),
wherein the circuitry is configured to:
execute each of the first set of cycles without waiting for a completion of the first control period in the first simulation (see at least [0044]-[0046]; the simulation occurs simultaneously rather than after);
execute each of the second set of cycles without waiting for a completion of the second control period in the second simulation (see at least [0044]-[0046]; the simulation occurs simultaneously rather than after);
control the execution timing of each of the first set of cycles in the first simulation and the execution timing of each of the second set of cycles in the second simulation to maintain the simulated ratio to be equal to the ratio based on the first control period and the second control period (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning).
Regarding claim 5, Liu discloses all of the limitations of claim 1. Additionally, Liu discloses wherein the circuitry is further configured to simulate an operation of the first machine and an operation of the second machine based on a result of the first simulation and a result of the second simulation (see at least [0021]; the process is iterative and new simulations are based on past results).
Regarding claim 6, Liu discloses all of the limitations of claim 5. Additionally, Liu discloses wherein the circuitry is configured to simulate the operation of the first machine and the operation of the second machine in response to determining that both the result of the first simulation and the result of the second simulation are updated (see at least [0021]; the process is iterative and new simulations are based on past results).
Regarding claim 7, Liu discloses all of the limitations of claim 1. Additionally, Liu discloses wherein the circuitry is further configured to simulate communication executed between the first controller and the second controller during execution of the first simulation and the second simulation (see at least [0010], [0019], and [0044]-[0045]; communication between the different devices is facilitated during the simulation and synchronization processes).
Regarding claim 8, Liu discloses all of the limitations of claim 7. Additionally, Liu discloses wherein the circuitry is configured to:
generate communication data for the communication by executing at least a part of the first simulation (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning); and
acquire the generated communication data after a lapse of a predetermined virtual delay time to execute at least a part of the second simulation based on the acquired communication data (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning. Examiner notes that these limitations are necessary for the synchronization).
Regarding claim 9, Liu discloses all of the limitations of claim 8. Additionally, Liu discloses wherein the circuitry is further configured to:
store, in a communication buffer, communication data generated by executing at least the part of the first simulation (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning. Examiner notes that this step is needed for synchronization);
count a number of communication cycles after the communication data is stored in the communication buffer (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning Examiner notes that this step is needed for synchronization); and
acquire, in response to determining that the number of communication cycles becomes a number corresponding to the virtual delay time, the stored communication data to execute at least the part of the second simulation based on the acquired communication data (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning Examiner notes that this step is needed for synchronization).
Regarding claim 15, Liu discloses all of the limitations of claim 1. Additionally, Liu discloses wherein the circuitry is configured to, in response to receiving a designation of individual simulation, execute the first simulation regardless of the progress of the second simulation (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning).
Regarding claim 16, Liu discloses all of the limitations of claim 8. Additionally, Liu discloses A control system comprising: the simulation device according to claim 8; and the first controller and the second controller, wherein the circuitry is further configured to set the virtual delay time to correspond to a communication delay time between the first controller and the second controller (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning).
Regarding claim 18, Liu discloses all of the limitations of claim 1. Additionally, Liu discloses A control system comprising:
the simulation device according to claim 1 (see at least the citations above pertaining to claim 1); and
the first controller and the second controller, wherein the circuitry is further configured to generate a comparison image that compares the progress speed of the first control, the progress speed of the second control, the progress speed of the first simulation, and the progress speed of the second simulation (see at least [0044]-[0046]; synchronization between the first machine and first simulation, second machine and second simulation, and relationship therebetween is maintained in order to facilitate digital twinning).
Allowable Subject Matter
Each of claims 4, 10-14, and 17 is objected to as depending from a rejected claim but would be allowable if re-written in independent form including all intervening claims. Examiner will provide specific reasons for allowability when one or more claims is found to be in a state of allowance.
Additional Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and may be found on the accompanying PTO-892 Notice of References Cited:
12,216,460 which pertains to simulating an automation system via digital twins.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIFFANY P YOUNG whose telephone number is (313)446-6575. The examiner can normally be reached M-R 6:30 AM- 4:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helal Algahaim can be reached at (571) 270-5227. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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TIFFANY YOUNG
Primary Examiner
Art Unit 3666
/TIFFANY P YOUNG/Primary Examiner, Art Unit 3666
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